blob: bc2d441a5e00f423524280c054934fc2b0026506 [file] [log] [blame]
Heiko Schocher4e43b2e2010-07-07 12:26:34 +02001/*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 *
4 * (C) Copyright 2010
5 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocher4e43b2e2010-07-07 12:26:34 +02008 */
9/*
10 * ve8313 board configuration file
11 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
Kim Phillipsfdfaa292015-03-17 12:00:45 -050016#define CONFIG_DISPLAY_BOARDINFO
17
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020018/*
19 * High Level Configuration Options
20 */
21#define CONFIG_E300 1
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020022#define CONFIG_MPC831x 1
23#define CONFIG_MPC8313 1
24#define CONFIG_VE8313 1
25
Wolfgang Denk2ae18242010-10-06 09:05:45 +020026#ifndef CONFIG_SYS_TEXT_BASE
27#define CONFIG_SYS_TEXT_BASE 0xfe000000
28#endif
29
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020030#define CONFIG_PCI 1
Gabor Juhos842033e2013-05-30 07:06:12 +000031#define CONFIG_PCI_INDIRECT_BRIDGE 1
Kumar Galaa2243b82010-08-19 01:48:14 -050032#define CONFIG_FSL_ELBC 1
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020033
34#define CONFIG_BOARD_EARLY_INIT_F 1
35
36/*
37 * On-board devices
38 *
39 */
40#define CONFIG_83XX_CLKIN 32000000 /* in Hz */
41
42#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
43
44#define CONFIG_SYS_IMMR 0xE0000000
45
46#define CONFIG_SYS_MEMTEST_START 0x00001000
47#define CONFIG_SYS_MEMTEST_END 0x07000000
48
49#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */
50#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */
51
52/*
53 * Device configurations
54 */
55
56/*
57 * DDR Setup
58 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -050059#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020060#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
61#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
62
63/*
64 * Manually set up DDR parameters, as this board does not
65 * have the SPD connected to I2C.
66 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -050067#define CONFIG_SYS_DDR_SIZE 128 /* MB */
Joe Hershberger2e651b22011-10-11 23:57:31 -050068#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020069 | CSCONFIG_AP \
Joe Hershberger2fef4022011-10-11 23:57:29 -050070 | CSCONFIG_ODT_RD_NEVER \
71 | CSCONFIG_ODT_WR_ALL \
Joe Hershbergerbe29fa72011-10-11 23:57:26 -050072 | CSCONFIG_ROW_BIT_13 \
73 | CSCONFIG_COL_BIT_10)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020074 /* 0x80840102 */
75
76#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Joe Hershbergerbe29fa72011-10-11 23:57:26 -050077#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
78 | (0 << TIMING_CFG0_WRT_SHIFT) \
79 | (3 << TIMING_CFG0_RRT_SHIFT) \
80 | (2 << TIMING_CFG0_WWT_SHIFT) \
81 | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
82 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
83 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
84 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020085 /* 0x0e720802 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -050086#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
87 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
88 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
89 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
90 | (6 << TIMING_CFG1_REFREC_SHIFT) \
91 | (2 << TIMING_CFG1_WRREC_SHIFT) \
92 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
93 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020094 /* 0x26256222 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -050095#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
96 | (5 << TIMING_CFG2_CPO_SHIFT) \
97 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
98 | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
99 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
100 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
101 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200102 /* 0x029028c7 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500103#define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
104 | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200105 /* 0x03202000 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500106#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200107 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500108 | SDRAM_CFG_DBW_32)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200109 /* 0x43080000 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500110#define CONFIG_SYS_SDRAM_CFG2 0x00401000
111#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
112 | (0x0232 << SDRAM_MODE_SD_SHIFT))
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200113 /* 0x44400232 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500114#define CONFIG_SYS_DDR_MODE_2 0x8000C000
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200115
116#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
117 /*0x02000000*/
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500118#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200119 | DDRCDR_PZ_NOMZ \
120 | DDRCDR_NZ_NOMZ \
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500121 | DDRCDR_M_ODR)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200122 /* 0x73000002 */
123
124/*
125 * FLASH on the Local Bus
126 */
127#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
128#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
129#define CONFIG_SYS_FLASH_BASE 0xFE000000
130#define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */
131#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
132#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
133
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500134#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500135 | BR_PS_16 /* 16 bit */ \
136 | BR_MS_GPCM /* MSEL = GPCM */ \
137 | BR_V) /* valid */
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200138#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500139 | OR_GPCM_CSNT \
140 | OR_GPCM_ACS_DIV4 \
141 | OR_GPCM_SCY_5 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500142 | OR_GPCM_TRLX_SET \
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500143 | OR_GPCM_EAD)
144 /* 0xfe000c55 */
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200145
146#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500147#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200148
149#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
150#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */
151
152#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
153#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
154
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200155#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200156
157#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
158#define CONFIG_SYS_RAMBOOT
159#endif
160
161#define CONFIG_SYS_INIT_RAM_LOCK 1
162#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500163#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200164
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500165#define CONFIG_SYS_GBL_DATA_OFFSET \
166 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200167#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
168
169/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
170#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
171#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
172
173/*
174 * Local Bus LCRR and LBCR regs
175 */
176#define CONFIG_SYS_LCRR_EADC LCRR_EADC_3
177#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
178
179#define CONFIG_SYS_LBC_LBCR 0x00040000
180
181#define CONFIG_SYS_LBC_MRTPR 0x20000000
182
183/*
184 * NAND settings
185 */
186#define CONFIG_SYS_NAND_BASE 0x61000000
187#define CONFIG_SYS_MAX_NAND_DEVICE 1
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200188#define CONFIG_CMD_NAND 1
189#define CONFIG_NAND_FSL_ELBC 1
190#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
191
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500192#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
193 | BR_PS_8 \
194 | BR_DECC_CHK_GEN \
195 | BR_MS_FCM \
196 | BR_V) /* valid */
197 /* 0x61000c21 */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500198#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500199 | OR_FCM_BCTLD \
200 | OR_FCM_CHT \
201 | OR_FCM_SCY_2 \
202 | OR_FCM_RST \
203 | OR_FCM_TRLX)
204 /* 0xffff90ac */
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200205
206#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
207#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
208#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
209#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
210
211#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500212#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200213
214#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
215#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
216
217/* CS2 NvRAM */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500218#define CONFIG_SYS_BR2_PRELIM (0x60000000 \
219 | BR_PS_8 \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200220 | BR_V)
221 /* 0x60000801 */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500222#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500223 | OR_GPCM_CSNT \
224 | OR_GPCM_XACS \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200225 | OR_GPCM_SCY_3 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500226 | OR_GPCM_TRLX_SET \
227 | OR_GPCM_EHTR_SET \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200228 | OR_GPCM_EAD)
229 /* 0xfffe0937 */
230/* local bus read write buffer mapping SRAM@0x64000000 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500231#define CONFIG_SYS_BR3_PRELIM (0x62000000 \
232 | BR_PS_16 \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200233 | BR_V)
234 /* 0x62001001 */
235
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500236#define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB \
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500237 | OR_GPCM_CSNT \
238 | OR_GPCM_XACS \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200239 | OR_GPCM_SCY_15 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500240 | OR_GPCM_TRLX_SET \
241 | OR_GPCM_EHTR_SET \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200242 | OR_GPCM_EAD)
243 /* 0xfe0009f7 */
244
245/* pass open firmware flat tree */
246#define CONFIG_OF_LIBFDT 1
247#define CONFIG_OF_BOARD_SETUP 1
248#define CONFIG_OF_STDOUT_VIA_ALIAS 1
249
250/*
251 * Serial Port
252 */
253#define CONFIG_CONS_INDEX 1
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200254#define CONFIG_SYS_NS16550_SERIAL
255#define CONFIG_SYS_NS16550_REG_SIZE 1
256#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
257
258#define CONFIG_SYS_BAUDRATE_TABLE \
259 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
260
261#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
262#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
263
264/* Use the HUSH parser */
265#define CONFIG_SYS_HUSH_PARSER
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200266
267#if defined(CONFIG_PCI)
268/*
269 * General PCI
270 * Addresses are mapped 1-1.
271 */
272#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
273#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
274#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
275#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
276#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
277#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500278#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
279#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
280#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200281
282#define CONFIG_PCI_PNP /* do pci plug-and-play */
283#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
284#endif
285
286/*
287 * TSEC
288 */
289#define CONFIG_TSEC_ENET /* TSEC ethernet support */
290
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200291
292#define CONFIG_TSEC1
293#ifdef CONFIG_TSEC1
294#define CONFIG_HAS_ETH0
295#define CONFIG_TSEC1_NAME "TSEC1"
296#define CONFIG_SYS_TSEC1_OFFSET 0x24000
297#define TSEC1_PHY_ADDR 0x01
298#define TSEC1_FLAGS 0
299#define TSEC1_PHYIDX 0
300#endif
301
302/* Options are: TSEC[0-1] */
303#define CONFIG_ETHPRIME "TSEC1"
304
305/*
306 * Environment
307 */
308#define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500309#define CONFIG_ENV_ADDR \
310 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200311#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
312#define CONFIG_ENV_SIZE 0x4000
313/* Address and size of Redundant Environment Sector */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500314#define CONFIG_ENV_OFFSET_REDUND \
315 (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200316#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
317
318#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
319#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
320
321/*
322 * BOOTP options
323 */
324#define CONFIG_BOOTP_BOOTFILESIZE
325#define CONFIG_BOOTP_BOOTPATH
326#define CONFIG_BOOTP_GATEWAY
327#define CONFIG_BOOTP_HOSTNAME
328
329/*
330 * Command line configuration.
331 */
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200332#define CONFIG_CMD_DHCP
333#define CONFIG_CMD_MII
334#define CONFIG_CMD_PING
335#define CONFIG_CMD_PCI
336
337#define CONFIG_CMDLINE_EDITING 1
338#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
339
340/*
341 * Miscellaneous configurable options
342 */
343#define CONFIG_SYS_LONGHELP /* undef to save memory */
344#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200345#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
346
347#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
348#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
349#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200350
351/*
352 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700353 * have to be in the first 256 MB of memory, since this is
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200354 * the maximum mapped by the Linux kernel during initialization.
355 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500356 /* Initial Memory map for Linux*/
357#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200358
359/* 0x64050000 */
360#define CONFIG_SYS_HRCW_LOW (\
361 0x20000000 /* reserved, must be set */ |\
362 HRCWL_DDRCM |\
363 HRCWL_CSB_TO_CLKIN_4X1 | \
364 HRCWL_CORE_TO_CSB_2_5X1)
365
366/* 0xa0600004 */
367#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
368 HRCWH_PCI_ARBITER_ENABLE | \
369 HRCWH_CORE_ENABLE | \
370 HRCWH_FROM_0X00000100 | \
371 HRCWH_BOOTSEQ_DISABLE |\
372 HRCWH_SW_WATCHDOG_DISABLE |\
373 HRCWH_ROM_LOC_LOCAL_16BIT | \
374 HRCWH_TSEC1M_IN_MII | \
375 HRCWH_BIG_ENDIAN | \
376 HRCWH_LALE_EARLY)
377
378/* System IO Config */
379#define CONFIG_SYS_SICRH (0x01000000 | \
380 SICRH_ETSEC2_B | \
381 SICRH_ETSEC2_C | \
382 SICRH_ETSEC2_D | \
383 SICRH_ETSEC2_E | \
384 SICRH_ETSEC2_F | \
385 SICRH_ETSEC2_G | \
386 SICRH_TSOBI1 | \
387 SICRH_TSOBI2)
388 /* 0x010fff03 */
389#define CONFIG_SYS_SICRL (SICRL_LBC | \
390 SICRL_SPI_A | \
391 SICRL_SPI_B | \
392 SICRL_SPI_C | \
393 SICRL_SPI_D | \
394 SICRL_ETSEC2_A)
395 /* 0x33fc0003) */
396
397#define CONFIG_SYS_HID0_INIT 0x000000000
398#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
399 HID0_ENABLE_INSTRUCTION_CACHE)
400
401#define CONFIG_SYS_HID2 HID2_HBE
402
403#define CONFIG_HIGH_BATS 1 /* High BATs supported */
404
405/* DDR @ 0x00000000 */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500406#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500407#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
408 | BATU_BL_256M \
409 | BATU_VS \
410 | BATU_VP)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200411
412#if defined(CONFIG_PCI)
413/* PCI @ 0x80000000 */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500414#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500415#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
416 | BATU_BL_256M \
417 | BATU_VS \
418 | BATU_VP)
419#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500420 | BATL_PP_RW \
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500421 | BATL_CACHEINHIBIT \
422 | BATL_GUARDEDSTORAGE)
423#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
424 | BATU_BL_256M \
425 | BATU_VS \
426 | BATU_VP)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200427#else
428#define CONFIG_SYS_IBAT1L (0)
429#define CONFIG_SYS_IBAT1U (0)
430#define CONFIG_SYS_IBAT2L (0)
431#define CONFIG_SYS_IBAT2U (0)
432#endif
433
434/* PCI2 not supported on 8313 */
435#define CONFIG_SYS_IBAT3L (0)
436#define CONFIG_SYS_IBAT3U (0)
437#define CONFIG_SYS_IBAT4L (0)
438#define CONFIG_SYS_IBAT4U (0)
439
440/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500441#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500442 | BATL_PP_RW \
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500443 | BATL_CACHEINHIBIT \
444 | BATL_GUARDEDSTORAGE)
445#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
446 | BATU_BL_256M \
447 | BATU_VS \
448 | BATU_VP)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200449
450/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500451#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200452#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
453
454/* FPGA, SRAM, NAND @ 0x60000000 */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500455#define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200456#define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
457
458#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
459#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
460#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
461#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
462#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
463#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
464#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
465#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
466#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
467#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
468#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
469#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
470#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
471#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
472#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
473#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
474
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200475#define CONFIG_NETDEV eth0
476
477#define CONFIG_HOSTNAME ve8313
478#define CONFIG_UBOOTPATH ve8313/u-boot.bin
479
480#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
481#define CONFIG_BAUDRATE 115200
482
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200483#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200484 "netdev=" __stringify(CONFIG_NETDEV) "\0" \
485 "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \
486 "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200487 "u-boot_addr_r=100000\0" \
488 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200489 "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
490 " +${filesize};" \
491 "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
492 "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \
Joe Hershbergerbe29fa72011-10-11 23:57:26 -0500493 " ${filesize};" \
Marek Vasut5368c552012-09-23 17:41:24 +0200494 "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200495
496#endif /* __CONFIG_H */