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Stefan Roese995b72d2012-05-30 22:59:08 +00001/*
2 * (C) Copyright 2009
3 * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
4 *
Stefan Roese2fbdbda2015-08-18 09:27:17 +02005 * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de>
Stefan Roese995b72d2012-05-30 22:59:08 +00006 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese995b72d2012-05-30 22:59:08 +00008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/*
14 * High Level Configuration Options
15 * (easy to change)
16 */
17#define CONFIG_SPEAR600 /* SPEAr600 SoC */
18#define CONFIG_X600 /* on X600 board */
Stefan Roese9b6aa002015-09-02 11:11:00 +020019#define CONFIG_SYS_THUMB_BUILD
Stefan Roese995b72d2012-05-30 22:59:08 +000020
21#include <asm/arch/hardware.h>
22
23/* Timer, HZ specific defines */
Stefan Roese995b72d2012-05-30 22:59:08 +000024#define CONFIG_SYS_HZ_CLOCK 8300000
25
26#define CONFIG_SYS_TEXT_BASE 0x00800040
27#define CONFIG_SYS_FLASH_BASE 0xf8000000
28/* Reserve 8KiB for SPL */
29#define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */
30#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
31#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
32 CONFIG_SYS_SPL_LEN)
Stefan Roese285e2662015-08-18 09:27:20 +020033#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
Stefan Roese995b72d2012-05-30 22:59:08 +000034#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
35#define CONFIG_SYS_MONITOR_LEN 0x60000
36
37#define CONFIG_ENV_IS_IN_FLASH
38
39/* Serial Configuration (PL011) */
40#define CONFIG_SYS_SERIAL0 0xD0000000
41#define CONFIG_SYS_SERIAL1 0xD0080000
42#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
43 (void *)CONFIG_SYS_SERIAL1 }
44#define CONFIG_PL011_SERIAL
45#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
46#define CONFIG_CONS_INDEX 0
47#define CONFIG_BAUDRATE 115200
48#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
49 57600, 115200 }
50#define CONFIG_SYS_LOADS_BAUD_CHANGE
51
52/* NOR FLASH config options */
53#define CONFIG_ST_SMI
54#define CONFIG_SYS_MAX_FLASH_BANKS 1
55#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
56#define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE }
57#define CONFIG_SYS_MAX_FLASH_SECT 128
58#define CONFIG_SYS_FLASH_EMPTY_INFO
59#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
60#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
61
62/* NAND FLASH config options */
63#define CONFIG_NAND_FSMC
64#define CONFIG_SYS_NAND_SELF_INIT
65#define CONFIG_SYS_MAX_NAND_DEVICE 1
66#define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE
67#define CONFIG_MTD_ECC_SOFT
68#define CONFIG_SYS_FSMC_NAND_8BIT
69#define CONFIG_SYS_NAND_ONFI_DETECTION
Stefan Roese0ddc5a22015-09-02 11:10:59 +020070#define CONFIG_NAND_ECC_BCH
71#define CONFIG_BCH
Stefan Roese995b72d2012-05-30 22:59:08 +000072
73/* UBI/UBI config options */
74#define CONFIG_MTD_DEVICE
75#define CONFIG_MTD_PARTITIONS
76#define CONFIG_RBTREE
77
78/* Ethernet config options */
79#define CONFIG_MII
Stefan Roese995b72d2012-05-30 22:59:08 +000080#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
Stefan Roese995b72d2012-05-30 22:59:08 +000081#define CONFIG_PHY_ADDR 0 /* PHY address */
82#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
83
84#define CONFIG_SPEAR_GPIO
85
86/* I2C config options */
Stefan Roese678398b2014-10-28 12:12:00 +010087#define CONFIG_SYS_I2C
88#define CONFIG_SYS_I2C_DW
Alexey Brodkinf93f5892014-02-10 12:20:11 +040089#define CONFIG_SYS_I2C_BASE 0xD0200000
Stefan Roese995b72d2012-05-30 22:59:08 +000090#define CONFIG_SYS_I2C_SPEED 400000
91#define CONFIG_SYS_I2C_SLAVE 0x02
92#define CONFIG_I2C_CHIPADDRESS 0x50
93
94#define CONFIG_RTC_M41T62 1
95#define CONFIG_SYS_I2C_RTC_ADDR 0x68
96
97/* FPGA config options */
98#define CONFIG_FPGA
99#define CONFIG_FPGA_XILINX
100#define CONFIG_FPGA_SPARTAN3
101#define CONFIG_FPGA_COUNT 1
102
Stefan Roese285e2662015-08-18 09:27:20 +0200103/* USB EHCI options */
104#define CONFIG_USB_EHCI
105#define CONFIG_USB_EHCI_SPEAR
106#define CONFIG_USB_STORAGE
107#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
108
Stefan Roese995b72d2012-05-30 22:59:08 +0000109/*
110 * Command support defines
111 */
112#define CONFIG_CMD_CACHE
113#define CONFIG_CMD_DATE
114#define CONFIG_CMD_DHCP
115#define CONFIG_CMD_ENV
Stefan Roese285e2662015-08-18 09:27:20 +0200116#define CONFIG_CMD_FAT
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530117#define CONFIG_CMD_FPGA_LOADMK
Stefan Roese285e2662015-08-18 09:27:20 +0200118#define CONFIG_CMD_FS_GENERIC
Stefan Roese995b72d2012-05-30 22:59:08 +0000119#define CONFIG_CMD_I2C
Stefan Roese995b72d2012-05-30 22:59:08 +0000120#define CONFIG_CMD_MII
121#define CONFIG_CMD_MTDPARTS
122#define CONFIG_CMD_NAND
Stefan Roese995b72d2012-05-30 22:59:08 +0000123#define CONFIG_CMD_PING
Stefan Roese995b72d2012-05-30 22:59:08 +0000124#define CONFIG_CMD_SAVES
125#define CONFIG_CMD_UBI
126#define CONFIG_CMD_UBIFS
Stefan Roese285e2662015-08-18 09:27:20 +0200127#define CONFIG_CMD_USB
Stefan Roese995b72d2012-05-30 22:59:08 +0000128#define CONFIG_LZO
129
Stefan Roese285e2662015-08-18 09:27:20 +0200130/* Filesystem support (for USB key) */
131#define CONFIG_SUPPORT_VFAT
132#define CONFIG_DOS_PARTITION
133
Stefan Roese995b72d2012-05-30 22:59:08 +0000134#define CONFIG_BOOTDELAY 3
135
136#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
137#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
138
139/*
140 * U-Boot Environment placing definitions.
141 */
142#define CONFIG_ENV_SECT_SIZE 0x00010000
143#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
144 CONFIG_SYS_MONITOR_LEN)
145#define CONFIG_ENV_SIZE 0x02000
146#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
147 CONFIG_ENV_SECT_SIZE)
148#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
149
150/* Miscellaneous configurable options */
151#define CONFIG_ARCH_CPU_INIT
152#define CONFIG_DISPLAY_CPUINFO
153#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
154#define CONFIG_CMDLINE_TAG
155#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
156#define CONFIG_SETUP_MEMORY_TAGS
157#define CONFIG_MISC_INIT_R
158#define CONFIG_BOARD_LATE_INIT
159#define CONFIG_LOOPW /* enable loopw command */
160#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
161#define CONFIG_ZERO_BOOTDELAY_CHECK
Stefan Roese995b72d2012-05-30 22:59:08 +0000162
163#define CONFIG_SYS_MEMTEST_START 0x00800000
164#define CONFIG_SYS_MEMTEST_END 0x04000000
Stefan Roese285e2662015-08-18 09:27:20 +0200165#define CONFIG_SYS_MALLOC_LEN (8 << 20)
Stefan Roese995b72d2012-05-30 22:59:08 +0000166#define CONFIG_IDENT_STRING "-SPEAr"
167#define CONFIG_SYS_LONGHELP
Stefan Roese995b72d2012-05-30 22:59:08 +0000168#define CONFIG_CMDLINE_EDITING
Stefan Roese285e2662015-08-18 09:27:20 +0200169#define CONFIG_AUTO_COMPLETE
Stefan Roese995b72d2012-05-30 22:59:08 +0000170#define CONFIG_SYS_CBSIZE 256
171#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
172 sizeof(CONFIG_SYS_PROMPT) + 16)
173#define CONFIG_SYS_MAXARGS 16
174#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
175#define CONFIG_SYS_LOAD_ADDR 0x00800000
176#define CONFIG_SYS_CONSOLE_INFO_QUIET
Stefan Roese995b72d2012-05-30 22:59:08 +0000177
178/* Use last 2 lwords in internal SRAM for bootcounter */
179#define CONFIG_BOOTCOUNT_LIMIT
Stefan Roese2fbdbda2015-08-18 09:27:17 +0200180#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SRAM_BASE + \
181 CONFIG_SRAM_SIZE)
Stefan Roese995b72d2012-05-30 22:59:08 +0000182
183#define CONFIG_HOSTNAME x600
184#define CONFIG_UBI_PART ubi0
185#define CONFIG_UBIFS_VOLUME rootfs
186
Stefan Roese995b72d2012-05-30 22:59:08 +0000187#define MTDIDS_DEFAULT "nand0=nand"
188#define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)"
189
190#define CONFIG_EXTRA_ENV_SETTINGS \
191 "u-boot_addr=1000000\0" \
Anatolij Gustschin4a8c3f62014-10-24 20:13:51 +0200192 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \
Stefan Roese995b72d2012-05-30 22:59:08 +0000193 "load=tftp ${u-boot_addr} ${u-boot}\0" \
Anatolij Gustschin4a8c3f62014-10-24 20:13:51 +0200194 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
195 " +${filesize};" \
196 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
197 "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
Stefan Roese995b72d2012-05-30 22:59:08 +0000198 " ${filesize};" \
Anatolij Gustschin4a8c3f62014-10-24 20:13:51 +0200199 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
Stefan Roese995b72d2012-05-30 22:59:08 +0000200 " +${filesize}\0" \
201 "upd=run load update\0" \
Anatolij Gustschin4a8c3f62014-10-24 20:13:51 +0200202 "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \
203 "part=" __stringify(CONFIG_UBI_PART) "\0" \
204 "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \
Stefan Roese995b72d2012-05-30 22:59:08 +0000205 "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
206 "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
207 " ${filesize}\0" \
208 "upd_ubifs=run load_ubifs update_ubifs\0" \
209 "init_ubifs=nand erase.part ubi0;ubi part ${part};" \
210 "ubi create ${vol} 4000000\0" \
211 "netdev=eth0\0" \
212 "rootpath=/opt/eldk-4.2/arm\0" \
213 "nfsargs=setenv bootargs root=/dev/nfs rw " \
214 "nfsroot=${serverip}:${rootpath}\0" \
215 "ramargs=setenv bootargs root=/dev/ram rw\0" \
216 "boot_part=0\0" \
217 "altbootcmd=if test $boot_part -eq 0;then " \
218 "echo Switching to partition 1!;" \
219 "setenv boot_part 1;" \
220 "else; " \
221 "echo Switching to partition 0!;" \
222 "setenv boot_part 0;" \
223 "fi;" \
224 "saveenv;boot\0" \
225 "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \
226 "root=ubi0:rootfs rootfstype=ubifs\0" \
Anatolij Gustschin4a8c3f62014-10-24 20:13:51 +0200227 "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
Stefan Roese995b72d2012-05-30 22:59:08 +0000228 "kernel_fs=/boot/uImage \0" \
229 "kernel_addr=1000000\0" \
Anatolij Gustschin4a8c3f62014-10-24 20:13:51 +0200230 "dtb=" __stringify(CONFIG_HOSTNAME) "/" \
231 __stringify(CONFIG_HOSTNAME) ".dtb\0" \
232 "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \
Stefan Roese995b72d2012-05-30 22:59:08 +0000233 "dtb_addr=1800000\0" \
234 "load_kernel=tftp ${kernel_addr} ${kernel}\0" \
235 "load_dtb=tftp ${dtb_addr} ${dtb}\0" \
236 "addip=setenv bootargs ${bootargs} " \
237 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
238 ":${hostname}:${netdev}:off panic=1\0" \
239 "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \
240 "${baudrate}\0" \
241 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
242 "net_nfs=run load_dtb load_kernel; " \
243 "run nfsargs addip addcon addmtd addmisc;" \
244 "bootm ${kernel_addr} - ${dtb_addr}\0" \
245 "mtdids=" MTDIDS_DEFAULT "\0" \
246 "mtdparts=" MTDPARTS_DEFAULT "\0" \
247 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \
248 " addcon addmisc addmtd;" \
249 "bootm ${kernel_addr} - ${dtb_addr}\0" \
Joe Hershberger949a7712012-11-01 16:54:18 +0000250 "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \
Stefan Roese995b72d2012-05-30 22:59:08 +0000251 "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \
252 "ubifsload ${dtb_addr} ${dtb_fs};\0" \
253 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
254 "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \
255 "bootcmd=run nand_ubifs\0" \
256 "\0"
257
Stefan Roese995b72d2012-05-30 22:59:08 +0000258/* Physical Memory Map */
259#define CONFIG_NR_DRAM_BANKS 1
260#define PHYS_SDRAM_1 0x00000000
261#define PHYS_SDRAM_1_MAXSIZE 0x40000000
262
263#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Stefan Roese2fbdbda2015-08-18 09:27:17 +0200264#define CONFIG_SRAM_BASE 0xd2800000
265/* Preserve the last 2 lwords for the boot-counter */
266#define CONFIG_SRAM_SIZE ((8 << 10) - 0x8)
267#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE
268#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE
Stefan Roese995b72d2012-05-30 22:59:08 +0000269
270#define CONFIG_SYS_INIT_SP_OFFSET \
271 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
272
273#define CONFIG_SYS_INIT_SP_ADDR \
274 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
275
276/*
277 * SPL related defines
278 */
Stefan Roese2fbdbda2015-08-18 09:27:17 +0200279#define CONFIG_SPL_TEXT_BASE 0xd2800b00
280#define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00)
Stefan Roese995b72d2012-05-30 22:59:08 +0000281#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
282#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
283
Stefan Roese2fbdbda2015-08-18 09:27:17 +0200284#define CONFIG_SPL_FRAMEWORK
285#define CONFIG_SPL_NOR_SUPPORT
Stefan Roese995b72d2012-05-30 22:59:08 +0000286#define CONFIG_SPL_SERIAL_SUPPORT
287#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
288#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
Stefan Roese995b72d2012-05-30 22:59:08 +0000289
290/*
291 * Please select/define only one of the following
292 * Each definition corresponds to a supported DDR chip.
293 * DDR configuration is based on the following selection
294 */
295#define CONFIG_DDR_MT47H64M16 1
296#define CONFIG_DDR_MT47H32M16 0
297#define CONFIG_DDR_MT47H128M8 0
298
299/*
300 * Synchronous/Asynchronous operation of DDR
301 *
302 * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
303 * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
304 * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
305 */
306#define CONFIG_DDR_2HCLK 1
307#define CONFIG_DDR_HCLK 0
308#define CONFIG_DDR_PLL2 0
309
310/*
311 * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
312 * or not. Modify/Add to only these macros to define new boot types
313 */
314#define USB_BOOT_SUPPORTED 0
315#define PCIE_BOOT_SUPPORTED 0
316#define SNOR_BOOT_SUPPORTED 1
317#define NAND_BOOT_SUPPORTED 1
318#define PNOR_BOOT_SUPPORTED 0
319#define TFTP_BOOT_SUPPORTED 0
320#define UART_BOOT_SUPPORTED 0
321#define SPI_BOOT_SUPPORTED 0
322#define I2C_BOOT_SUPPORTED 0
323#define MMC_BOOT_SUPPORTED 0
324
325#endif /* __CONFIG_H */