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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 373e526e42e199bed135e8382e15aebcb6557b7b / . / arch / arm / dts / sm8250.dtsi
blob: be970472f6c4e75b5b036aec8b8b2f7c70a63b31 [file] [log] [blame]
Caleb Connolly373e5262023-10-03 12:39:03 +0100[diff] [blame^]1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8#include <dt-bindings/clock/qcom,gcc-sm8250.h>
9#include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10#include <dt-bindings/clock/qcom,rpmh.h>
11#include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
12#include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
13#include <dt-bindings/dma/qcom-gpi.h>
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/interconnect/qcom,osm-l3.h>
16#include <dt-bindings/interconnect/qcom,sm8250.h>
17#include <dt-bindings/mailbox/qcom-ipcc.h>
18#include <dt-bindings/phy/phy-qcom-qmp.h>
19#include <dt-bindings/power/qcom-rpmpd.h>
20#include <dt-bindings/power/qcom,rpmhpd.h>
21#include <dt-bindings/soc/qcom,apr.h>
22#include <dt-bindings/soc/qcom,rpmh-rsc.h>
23#include <dt-bindings/sound/qcom,q6afe.h>
24#include <dt-bindings/thermal/thermal.h>
25#include <dt-bindings/clock/qcom,camcc-sm8250.h>
26#include <dt-bindings/clock/qcom,videocc-sm8250.h>
27
28/ {
29 interrupt-parent = <&intc>;
30
31 #address-cells = <2>;
32 #size-cells = <2>;
33
34 aliases {
35 i2c0 = &i2c0;
36 i2c1 = &i2c1;
37 i2c2 = &i2c2;
38 i2c3 = &i2c3;
39 i2c4 = &i2c4;
40 i2c5 = &i2c5;
41 i2c6 = &i2c6;
42 i2c7 = &i2c7;
43 i2c8 = &i2c8;
44 i2c9 = &i2c9;
45 i2c10 = &i2c10;
46 i2c11 = &i2c11;
47 i2c12 = &i2c12;
48 i2c13 = &i2c13;
49 i2c14 = &i2c14;
50 i2c15 = &i2c15;
51 i2c16 = &i2c16;
52 i2c17 = &i2c17;
53 i2c18 = &i2c18;
54 i2c19 = &i2c19;
55 spi0 = &spi0;
56 spi1 = &spi1;
57 spi2 = &spi2;
58 spi3 = &spi3;
59 spi4 = &spi4;
60 spi5 = &spi5;
61 spi6 = &spi6;
62 spi7 = &spi7;
63 spi8 = &spi8;
64 spi9 = &spi9;
65 spi10 = &spi10;
66 spi11 = &spi11;
67 spi12 = &spi12;
68 spi13 = &spi13;
69 spi14 = &spi14;
70 spi15 = &spi15;
71 spi16 = &spi16;
72 spi17 = &spi17;
73 spi18 = &spi18;
74 spi19 = &spi19;
75 };
76
77 chosen { };
78
79 clocks {
80 xo_board: xo-board {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <38400000>;
84 clock-output-names = "xo_board";
85 };
86
87 sleep_clk: sleep-clk {
88 compatible = "fixed-clock";
89 clock-frequency = <32768>;
90 #clock-cells = <0>;
91 };
92 };
93
94 cpus {
95 #address-cells = <2>;
96 #size-cells = <0>;
97
98 CPU0: cpu@0 {
99 device_type = "cpu";
100 compatible = "qcom,kryo485";
101 reg = <0x0 0x0>;
102 clocks = <&cpufreq_hw 0>;
103 enable-method = "psci";
104 capacity-dmips-mhz = <448>;
105 dynamic-power-coefficient = <105>;
106 next-level-cache = <&L2_0>;
107 power-domains = <&CPU_PD0>;
108 power-domain-names = "psci";
109 qcom,freq-domain = <&cpufreq_hw 0>;
110 operating-points-v2 = <&cpu0_opp_table>;
111 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
112 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
113 #cooling-cells = <2>;
114 L2_0: l2-cache {
115 compatible = "cache";
116 cache-level = <2>;
117 cache-size = <0x20000>;
118 cache-unified;
119 next-level-cache = <&L3_0>;
120 L3_0: l3-cache {
121 compatible = "cache";
122 cache-level = <3>;
123 cache-size = <0x400000>;
124 cache-unified;
125 };
126 };
127 };
128
129 CPU1: cpu@100 {
130 device_type = "cpu";
131 compatible = "qcom,kryo485";
132 reg = <0x0 0x100>;
133 clocks = <&cpufreq_hw 0>;
134 enable-method = "psci";
135 capacity-dmips-mhz = <448>;
136 dynamic-power-coefficient = <105>;
137 next-level-cache = <&L2_100>;
138 power-domains = <&CPU_PD1>;
139 power-domain-names = "psci";
140 qcom,freq-domain = <&cpufreq_hw 0>;
141 operating-points-v2 = <&cpu0_opp_table>;
142 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
143 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
144 #cooling-cells = <2>;
145 L2_100: l2-cache {
146 compatible = "cache";
147 cache-level = <2>;
148 cache-size = <0x20000>;
149 cache-unified;
150 next-level-cache = <&L3_0>;
151 };
152 };
153
154 CPU2: cpu@200 {
155 device_type = "cpu";
156 compatible = "qcom,kryo485";
157 reg = <0x0 0x200>;
158 clocks = <&cpufreq_hw 0>;
159 enable-method = "psci";
160 capacity-dmips-mhz = <448>;
161 dynamic-power-coefficient = <105>;
162 next-level-cache = <&L2_200>;
163 power-domains = <&CPU_PD2>;
164 power-domain-names = "psci";
165 qcom,freq-domain = <&cpufreq_hw 0>;
166 operating-points-v2 = <&cpu0_opp_table>;
167 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
168 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
169 #cooling-cells = <2>;
170 L2_200: l2-cache {
171 compatible = "cache";
172 cache-level = <2>;
173 cache-size = <0x20000>;
174 cache-unified;
175 next-level-cache = <&L3_0>;
176 };
177 };
178
179 CPU3: cpu@300 {
180 device_type = "cpu";
181 compatible = "qcom,kryo485";
182 reg = <0x0 0x300>;
183 clocks = <&cpufreq_hw 0>;
184 enable-method = "psci";
185 capacity-dmips-mhz = <448>;
186 dynamic-power-coefficient = <105>;
187 next-level-cache = <&L2_300>;
188 power-domains = <&CPU_PD3>;
189 power-domain-names = "psci";
190 qcom,freq-domain = <&cpufreq_hw 0>;
191 operating-points-v2 = <&cpu0_opp_table>;
192 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
193 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
194 #cooling-cells = <2>;
195 L2_300: l2-cache {
196 compatible = "cache";
197 cache-level = <2>;
198 cache-size = <0x20000>;
199 cache-unified;
200 next-level-cache = <&L3_0>;
201 };
202 };
203
204 CPU4: cpu@400 {
205 device_type = "cpu";
206 compatible = "qcom,kryo485";
207 reg = <0x0 0x400>;
208 clocks = <&cpufreq_hw 1>;
209 enable-method = "psci";
210 capacity-dmips-mhz = <1024>;
211 dynamic-power-coefficient = <379>;
212 next-level-cache = <&L2_400>;
213 power-domains = <&CPU_PD4>;
214 power-domain-names = "psci";
215 qcom,freq-domain = <&cpufreq_hw 1>;
216 operating-points-v2 = <&cpu4_opp_table>;
217 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
218 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
219 #cooling-cells = <2>;
220 L2_400: l2-cache {
221 compatible = "cache";
222 cache-level = <2>;
223 cache-size = <0x40000>;
224 cache-unified;
225 next-level-cache = <&L3_0>;
226 };
227 };
228
229 CPU5: cpu@500 {
230 device_type = "cpu";
231 compatible = "qcom,kryo485";
232 reg = <0x0 0x500>;
233 clocks = <&cpufreq_hw 1>;
234 enable-method = "psci";
235 capacity-dmips-mhz = <1024>;
236 dynamic-power-coefficient = <379>;
237 next-level-cache = <&L2_500>;
238 power-domains = <&CPU_PD5>;
239 power-domain-names = "psci";
240 qcom,freq-domain = <&cpufreq_hw 1>;
241 operating-points-v2 = <&cpu4_opp_table>;
242 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
243 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
244 #cooling-cells = <2>;
245 L2_500: l2-cache {
246 compatible = "cache";
247 cache-level = <2>;
248 cache-size = <0x40000>;
249 cache-unified;
250 next-level-cache = <&L3_0>;
251 };
252 };
253
254 CPU6: cpu@600 {
255 device_type = "cpu";
256 compatible = "qcom,kryo485";
257 reg = <0x0 0x600>;
258 clocks = <&cpufreq_hw 1>;
259 enable-method = "psci";
260 capacity-dmips-mhz = <1024>;
261 dynamic-power-coefficient = <379>;
262 next-level-cache = <&L2_600>;
263 power-domains = <&CPU_PD6>;
264 power-domain-names = "psci";
265 qcom,freq-domain = <&cpufreq_hw 1>;
266 operating-points-v2 = <&cpu4_opp_table>;
267 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
268 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
269 #cooling-cells = <2>;
270 L2_600: l2-cache {
271 compatible = "cache";
272 cache-level = <2>;
273 cache-size = <0x40000>;
274 cache-unified;
275 next-level-cache = <&L3_0>;
276 };
277 };
278
279 CPU7: cpu@700 {
280 device_type = "cpu";
281 compatible = "qcom,kryo485";
282 reg = <0x0 0x700>;
283 clocks = <&cpufreq_hw 2>;
284 enable-method = "psci";
285 capacity-dmips-mhz = <1024>;
286 dynamic-power-coefficient = <444>;
287 next-level-cache = <&L2_700>;
288 power-domains = <&CPU_PD7>;
289 power-domain-names = "psci";
290 qcom,freq-domain = <&cpufreq_hw 2>;
291 operating-points-v2 = <&cpu7_opp_table>;
292 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
293 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
294 #cooling-cells = <2>;
295 L2_700: l2-cache {
296 compatible = "cache";
297 cache-level = <2>;
298 cache-size = <0x80000>;
299 cache-unified;
300 next-level-cache = <&L3_0>;
301 };
302 };
303
304 cpu-map {
305 cluster0 {
306 core0 {
307 cpu = <&CPU0>;
308 };
309
310 core1 {
311 cpu = <&CPU1>;
312 };
313
314 core2 {
315 cpu = <&CPU2>;
316 };
317
318 core3 {
319 cpu = <&CPU3>;
320 };
321
322 core4 {
323 cpu = <&CPU4>;
324 };
325
326 core5 {
327 cpu = <&CPU5>;
328 };
329
330 core6 {
331 cpu = <&CPU6>;
332 };
333
334 core7 {
335 cpu = <&CPU7>;
336 };
337 };
338 };
339
340 idle-states {
341 entry-method = "psci";
342
343 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
344 compatible = "arm,idle-state";
345 idle-state-name = "silver-rail-power-collapse";
346 arm,psci-suspend-param = <0x40000004>;
347 entry-latency-us = <360>;
348 exit-latency-us = <531>;
349 min-residency-us = <3934>;
350 local-timer-stop;
351 };
352
353 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
354 compatible = "arm,idle-state";
355 idle-state-name = "gold-rail-power-collapse";
356 arm,psci-suspend-param = <0x40000004>;
357 entry-latency-us = <702>;
358 exit-latency-us = <1061>;
359 min-residency-us = <4488>;
360 local-timer-stop;
361 };
362 };
363
364 domain-idle-states {
365 CLUSTER_SLEEP_0: cluster-sleep-0 {
366 compatible = "domain-idle-state";
367 arm,psci-suspend-param = <0x4100c244>;
368 entry-latency-us = <3264>;
369 exit-latency-us = <6562>;
370 min-residency-us = <9987>;
371 };
372 };
373 };
374
375 qup_virt: interconnect-qup-virt {
376 compatible = "qcom,sm8250-qup-virt";
377 #interconnect-cells = <2>;
378 qcom,bcm-voters = <&apps_bcm_voter>;
379 };
380
381 cpu0_opp_table: opp-table-cpu0 {
382 compatible = "operating-points-v2";
383 opp-shared;
384
385 cpu0_opp1: opp-300000000 {
386 opp-hz = /bits/ 64 <300000000>;
387 opp-peak-kBps = <800000 9600000>;
388 };
389
390 cpu0_opp2: opp-403200000 {
391 opp-hz = /bits/ 64 <403200000>;
392 opp-peak-kBps = <800000 9600000>;
393 };
394
395 cpu0_opp3: opp-518400000 {
396 opp-hz = /bits/ 64 <518400000>;
397 opp-peak-kBps = <800000 16588800>;
398 };
399
400 cpu0_opp4: opp-614400000 {
401 opp-hz = /bits/ 64 <614400000>;
402 opp-peak-kBps = <800000 16588800>;
403 };
404
405 cpu0_opp5: opp-691200000 {
406 opp-hz = /bits/ 64 <691200000>;
407 opp-peak-kBps = <800000 19660800>;
408 };
409
410 cpu0_opp6: opp-787200000 {
411 opp-hz = /bits/ 64 <787200000>;
412 opp-peak-kBps = <1804000 19660800>;
413 };
414
415 cpu0_opp7: opp-883200000 {
416 opp-hz = /bits/ 64 <883200000>;
417 opp-peak-kBps = <1804000 23347200>;
418 };
419
420 cpu0_opp8: opp-979200000 {
421 opp-hz = /bits/ 64 <979200000>;
422 opp-peak-kBps = <1804000 26419200>;
423 };
424
425 cpu0_opp9: opp-1075200000 {
426 opp-hz = /bits/ 64 <1075200000>;
427 opp-peak-kBps = <1804000 29491200>;
428 };
429
430 cpu0_opp10: opp-1171200000 {
431 opp-hz = /bits/ 64 <1171200000>;
432 opp-peak-kBps = <1804000 32563200>;
433 };
434
435 cpu0_opp11: opp-1248000000 {
436 opp-hz = /bits/ 64 <1248000000>;
437 opp-peak-kBps = <1804000 36249600>;
438 };
439
440 cpu0_opp12: opp-1344000000 {
441 opp-hz = /bits/ 64 <1344000000>;
442 opp-peak-kBps = <2188000 36249600>;
443 };
444
445 cpu0_opp13: opp-1420800000 {
446 opp-hz = /bits/ 64 <1420800000>;
447 opp-peak-kBps = <2188000 39321600>;
448 };
449
450 cpu0_opp14: opp-1516800000 {
451 opp-hz = /bits/ 64 <1516800000>;
452 opp-peak-kBps = <3072000 42393600>;
453 };
454
455 cpu0_opp15: opp-1612800000 {
456 opp-hz = /bits/ 64 <1612800000>;
457 opp-peak-kBps = <3072000 42393600>;
458 };
459
460 cpu0_opp16: opp-1708800000 {
461 opp-hz = /bits/ 64 <1708800000>;
462 opp-peak-kBps = <4068000 42393600>;
463 };
464
465 cpu0_opp17: opp-1804800000 {
466 opp-hz = /bits/ 64 <1804800000>;
467 opp-peak-kBps = <4068000 42393600>;
468 };
469 };
470
471 cpu4_opp_table: opp-table-cpu4 {
472 compatible = "operating-points-v2";
473 opp-shared;
474
475 cpu4_opp1: opp-710400000 {
476 opp-hz = /bits/ 64 <710400000>;
477 opp-peak-kBps = <1804000 19660800>;
478 };
479
480 cpu4_opp2: opp-825600000 {
481 opp-hz = /bits/ 64 <825600000>;
482 opp-peak-kBps = <2188000 23347200>;
483 };
484
485 cpu4_opp3: opp-940800000 {
486 opp-hz = /bits/ 64 <940800000>;
487 opp-peak-kBps = <2188000 26419200>;
488 };
489
490 cpu4_opp4: opp-1056000000 {
491 opp-hz = /bits/ 64 <1056000000>;
492 opp-peak-kBps = <3072000 26419200>;
493 };
494
495 cpu4_opp5: opp-1171200000 {
496 opp-hz = /bits/ 64 <1171200000>;
497 opp-peak-kBps = <3072000 29491200>;
498 };
499
500 cpu4_opp6: opp-1286400000 {
501 opp-hz = /bits/ 64 <1286400000>;
502 opp-peak-kBps = <4068000 29491200>;
503 };
504
505 cpu4_opp7: opp-1382400000 {
506 opp-hz = /bits/ 64 <1382400000>;
507 opp-peak-kBps = <4068000 32563200>;
508 };
509
510 cpu4_opp8: opp-1478400000 {
511 opp-hz = /bits/ 64 <1478400000>;
512 opp-peak-kBps = <4068000 32563200>;
513 };
514
515 cpu4_opp9: opp-1574400000 {
516 opp-hz = /bits/ 64 <1574400000>;
517 opp-peak-kBps = <5412000 39321600>;
518 };
519
520 cpu4_opp10: opp-1670400000 {
521 opp-hz = /bits/ 64 <1670400000>;
522 opp-peak-kBps = <5412000 42393600>;
523 };
524
525 cpu4_opp11: opp-1766400000 {
526 opp-hz = /bits/ 64 <1766400000>;
527 opp-peak-kBps = <5412000 45465600>;
528 };
529
530 cpu4_opp12: opp-1862400000 {
531 opp-hz = /bits/ 64 <1862400000>;
532 opp-peak-kBps = <6220000 45465600>;
533 };
534
535 cpu4_opp13: opp-1958400000 {
536 opp-hz = /bits/ 64 <1958400000>;
537 opp-peak-kBps = <6220000 48537600>;
538 };
539
540 cpu4_opp14: opp-2054400000 {
541 opp-hz = /bits/ 64 <2054400000>;
542 opp-peak-kBps = <7216000 48537600>;
543 };
544
545 cpu4_opp15: opp-2150400000 {
546 opp-hz = /bits/ 64 <2150400000>;
547 opp-peak-kBps = <7216000 51609600>;
548 };
549
550 cpu4_opp16: opp-2246400000 {
551 opp-hz = /bits/ 64 <2246400000>;
552 opp-peak-kBps = <7216000 51609600>;
553 };
554
555 cpu4_opp17: opp-2342400000 {
556 opp-hz = /bits/ 64 <2342400000>;
557 opp-peak-kBps = <8368000 51609600>;
558 };
559
560 cpu4_opp18: opp-2419200000 {
561 opp-hz = /bits/ 64 <2419200000>;
562 opp-peak-kBps = <8368000 51609600>;
563 };
564 };
565
566 cpu7_opp_table: opp-table-cpu7 {
567 compatible = "operating-points-v2";
568 opp-shared;
569
570 cpu7_opp1: opp-844800000 {
571 opp-hz = /bits/ 64 <844800000>;
572 opp-peak-kBps = <2188000 19660800>;
573 };
574
575 cpu7_opp2: opp-960000000 {
576 opp-hz = /bits/ 64 <960000000>;
577 opp-peak-kBps = <2188000 26419200>;
578 };
579
580 cpu7_opp3: opp-1075200000 {
581 opp-hz = /bits/ 64 <1075200000>;
582 opp-peak-kBps = <3072000 26419200>;
583 };
584
585 cpu7_opp4: opp-1190400000 {
586 opp-hz = /bits/ 64 <1190400000>;
587 opp-peak-kBps = <3072000 29491200>;
588 };
589
590 cpu7_opp5: opp-1305600000 {
591 opp-hz = /bits/ 64 <1305600000>;
592 opp-peak-kBps = <4068000 32563200>;
593 };
594
595 cpu7_opp6: opp-1401600000 {
596 opp-hz = /bits/ 64 <1401600000>;
597 opp-peak-kBps = <4068000 32563200>;
598 };
599
600 cpu7_opp7: opp-1516800000 {
601 opp-hz = /bits/ 64 <1516800000>;
602 opp-peak-kBps = <4068000 36249600>;
603 };
604
605 cpu7_opp8: opp-1632000000 {
606 opp-hz = /bits/ 64 <1632000000>;
607 opp-peak-kBps = <5412000 39321600>;
608 };
609
610 cpu7_opp9: opp-1747200000 {
611 opp-hz = /bits/ 64 <1708800000>;
612 opp-peak-kBps = <5412000 42393600>;
613 };
614
615 cpu7_opp10: opp-1862400000 {
616 opp-hz = /bits/ 64 <1862400000>;
617 opp-peak-kBps = <6220000 45465600>;
618 };
619
620 cpu7_opp11: opp-1977600000 {
621 opp-hz = /bits/ 64 <1977600000>;
622 opp-peak-kBps = <6220000 48537600>;
623 };
624
625 cpu7_opp12: opp-2073600000 {
626 opp-hz = /bits/ 64 <2073600000>;
627 opp-peak-kBps = <7216000 48537600>;
628 };
629
630 cpu7_opp13: opp-2169600000 {
631 opp-hz = /bits/ 64 <2169600000>;
632 opp-peak-kBps = <7216000 51609600>;
633 };
634
635 cpu7_opp14: opp-2265600000 {
636 opp-hz = /bits/ 64 <2265600000>;
637 opp-peak-kBps = <7216000 51609600>;
638 };
639
640 cpu7_opp15: opp-2361600000 {
641 opp-hz = /bits/ 64 <2361600000>;
642 opp-peak-kBps = <8368000 51609600>;
643 };
644
645 cpu7_opp16: opp-2457600000 {
646 opp-hz = /bits/ 64 <2457600000>;
647 opp-peak-kBps = <8368000 51609600>;
648 };
649
650 cpu7_opp17: opp-2553600000 {
651 opp-hz = /bits/ 64 <2553600000>;
652 opp-peak-kBps = <8368000 51609600>;
653 };
654
655 cpu7_opp18: opp-2649600000 {
656 opp-hz = /bits/ 64 <2649600000>;
657 opp-peak-kBps = <8368000 51609600>;
658 };
659
660 cpu7_opp19: opp-2745600000 {
661 opp-hz = /bits/ 64 <2745600000>;
662 opp-peak-kBps = <8368000 51609600>;
663 };
664
665 cpu7_opp20: opp-2841600000 {
666 opp-hz = /bits/ 64 <2841600000>;
667 opp-peak-kBps = <8368000 51609600>;
668 };
669 };
670
671 firmware {
672 scm: scm {
673 compatible = "qcom,scm-sm8250", "qcom,scm";
674 #reset-cells = <1>;
675 };
676 };
677
678 memory@80000000 {
679 device_type = "memory";
680 /* We expect the bootloader to fill in the size */
681 reg = <0x0 0x80000000 0x0 0x0>;
682 };
683
684 pmu {
685 compatible = "arm,armv8-pmuv3";
686 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
687 };
688
689 psci {
690 compatible = "arm,psci-1.0";
691 method = "smc";
692
693 CPU_PD0: power-domain-cpu0 {
694 #power-domain-cells = <0>;
695 power-domains = <&CLUSTER_PD>;
696 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
697 };
698
699 CPU_PD1: power-domain-cpu1 {
700 #power-domain-cells = <0>;
701 power-domains = <&CLUSTER_PD>;
702 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
703 };
704
705 CPU_PD2: power-domain-cpu2 {
706 #power-domain-cells = <0>;
707 power-domains = <&CLUSTER_PD>;
708 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
709 };
710
711 CPU_PD3: power-domain-cpu3 {
712 #power-domain-cells = <0>;
713 power-domains = <&CLUSTER_PD>;
714 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
715 };
716
717 CPU_PD4: power-domain-cpu4 {
718 #power-domain-cells = <0>;
719 power-domains = <&CLUSTER_PD>;
720 domain-idle-states = <&BIG_CPU_SLEEP_0>;
721 };
722
723 CPU_PD5: power-domain-cpu5 {
724 #power-domain-cells = <0>;
725 power-domains = <&CLUSTER_PD>;
726 domain-idle-states = <&BIG_CPU_SLEEP_0>;
727 };
728
729 CPU_PD6: power-domain-cpu6 {
730 #power-domain-cells = <0>;
731 power-domains = <&CLUSTER_PD>;
732 domain-idle-states = <&BIG_CPU_SLEEP_0>;
733 };
734
735 CPU_PD7: power-domain-cpu7 {
736 #power-domain-cells = <0>;
737 power-domains = <&CLUSTER_PD>;
738 domain-idle-states = <&BIG_CPU_SLEEP_0>;
739 };
740
741 CLUSTER_PD: power-domain-cpu-cluster0 {
742 #power-domain-cells = <0>;
743 domain-idle-states = <&CLUSTER_SLEEP_0>;
744 };
745 };
746
747 qup_opp_table: opp-table-qup {
748 compatible = "operating-points-v2";
749
750 opp-50000000 {
751 opp-hz = /bits/ 64 <50000000>;
752 required-opps = <&rpmhpd_opp_min_svs>;
753 };
754
755 opp-75000000 {
756 opp-hz = /bits/ 64 <75000000>;
757 required-opps = <&rpmhpd_opp_low_svs>;
758 };
759
760 opp-120000000 {
761 opp-hz = /bits/ 64 <120000000>;
762 required-opps = <&rpmhpd_opp_svs>;
763 };
764 };
765
766 reserved-memory {
767 #address-cells = <2>;
768 #size-cells = <2>;
769 ranges;
770
771 hyp_mem: memory@80000000 {
772 reg = <0x0 0x80000000 0x0 0x600000>;
773 no-map;
774 };
775
776 xbl_aop_mem: memory@80700000 {
777 reg = <0x0 0x80700000 0x0 0x160000>;
778 no-map;
779 };
780
781 cmd_db: memory@80860000 {
782 compatible = "qcom,cmd-db";
783 reg = <0x0 0x80860000 0x0 0x20000>;
784 no-map;
785 };
786
787 smem_mem: memory@80900000 {
788 reg = <0x0 0x80900000 0x0 0x200000>;
789 no-map;
790 };
791
792 removed_mem: memory@80b00000 {
793 reg = <0x0 0x80b00000 0x0 0x5300000>;
794 no-map;
795 };
796
797 camera_mem: memory@86200000 {
798 reg = <0x0 0x86200000 0x0 0x500000>;
799 no-map;
800 };
801
802 wlan_mem: memory@86700000 {
803 reg = <0x0 0x86700000 0x0 0x100000>;
804 no-map;
805 };
806
807 ipa_fw_mem: memory@86800000 {
808 reg = <0x0 0x86800000 0x0 0x10000>;
809 no-map;
810 };
811
812 ipa_gsi_mem: memory@86810000 {
813 reg = <0x0 0x86810000 0x0 0xa000>;
814 no-map;
815 };
816
817 gpu_mem: memory@8681a000 {
818 reg = <0x0 0x8681a000 0x0 0x2000>;
819 no-map;
820 };
821
822 npu_mem: memory@86900000 {
823 reg = <0x0 0x86900000 0x0 0x500000>;
824 no-map;
825 };
826
827 video_mem: memory@86e00000 {
828 reg = <0x0 0x86e00000 0x0 0x500000>;
829 no-map;
830 };
831
832 cvp_mem: memory@87300000 {
833 reg = <0x0 0x87300000 0x0 0x500000>;
834 no-map;
835 };
836
837 cdsp_mem: memory@87800000 {
838 reg = <0x0 0x87800000 0x0 0x1400000>;
839 no-map;
840 };
841
842 slpi_mem: memory@88c00000 {
843 reg = <0x0 0x88c00000 0x0 0x1500000>;
844 no-map;
845 };
846
847 adsp_mem: memory@8a100000 {
848 reg = <0x0 0x8a100000 0x0 0x1d00000>;
849 no-map;
850 };
851
852 spss_mem: memory@8be00000 {
853 reg = <0x0 0x8be00000 0x0 0x100000>;
854 no-map;
855 };
856
857 cdsp_secure_heap: memory@8bf00000 {
858 reg = <0x0 0x8bf00000 0x0 0x4600000>;
859 no-map;
860 };
861 };
862
863 smem {
864 compatible = "qcom,smem";
865 memory-region = <&smem_mem>;
866 hwlocks = <&tcsr_mutex 3>;
867 };
868
869 smp2p-adsp {
870 compatible = "qcom,smp2p";
871 qcom,smem = <443>, <429>;
872 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
873 IPCC_MPROC_SIGNAL_SMP2P
874 IRQ_TYPE_EDGE_RISING>;
875 mboxes = <&ipcc IPCC_CLIENT_LPASS
876 IPCC_MPROC_SIGNAL_SMP2P>;
877
878 qcom,local-pid = <0>;
879 qcom,remote-pid = <2>;
880
881 smp2p_adsp_out: master-kernel {
882 qcom,entry-name = "master-kernel";
883 #qcom,smem-state-cells = <1>;
884 };
885
886 smp2p_adsp_in: slave-kernel {
887 qcom,entry-name = "slave-kernel";
888 interrupt-controller;
889 #interrupt-cells = <2>;
890 };
891 };
892
893 smp2p-cdsp {
894 compatible = "qcom,smp2p";
895 qcom,smem = <94>, <432>;
896 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
897 IPCC_MPROC_SIGNAL_SMP2P
898 IRQ_TYPE_EDGE_RISING>;
899 mboxes = <&ipcc IPCC_CLIENT_CDSP
900 IPCC_MPROC_SIGNAL_SMP2P>;
901
902 qcom,local-pid = <0>;
903 qcom,remote-pid = <5>;
904
905 smp2p_cdsp_out: master-kernel {
906 qcom,entry-name = "master-kernel";
907 #qcom,smem-state-cells = <1>;
908 };
909
910 smp2p_cdsp_in: slave-kernel {
911 qcom,entry-name = "slave-kernel";
912 interrupt-controller;
913 #interrupt-cells = <2>;
914 };
915 };
916
917 smp2p-slpi {
918 compatible = "qcom,smp2p";
919 qcom,smem = <481>, <430>;
920 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
921 IPCC_MPROC_SIGNAL_SMP2P
922 IRQ_TYPE_EDGE_RISING>;
923 mboxes = <&ipcc IPCC_CLIENT_SLPI
924 IPCC_MPROC_SIGNAL_SMP2P>;
925
926 qcom,local-pid = <0>;
927 qcom,remote-pid = <3>;
928
929 smp2p_slpi_out: master-kernel {
930 qcom,entry-name = "master-kernel";
931 #qcom,smem-state-cells = <1>;
932 };
933
934 smp2p_slpi_in: slave-kernel {
935 qcom,entry-name = "slave-kernel";
936 interrupt-controller;
937 #interrupt-cells = <2>;
938 };
939 };
940
941 soc: soc@0 {
942 #address-cells = <2>;
943 #size-cells = <2>;
944 ranges = <0 0 0 0 0x10 0>;
945 dma-ranges = <0 0 0 0 0x10 0>;
946 compatible = "simple-bus";
947
948 gcc: clock-controller@100000 {
949 compatible = "qcom,gcc-sm8250";
950 reg = <0x0 0x00100000 0x0 0x1f0000>;
951 #clock-cells = <1>;
952 #reset-cells = <1>;
953 #power-domain-cells = <1>;
954 clock-names = "bi_tcxo",
955 "bi_tcxo_ao",
956 "sleep_clk";
957 clocks = <&rpmhcc RPMH_CXO_CLK>,
958 <&rpmhcc RPMH_CXO_CLK_A>,
959 <&sleep_clk>;
960 };
961
962 ipcc: mailbox@408000 {
963 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
964 reg = <0 0x00408000 0 0x1000>;
965 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
966 interrupt-controller;
967 #interrupt-cells = <3>;
968 #mbox-cells = <2>;
969 };
970
971 qfprom: efuse@784000 {
972 compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
973 reg = <0 0x00784000 0 0x8ff>;
974 #address-cells = <1>;
975 #size-cells = <1>;
976
977 gpu_speed_bin: gpu_speed_bin@19b {
978 reg = <0x19b 0x1>;
979 bits = <5 3>;
980 };
981 };
982
983 rng: rng@793000 {
984 compatible = "qcom,prng-ee";
985 reg = <0 0x00793000 0 0x1000>;
986 clocks = <&gcc GCC_PRNG_AHB_CLK>;
987 clock-names = "core";
988 };
989
990 gpi_dma2: dma-controller@800000 {
991 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
992 reg = <0 0x00800000 0 0x70000>;
993 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
999 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1002 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
1003 dma-channels = <10>;
1004 dma-channel-mask = <0x3f>;
1005 iommus = <&apps_smmu 0x76 0x0>;
1006 #dma-cells = <3>;
1007 status = "disabled";
1008 };
1009
1010 qupv3_id_2: geniqup@8c0000 {
1011 compatible = "qcom,geni-se-qup";
1012 reg = <0x0 0x008c0000 0x0 0x6000>;
1013 clock-names = "m-ahb", "s-ahb";
1014 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1015 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1016 #address-cells = <2>;
1017 #size-cells = <2>;
1018 iommus = <&apps_smmu 0x63 0x0>;
1019 ranges;
1020 status = "disabled";
1021
1022 i2c14: i2c@880000 {
1023 compatible = "qcom,geni-i2c";
1024 reg = <0 0x00880000 0 0x4000>;
1025 clock-names = "se";
1026 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1027 pinctrl-names = "default";
1028 pinctrl-0 = <&qup_i2c14_default>;
1029 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1030 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1031 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1032 dma-names = "tx", "rx";
1033 power-domains = <&rpmhpd SM8250_CX>;
1034 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1035 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1036 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1037 interconnect-names = "qup-core",
1038 "qup-config",
1039 "qup-memory";
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1042 status = "disabled";
1043 };
1044
1045 spi14: spi@880000 {
1046 compatible = "qcom,geni-spi";
1047 reg = <0 0x00880000 0 0x4000>;
1048 clock-names = "se";
1049 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1050 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1051 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1052 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1053 dma-names = "tx", "rx";
1054 power-domains = <&rpmhpd RPMHPD_CX>;
1055 operating-points-v2 = <&qup_opp_table>;
1056 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1057 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1058 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1059 interconnect-names = "qup-core",
1060 "qup-config",
1061 "qup-memory";
1062 #address-cells = <1>;
1063 #size-cells = <0>;
1064 status = "disabled";
1065 };
1066
1067 i2c15: i2c@884000 {
1068 compatible = "qcom,geni-i2c";
1069 reg = <0 0x00884000 0 0x4000>;
1070 clock-names = "se";
1071 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1072 pinctrl-names = "default";
1073 pinctrl-0 = <&qup_i2c15_default>;
1074 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1075 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1076 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1077 dma-names = "tx", "rx";
1078 power-domains = <&rpmhpd SM8250_CX>;
1079 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1080 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1081 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1082 interconnect-names = "qup-core",
1083 "qup-config",
1084 "qup-memory";
1085 #address-cells = <1>;
1086 #size-cells = <0>;
1087 status = "disabled";
1088 };
1089
1090 spi15: spi@884000 {
1091 compatible = "qcom,geni-spi";
1092 reg = <0 0x00884000 0 0x4000>;
1093 clock-names = "se";
1094 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1095 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1096 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1097 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1098 dma-names = "tx", "rx";
1099 power-domains = <&rpmhpd RPMHPD_CX>;
1100 operating-points-v2 = <&qup_opp_table>;
1101 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1102 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1103 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1104 interconnect-names = "qup-core",
1105 "qup-config",
1106 "qup-memory";
1107 #address-cells = <1>;
1108 #size-cells = <0>;
1109 status = "disabled";
1110 };
1111
1112 i2c16: i2c@888000 {
1113 compatible = "qcom,geni-i2c";
1114 reg = <0 0x00888000 0 0x4000>;
1115 clock-names = "se";
1116 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1117 pinctrl-names = "default";
1118 pinctrl-0 = <&qup_i2c16_default>;
1119 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1120 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1121 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1122 dma-names = "tx", "rx";
1123 power-domains = <&rpmhpd SM8250_CX>;
1124 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1125 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1126 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1127 interconnect-names = "qup-core",
1128 "qup-config",
1129 "qup-memory";
1130 #address-cells = <1>;
1131 #size-cells = <0>;
1132 status = "disabled";
1133 };
1134
1135 spi16: spi@888000 {
1136 compatible = "qcom,geni-spi";
1137 reg = <0 0x00888000 0 0x4000>;
1138 clock-names = "se";
1139 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1140 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1141 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1142 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1143 dma-names = "tx", "rx";
1144 power-domains = <&rpmhpd RPMHPD_CX>;
1145 operating-points-v2 = <&qup_opp_table>;
1146 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1147 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1148 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1149 interconnect-names = "qup-core",
1150 "qup-config",
1151 "qup-memory";
1152 #address-cells = <1>;
1153 #size-cells = <0>;
1154 status = "disabled";
1155 };
1156
1157 i2c17: i2c@88c000 {
1158 compatible = "qcom,geni-i2c";
1159 reg = <0 0x0088c000 0 0x4000>;
1160 clock-names = "se";
1161 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1162 pinctrl-names = "default";
1163 pinctrl-0 = <&qup_i2c17_default>;
1164 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1165 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1166 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1167 dma-names = "tx", "rx";
1168 power-domains = <&rpmhpd SM8250_CX>;
1169 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1170 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1171 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1172 interconnect-names = "qup-core",
1173 "qup-config",
1174 "qup-memory";
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1177 status = "disabled";
1178 };
1179
1180 spi17: spi@88c000 {
1181 compatible = "qcom,geni-spi";
1182 reg = <0 0x0088c000 0 0x4000>;
1183 clock-names = "se";
1184 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1185 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1186 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1187 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1188 dma-names = "tx", "rx";
1189 power-domains = <&rpmhpd RPMHPD_CX>;
1190 operating-points-v2 = <&qup_opp_table>;
1191 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1192 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1193 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1194 interconnect-names = "qup-core",
1195 "qup-config",
1196 "qup-memory";
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1199 status = "disabled";
1200 };
1201
1202 uart17: serial@88c000 {
1203 compatible = "qcom,geni-uart";
1204 reg = <0 0x0088c000 0 0x4000>;
1205 clock-names = "se";
1206 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1207 pinctrl-names = "default";
1208 pinctrl-0 = <&qup_uart17_default>;
1209 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1210 power-domains = <&rpmhpd RPMHPD_CX>;
1211 operating-points-v2 = <&qup_opp_table>;
1212 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1213 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1214 interconnect-names = "qup-core",
1215 "qup-config";
1216 status = "disabled";
1217 };
1218
1219 i2c18: i2c@890000 {
1220 compatible = "qcom,geni-i2c";
1221 reg = <0 0x00890000 0 0x4000>;
1222 clock-names = "se";
1223 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1224 pinctrl-names = "default";
1225 pinctrl-0 = <&qup_i2c18_default>;
1226 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1227 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1228 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1229 dma-names = "tx", "rx";
1230 power-domains = <&rpmhpd SM8250_CX>;
1231 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1232 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1233 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1234 interconnect-names = "qup-core",
1235 "qup-config",
1236 "qup-memory";
1237 #address-cells = <1>;
1238 #size-cells = <0>;
1239 status = "disabled";
1240 };
1241
1242 spi18: spi@890000 {
1243 compatible = "qcom,geni-spi";
1244 reg = <0 0x00890000 0 0x4000>;
1245 clock-names = "se";
1246 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1247 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1248 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1249 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1250 dma-names = "tx", "rx";
1251 power-domains = <&rpmhpd RPMHPD_CX>;
1252 operating-points-v2 = <&qup_opp_table>;
1253 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1254 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1255 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1256 interconnect-names = "qup-core",
1257 "qup-config",
1258 "qup-memory";
1259 #address-cells = <1>;
1260 #size-cells = <0>;
1261 status = "disabled";
1262 };
1263
1264 uart18: serial@890000 {
1265 compatible = "qcom,geni-uart";
1266 reg = <0 0x00890000 0 0x4000>;
1267 clock-names = "se";
1268 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1269 pinctrl-names = "default";
1270 pinctrl-0 = <&qup_uart18_default>;
1271 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1272 power-domains = <&rpmhpd RPMHPD_CX>;
1273 operating-points-v2 = <&qup_opp_table>;
1274 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1275 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1276 interconnect-names = "qup-core",
1277 "qup-config";
1278 status = "disabled";
1279 };
1280
1281 i2c19: i2c@894000 {
1282 compatible = "qcom,geni-i2c";
1283 reg = <0 0x00894000 0 0x4000>;
1284 clock-names = "se";
1285 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1286 pinctrl-names = "default";
1287 pinctrl-0 = <&qup_i2c19_default>;
1288 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1289 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1290 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1291 dma-names = "tx", "rx";
1292 power-domains = <&rpmhpd SM8250_CX>;
1293 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1294 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1295 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1296 interconnect-names = "qup-core",
1297 "qup-config",
1298 "qup-memory";
1299 #address-cells = <1>;
1300 #size-cells = <0>;
1301 status = "disabled";
1302 };
1303
1304 spi19: spi@894000 {
1305 compatible = "qcom,geni-spi";
1306 reg = <0 0x00894000 0 0x4000>;
1307 clock-names = "se";
1308 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1309 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1310 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1311 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1312 dma-names = "tx", "rx";
1313 power-domains = <&rpmhpd RPMHPD_CX>;
1314 operating-points-v2 = <&qup_opp_table>;
1315 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1316 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1317 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1318 interconnect-names = "qup-core",
1319 "qup-config",
1320 "qup-memory";
1321 #address-cells = <1>;
1322 #size-cells = <0>;
1323 status = "disabled";
1324 };
1325 };
1326
1327 gpi_dma0: dma-controller@900000 {
1328 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1329 reg = <0 0x00900000 0 0x70000>;
1330 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1331 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1342 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1343 dma-channels = <15>;
1344 dma-channel-mask = <0x7ff>;
1345 iommus = <&apps_smmu 0x5b6 0x0>;
1346 #dma-cells = <3>;
1347 status = "disabled";
1348 };
1349
1350 qupv3_id_0: geniqup@9c0000 {
1351 compatible = "qcom,geni-se-qup";
1352 reg = <0x0 0x009c0000 0x0 0x6000>;
1353 clock-names = "m-ahb", "s-ahb";
1354 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1355 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1356 #address-cells = <2>;
1357 #size-cells = <2>;
1358 iommus = <&apps_smmu 0x5a3 0x0>;
1359 ranges;
1360 status = "disabled";
1361
1362 i2c0: i2c@980000 {
1363 compatible = "qcom,geni-i2c";
1364 reg = <0 0x00980000 0 0x4000>;
1365 clock-names = "se";
1366 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1367 pinctrl-names = "default";
1368 pinctrl-0 = <&qup_i2c0_default>;
1369 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1370 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1371 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1372 dma-names = "tx", "rx";
1373 power-domains = <&rpmhpd SM8250_CX>;
1374 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1375 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1376 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1377 interconnect-names = "qup-core",
1378 "qup-config",
1379 "qup-memory";
1380 #address-cells = <1>;
1381 #size-cells = <0>;
1382 status = "disabled";
1383 };
1384
1385 spi0: spi@980000 {
1386 compatible = "qcom,geni-spi";
1387 reg = <0 0x00980000 0 0x4000>;
1388 clock-names = "se";
1389 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1390 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1391 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1392 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1393 dma-names = "tx", "rx";
1394 power-domains = <&rpmhpd RPMHPD_CX>;
1395 operating-points-v2 = <&qup_opp_table>;
1396 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1397 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1398 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1399 interconnect-names = "qup-core",
1400 "qup-config",
1401 "qup-memory";
1402 #address-cells = <1>;
1403 #size-cells = <0>;
1404 status = "disabled";
1405 };
1406
1407 i2c1: i2c@984000 {
1408 compatible = "qcom,geni-i2c";
1409 reg = <0 0x00984000 0 0x4000>;
1410 clock-names = "se";
1411 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1412 pinctrl-names = "default";
1413 pinctrl-0 = <&qup_i2c1_default>;
1414 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1415 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1416 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1417 dma-names = "tx", "rx";
1418 power-domains = <&rpmhpd SM8250_CX>;
1419 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1420 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1421 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1422 interconnect-names = "qup-core",
1423 "qup-config",
1424 "qup-memory";
1425 #address-cells = <1>;
1426 #size-cells = <0>;
1427 status = "disabled";
1428 };
1429
1430 spi1: spi@984000 {
1431 compatible = "qcom,geni-spi";
1432 reg = <0 0x00984000 0 0x4000>;
1433 clock-names = "se";
1434 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1435 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1436 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1437 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1438 dma-names = "tx", "rx";
1439 power-domains = <&rpmhpd RPMHPD_CX>;
1440 operating-points-v2 = <&qup_opp_table>;
1441 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1442 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1443 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1444 interconnect-names = "qup-core",
1445 "qup-config",
1446 "qup-memory";
1447 #address-cells = <1>;
1448 #size-cells = <0>;
1449 status = "disabled";
1450 };
1451
1452 i2c2: i2c@988000 {
1453 compatible = "qcom,geni-i2c";
1454 reg = <0 0x00988000 0 0x4000>;
1455 clock-names = "se";
1456 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1457 pinctrl-names = "default";
1458 pinctrl-0 = <&qup_i2c2_default>;
1459 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1460 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1461 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1462 dma-names = "tx", "rx";
1463 power-domains = <&rpmhpd SM8250_CX>;
1464 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1465 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1466 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1467 interconnect-names = "qup-core",
1468 "qup-config",
1469 "qup-memory";
1470 #address-cells = <1>;
1471 #size-cells = <0>;
1472 status = "disabled";
1473 };
1474
1475 spi2: spi@988000 {
1476 compatible = "qcom,geni-spi";
1477 reg = <0 0x00988000 0 0x4000>;
1478 clock-names = "se";
1479 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1480 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1481 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1482 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1483 dma-names = "tx", "rx";
1484 power-domains = <&rpmhpd RPMHPD_CX>;
1485 operating-points-v2 = <&qup_opp_table>;
1486 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1487 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1488 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1489 interconnect-names = "qup-core",
1490 "qup-config",
1491 "qup-memory";
1492 #address-cells = <1>;
1493 #size-cells = <0>;
1494 status = "disabled";
1495 };
1496
1497 uart2: serial@988000 {
1498 compatible = "qcom,geni-debug-uart";
1499 reg = <0 0x00988000 0 0x4000>;
1500 clock-names = "se";
1501 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1502 pinctrl-names = "default";
1503 pinctrl-0 = <&qup_uart2_default>;
1504 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1505 power-domains = <&rpmhpd RPMHPD_CX>;
1506 operating-points-v2 = <&qup_opp_table>;
1507 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1508 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1509 interconnect-names = "qup-core",
1510 "qup-config";
1511 status = "disabled";
1512 };
1513
1514 i2c3: i2c@98c000 {
1515 compatible = "qcom,geni-i2c";
1516 reg = <0 0x0098c000 0 0x4000>;
1517 clock-names = "se";
1518 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1519 pinctrl-names = "default";
1520 pinctrl-0 = <&qup_i2c3_default>;
1521 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1522 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1523 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1524 dma-names = "tx", "rx";
1525 power-domains = <&rpmhpd SM8250_CX>;
1526 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1527 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1528 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1529 interconnect-names = "qup-core",
1530 "qup-config",
1531 "qup-memory";
1532 #address-cells = <1>;
1533 #size-cells = <0>;
1534 status = "disabled";
1535 };
1536
1537 spi3: spi@98c000 {
1538 compatible = "qcom,geni-spi";
1539 reg = <0 0x0098c000 0 0x4000>;
1540 clock-names = "se";
1541 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1542 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1543 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1544 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1545 dma-names = "tx", "rx";
1546 power-domains = <&rpmhpd RPMHPD_CX>;
1547 operating-points-v2 = <&qup_opp_table>;
1548 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1549 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1550 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1551 interconnect-names = "qup-core",
1552 "qup-config",
1553 "qup-memory";
1554 #address-cells = <1>;
1555 #size-cells = <0>;
1556 status = "disabled";
1557 };
1558
1559 i2c4: i2c@990000 {
1560 compatible = "qcom,geni-i2c";
1561 reg = <0 0x00990000 0 0x4000>;
1562 clock-names = "se";
1563 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1564 pinctrl-names = "default";
1565 pinctrl-0 = <&qup_i2c4_default>;
1566 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1567 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1568 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1569 dma-names = "tx", "rx";
1570 power-domains = <&rpmhpd SM8250_CX>;
1571 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1572 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1573 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1574 interconnect-names = "qup-core",
1575 "qup-config",
1576 "qup-memory";
1577 #address-cells = <1>;
1578 #size-cells = <0>;
1579 status = "disabled";
1580 };
1581
1582 spi4: spi@990000 {
1583 compatible = "qcom,geni-spi";
1584 reg = <0 0x00990000 0 0x4000>;
1585 clock-names = "se";
1586 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1587 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1588 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1589 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1590 dma-names = "tx", "rx";
1591 power-domains = <&rpmhpd RPMHPD_CX>;
1592 operating-points-v2 = <&qup_opp_table>;
1593 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1594 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1595 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1596 interconnect-names = "qup-core",
1597 "qup-config",
1598 "qup-memory";
1599 #address-cells = <1>;
1600 #size-cells = <0>;
1601 status = "disabled";
1602 };
1603
1604 i2c5: i2c@994000 {
1605 compatible = "qcom,geni-i2c";
1606 reg = <0 0x00994000 0 0x4000>;
1607 clock-names = "se";
1608 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1609 pinctrl-names = "default";
1610 pinctrl-0 = <&qup_i2c5_default>;
1611 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1612 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1613 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1614 dma-names = "tx", "rx";
1615 power-domains = <&rpmhpd SM8250_CX>;
1616 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1617 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1618 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1619 interconnect-names = "qup-core",
1620 "qup-config",
1621 "qup-memory";
1622 #address-cells = <1>;
1623 #size-cells = <0>;
1624 status = "disabled";
1625 };
1626
1627 spi5: spi@994000 {
1628 compatible = "qcom,geni-spi";
1629 reg = <0 0x00994000 0 0x4000>;
1630 clock-names = "se";
1631 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1632 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1633 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1634 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1635 dma-names = "tx", "rx";
1636 power-domains = <&rpmhpd RPMHPD_CX>;
1637 operating-points-v2 = <&qup_opp_table>;
1638 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1639 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1640 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1641 interconnect-names = "qup-core",
1642 "qup-config",
1643 "qup-memory";
1644 #address-cells = <1>;
1645 #size-cells = <0>;
1646 status = "disabled";
1647 };
1648
1649 i2c6: i2c@998000 {
1650 compatible = "qcom,geni-i2c";
1651 reg = <0 0x00998000 0 0x4000>;
1652 clock-names = "se";
1653 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1654 pinctrl-names = "default";
1655 pinctrl-0 = <&qup_i2c6_default>;
1656 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1657 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1658 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1659 dma-names = "tx", "rx";
1660 power-domains = <&rpmhpd SM8250_CX>;
1661 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1662 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1663 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1664 interconnect-names = "qup-core",
1665 "qup-config",
1666 "qup-memory";
1667 #address-cells = <1>;
1668 #size-cells = <0>;
1669 status = "disabled";
1670 };
1671
1672 spi6: spi@998000 {
1673 compatible = "qcom,geni-spi";
1674 reg = <0 0x00998000 0 0x4000>;
1675 clock-names = "se";
1676 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1677 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1678 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1679 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1680 dma-names = "tx", "rx";
1681 power-domains = <&rpmhpd RPMHPD_CX>;
1682 operating-points-v2 = <&qup_opp_table>;
1683 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1684 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1685 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1686 interconnect-names = "qup-core",
1687 "qup-config",
1688 "qup-memory";
1689 #address-cells = <1>;
1690 #size-cells = <0>;
1691 status = "disabled";
1692 };
1693
1694 uart6: serial@998000 {
1695 compatible = "qcom,geni-uart";
1696 reg = <0 0x00998000 0 0x4000>;
1697 clock-names = "se";
1698 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1699 pinctrl-names = "default";
1700 pinctrl-0 = <&qup_uart6_default>;
1701 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1702 power-domains = <&rpmhpd RPMHPD_CX>;
1703 operating-points-v2 = <&qup_opp_table>;
1704 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1705 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1706 interconnect-names = "qup-core",
1707 "qup-config";
1708 status = "disabled";
1709 };
1710
1711 i2c7: i2c@99c000 {
1712 compatible = "qcom,geni-i2c";
1713 reg = <0 0x0099c000 0 0x4000>;
1714 clock-names = "se";
1715 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1716 pinctrl-names = "default";
1717 pinctrl-0 = <&qup_i2c7_default>;
1718 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1719 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1720 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1721 dma-names = "tx", "rx";
1722 power-domains = <&rpmhpd SM8250_CX>;
1723 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1724 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1725 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1726 interconnect-names = "qup-core",
1727 "qup-config",
1728 "qup-memory";
1729 #address-cells = <1>;
1730 #size-cells = <0>;
1731 status = "disabled";
1732 };
1733
1734 spi7: spi@99c000 {
1735 compatible = "qcom,geni-spi";
1736 reg = <0 0x0099c000 0 0x4000>;
1737 clock-names = "se";
1738 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1739 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1740 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1741 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1742 dma-names = "tx", "rx";
1743 power-domains = <&rpmhpd RPMHPD_CX>;
1744 operating-points-v2 = <&qup_opp_table>;
1745 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1746 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1747 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1748 interconnect-names = "qup-core",
1749 "qup-config",
1750 "qup-memory";
1751 #address-cells = <1>;
1752 #size-cells = <0>;
1753 status = "disabled";
1754 };
1755 };
1756
1757 gpi_dma1: dma-controller@a00000 {
1758 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1759 reg = <0 0x00a00000 0 0x70000>;
1760 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1769 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1770 dma-channels = <10>;
1771 dma-channel-mask = <0x3f>;
1772 iommus = <&apps_smmu 0x56 0x0>;
1773 #dma-cells = <3>;
1774 status = "disabled";
1775 };
1776
1777 qupv3_id_1: geniqup@ac0000 {
1778 compatible = "qcom,geni-se-qup";
1779 reg = <0x0 0x00ac0000 0x0 0x6000>;
1780 clock-names = "m-ahb", "s-ahb";
1781 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1782 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1783 #address-cells = <2>;
1784 #size-cells = <2>;
1785 iommus = <&apps_smmu 0x43 0x0>;
1786 ranges;
1787 status = "disabled";
1788
1789 i2c8: i2c@a80000 {
1790 compatible = "qcom,geni-i2c";
1791 reg = <0 0x00a80000 0 0x4000>;
1792 clock-names = "se";
1793 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1794 pinctrl-names = "default";
1795 pinctrl-0 = <&qup_i2c8_default>;
1796 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1797 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1798 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1799 dma-names = "tx", "rx";
1800 power-domains = <&rpmhpd SM8250_CX>;
1801 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1802 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1803 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1804 interconnect-names = "qup-core",
1805 "qup-config",
1806 "qup-memory";
1807 #address-cells = <1>;
1808 #size-cells = <0>;
1809 status = "disabled";
1810 };
1811
1812 spi8: spi@a80000 {
1813 compatible = "qcom,geni-spi";
1814 reg = <0 0x00a80000 0 0x4000>;
1815 clock-names = "se";
1816 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1817 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1818 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1819 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1820 dma-names = "tx", "rx";
1821 power-domains = <&rpmhpd RPMHPD_CX>;
1822 operating-points-v2 = <&qup_opp_table>;
1823 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1824 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1825 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1826 interconnect-names = "qup-core",
1827 "qup-config",
1828 "qup-memory";
1829 #address-cells = <1>;
1830 #size-cells = <0>;
1831 status = "disabled";
1832 };
1833
1834 i2c9: i2c@a84000 {
1835 compatible = "qcom,geni-i2c";
1836 reg = <0 0x00a84000 0 0x4000>;
1837 clock-names = "se";
1838 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1839 pinctrl-names = "default";
1840 pinctrl-0 = <&qup_i2c9_default>;
1841 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1842 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1843 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1844 dma-names = "tx", "rx";
1845 power-domains = <&rpmhpd SM8250_CX>;
1846 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1847 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1848 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1849 interconnect-names = "qup-core",
1850 "qup-config",
1851 "qup-memory";
1852 #address-cells = <1>;
1853 #size-cells = <0>;
1854 status = "disabled";
1855 };
1856
1857 spi9: spi@a84000 {
1858 compatible = "qcom,geni-spi";
1859 reg = <0 0x00a84000 0 0x4000>;
1860 clock-names = "se";
1861 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1862 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1863 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1864 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1865 dma-names = "tx", "rx";
1866 power-domains = <&rpmhpd RPMHPD_CX>;
1867 operating-points-v2 = <&qup_opp_table>;
1868 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1869 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1870 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1871 interconnect-names = "qup-core",
1872 "qup-config",
1873 "qup-memory";
1874 #address-cells = <1>;
1875 #size-cells = <0>;
1876 status = "disabled";
1877 };
1878
1879 i2c10: i2c@a88000 {
1880 compatible = "qcom,geni-i2c";
1881 reg = <0 0x00a88000 0 0x4000>;
1882 clock-names = "se";
1883 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1884 pinctrl-names = "default";
1885 pinctrl-0 = <&qup_i2c10_default>;
1886 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1887 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1888 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1889 dma-names = "tx", "rx";
1890 power-domains = <&rpmhpd SM8250_CX>;
1891 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1892 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1893 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1894 interconnect-names = "qup-core",
1895 "qup-config",
1896 "qup-memory";
1897 #address-cells = <1>;
1898 #size-cells = <0>;
1899 status = "disabled";
1900 };
1901
1902 spi10: spi@a88000 {
1903 compatible = "qcom,geni-spi";
1904 reg = <0 0x00a88000 0 0x4000>;
1905 clock-names = "se";
1906 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1907 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1908 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1909 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1910 dma-names = "tx", "rx";
1911 power-domains = <&rpmhpd RPMHPD_CX>;
1912 operating-points-v2 = <&qup_opp_table>;
1913 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1914 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1915 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1916 interconnect-names = "qup-core",
1917 "qup-config",
1918 "qup-memory";
1919 #address-cells = <1>;
1920 #size-cells = <0>;
1921 status = "disabled";
1922 };
1923
1924 i2c11: i2c@a8c000 {
1925 compatible = "qcom,geni-i2c";
1926 reg = <0 0x00a8c000 0 0x4000>;
1927 clock-names = "se";
1928 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1929 pinctrl-names = "default";
1930 pinctrl-0 = <&qup_i2c11_default>;
1931 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1932 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1933 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1934 dma-names = "tx", "rx";
1935 power-domains = <&rpmhpd SM8250_CX>;
1936 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1937 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1938 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1939 interconnect-names = "qup-core",
1940 "qup-config",
1941 "qup-memory";
1942 #address-cells = <1>;
1943 #size-cells = <0>;
1944 status = "disabled";
1945 };
1946
1947 spi11: spi@a8c000 {
1948 compatible = "qcom,geni-spi";
1949 reg = <0 0x00a8c000 0 0x4000>;
1950 clock-names = "se";
1951 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1952 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1953 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1954 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1955 dma-names = "tx", "rx";
1956 power-domains = <&rpmhpd RPMHPD_CX>;
1957 operating-points-v2 = <&qup_opp_table>;
1958 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1959 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1960 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1961 interconnect-names = "qup-core",
1962 "qup-config",
1963 "qup-memory";
1964 #address-cells = <1>;
1965 #size-cells = <0>;
1966 status = "disabled";
1967 };
1968
1969 i2c12: i2c@a90000 {
1970 compatible = "qcom,geni-i2c";
1971 reg = <0 0x00a90000 0 0x4000>;
1972 clock-names = "se";
1973 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1974 pinctrl-names = "default";
1975 pinctrl-0 = <&qup_i2c12_default>;
1976 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1977 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1978 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1979 dma-names = "tx", "rx";
1980 power-domains = <&rpmhpd SM8250_CX>;
1981 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1982 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1983 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1984 interconnect-names = "qup-core",
1985 "qup-config",
1986 "qup-memory";
1987 #address-cells = <1>;
1988 #size-cells = <0>;
1989 status = "disabled";
1990 };
1991
1992 spi12: spi@a90000 {
1993 compatible = "qcom,geni-spi";
1994 reg = <0 0x00a90000 0 0x4000>;
1995 clock-names = "se";
1996 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1997 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1998 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1999 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
2000 dma-names = "tx", "rx";
2001 power-domains = <&rpmhpd RPMHPD_CX>;
2002 operating-points-v2 = <&qup_opp_table>;
2003 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2004 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2005 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2006 interconnect-names = "qup-core",
2007 "qup-config",
2008 "qup-memory";
2009 #address-cells = <1>;
2010 #size-cells = <0>;
2011 status = "disabled";
2012 };
2013
2014 uart12: serial@a90000 {
2015 compatible = "qcom,geni-debug-uart";
2016 reg = <0x0 0x00a90000 0x0 0x4000>;
2017 clock-names = "se";
2018 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2019 pinctrl-names = "default";
2020 pinctrl-0 = <&qup_uart12_default>;
2021 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2022 power-domains = <&rpmhpd RPMHPD_CX>;
2023 operating-points-v2 = <&qup_opp_table>;
2024 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2025 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
2026 interconnect-names = "qup-core",
2027 "qup-config";
2028 status = "disabled";
2029 };
2030
2031 i2c13: i2c@a94000 {
2032 compatible = "qcom,geni-i2c";
2033 reg = <0 0x00a94000 0 0x4000>;
2034 clock-names = "se";
2035 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2036 pinctrl-names = "default";
2037 pinctrl-0 = <&qup_i2c13_default>;
2038 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2039 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2040 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2041 dma-names = "tx", "rx";
2042 power-domains = <&rpmhpd SM8250_CX>;
2043 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2044 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2045 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2046 interconnect-names = "qup-core",
2047 "qup-config",
2048 "qup-memory";
2049 #address-cells = <1>;
2050 #size-cells = <0>;
2051 status = "disabled";
2052 };
2053
2054 spi13: spi@a94000 {
2055 compatible = "qcom,geni-spi";
2056 reg = <0 0x00a94000 0 0x4000>;
2057 clock-names = "se";
2058 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2059 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2060 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2061 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2062 dma-names = "tx", "rx";
2063 power-domains = <&rpmhpd RPMHPD_CX>;
2064 operating-points-v2 = <&qup_opp_table>;
2065 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2066 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2067 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2068 interconnect-names = "qup-core",
2069 "qup-config",
2070 "qup-memory";
2071 #address-cells = <1>;
2072 #size-cells = <0>;
2073 status = "disabled";
2074 };
2075 };
2076
2077 config_noc: interconnect@1500000 {
2078 compatible = "qcom,sm8250-config-noc";
2079 reg = <0 0x01500000 0 0xa580>;
2080 #interconnect-cells = <2>;
2081 qcom,bcm-voters = <&apps_bcm_voter>;
2082 };
2083
2084 system_noc: interconnect@1620000 {
2085 compatible = "qcom,sm8250-system-noc";
2086 reg = <0 0x01620000 0 0x1c200>;
2087 #interconnect-cells = <2>;
2088 qcom,bcm-voters = <&apps_bcm_voter>;
2089 };
2090
2091 mc_virt: interconnect@163d000 {
2092 compatible = "qcom,sm8250-mc-virt";
2093 reg = <0 0x0163d000 0 0x1000>;
2094 #interconnect-cells = <2>;
2095 qcom,bcm-voters = <&apps_bcm_voter>;
2096 };
2097
2098 aggre1_noc: interconnect@16e0000 {
2099 compatible = "qcom,sm8250-aggre1-noc";
2100 reg = <0 0x016e0000 0 0x1f180>;
2101 #interconnect-cells = <2>;
2102 qcom,bcm-voters = <&apps_bcm_voter>;
2103 };
2104
2105 aggre2_noc: interconnect@1700000 {
2106 compatible = "qcom,sm8250-aggre2-noc";
2107 reg = <0 0x01700000 0 0x33000>;
2108 #interconnect-cells = <2>;
2109 qcom,bcm-voters = <&apps_bcm_voter>;
2110 };
2111
2112 compute_noc: interconnect@1733000 {
2113 compatible = "qcom,sm8250-compute-noc";
2114 reg = <0 0x01733000 0 0xa180>;
2115 #interconnect-cells = <2>;
2116 qcom,bcm-voters = <&apps_bcm_voter>;
2117 };
2118
2119 mmss_noc: interconnect@1740000 {
2120 compatible = "qcom,sm8250-mmss-noc";
2121 reg = <0 0x01740000 0 0x1f080>;
2122 #interconnect-cells = <2>;
2123 qcom,bcm-voters = <&apps_bcm_voter>;
2124 };
2125
2126 pcie0: pci@1c00000 {
2127 compatible = "qcom,pcie-sm8250";
2128 reg = <0 0x01c00000 0 0x3000>,
2129 <0 0x60000000 0 0xf1d>,
2130 <0 0x60000f20 0 0xa8>,
2131 <0 0x60001000 0 0x1000>,
2132 <0 0x60100000 0 0x100000>,
2133 <0 0x01c03000 0 0x1000>;
2134 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2135 device_type = "pci";
2136 linux,pci-domain = <0>;
2137 bus-range = <0x00 0xff>;
2138 num-lanes = <1>;
2139
2140 #address-cells = <3>;
2141 #size-cells = <2>;
2142
2143 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2144 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
2145
2146 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2147 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2148 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
2149 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2150 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2151 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2152 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
2153 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2154 interrupt-names = "msi0", "msi1", "msi2", "msi3",
2155 "msi4", "msi5", "msi6", "msi7";
2156 #interrupt-cells = <1>;
2157 interrupt-map-mask = <0 0 0 0x7>;
2158 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2159 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2160 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2161 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2162
2163 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2164 <&gcc GCC_PCIE_0_AUX_CLK>,
2165 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2166 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2167 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2168 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2169 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2170 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2171 clock-names = "pipe",
2172 "aux",
2173 "cfg",
2174 "bus_master",
2175 "bus_slave",
2176 "slave_q2a",
2177 "tbu",
2178 "ddrss_sf_tbu";
2179
2180 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2181 <0x100 &apps_smmu 0x1c01 0x1>;
2182
2183 resets = <&gcc GCC_PCIE_0_BCR>;
2184 reset-names = "pci";
2185
2186 power-domains = <&gcc PCIE_0_GDSC>;
2187
2188 phys = <&pcie0_phy>;
2189 phy-names = "pciephy";
2190
2191 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
2192 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
2193
2194 pinctrl-names = "default";
2195 pinctrl-0 = <&pcie0_default_state>;
2196 dma-coherent;
2197
2198 status = "disabled";
2199 };
2200
2201 pcie0_phy: phy@1c06000 {
2202 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2203 reg = <0 0x01c06000 0 0x1000>;
2204
2205 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2206 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2207 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
2208 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
2209 <&gcc GCC_PCIE_0_PIPE_CLK>;
2210 clock-names = "aux",
2211 "cfg_ahb",
2212 "ref",
2213 "refgen",
2214 "pipe";
2215
2216 clock-output-names = "pcie_0_pipe_clk";
2217 #clock-cells = <0>;
2218
2219 #phy-cells = <0>;
2220
2221 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2222 reset-names = "phy";
2223
2224 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2225 assigned-clock-rates = <100000000>;
2226
2227 status = "disabled";
2228 };
2229
2230 pcie1: pci@1c08000 {
2231 compatible = "qcom,pcie-sm8250";
2232 reg = <0 0x01c08000 0 0x3000>,
2233 <0 0x40000000 0 0xf1d>,
2234 <0 0x40000f20 0 0xa8>,
2235 <0 0x40001000 0 0x1000>,
2236 <0 0x40100000 0 0x100000>,
2237 <0 0x01c0b000 0 0x1000>;
2238 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2239 device_type = "pci";
2240 linux,pci-domain = <1>;
2241 bus-range = <0x00 0xff>;
2242 num-lanes = <2>;
2243
2244 #address-cells = <3>;
2245 #size-cells = <2>;
2246
2247 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2248 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2249
2250 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
2251 interrupt-names = "msi";
2252 #interrupt-cells = <1>;
2253 interrupt-map-mask = <0 0 0 0x7>;
2254 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2255 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2256 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2257 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2258
2259 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2260 <&gcc GCC_PCIE_1_AUX_CLK>,
2261 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2262 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2263 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2264 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2265 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2266 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2267 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2268 clock-names = "pipe",
2269 "aux",
2270 "cfg",
2271 "bus_master",
2272 "bus_slave",
2273 "slave_q2a",
2274 "ref",
2275 "tbu",
2276 "ddrss_sf_tbu";
2277
2278 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2279 assigned-clock-rates = <19200000>;
2280
2281 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2282 <0x100 &apps_smmu 0x1c81 0x1>;
2283
2284 resets = <&gcc GCC_PCIE_1_BCR>;
2285 reset-names = "pci";
2286
2287 power-domains = <&gcc PCIE_1_GDSC>;
2288
2289 phys = <&pcie1_phy>;
2290 phy-names = "pciephy";
2291
2292 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2293 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2294
2295 pinctrl-names = "default";
2296 pinctrl-0 = <&pcie1_default_state>;
2297 dma-coherent;
2298
2299 status = "disabled";
2300 };
2301
2302 pcie1_phy: phy@1c0e000 {
2303 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2304 reg = <0 0x01c0e000 0 0x1000>;
2305
2306 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2307 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2308 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2309 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
2310 <&gcc GCC_PCIE_1_PIPE_CLK>;
2311 clock-names = "aux",
2312 "cfg_ahb",
2313 "ref",
2314 "refgen",
2315 "pipe";
2316
2317 clock-output-names = "pcie_1_pipe_clk";
2318 #clock-cells = <0>;
2319
2320 #phy-cells = <0>;
2321
2322 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2323 reset-names = "phy";
2324
2325 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2326 assigned-clock-rates = <100000000>;
2327
2328 status = "disabled";
2329 };
2330
2331 pcie2: pci@1c10000 {
2332 compatible = "qcom,pcie-sm8250";
2333 reg = <0 0x01c10000 0 0x3000>,
2334 <0 0x64000000 0 0xf1d>,
2335 <0 0x64000f20 0 0xa8>,
2336 <0 0x64001000 0 0x1000>,
2337 <0 0x64100000 0 0x100000>,
2338 <0 0x01c13000 0 0x1000>;
2339 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2340 device_type = "pci";
2341 linux,pci-domain = <2>;
2342 bus-range = <0x00 0xff>;
2343 num-lanes = <2>;
2344
2345 #address-cells = <3>;
2346 #size-cells = <2>;
2347
2348 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
2349 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2350
2351 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2352 interrupt-names = "msi";
2353 #interrupt-cells = <1>;
2354 interrupt-map-mask = <0 0 0 0x7>;
2355 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2356 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2357 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2358 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2359
2360 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2361 <&gcc GCC_PCIE_2_AUX_CLK>,
2362 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2363 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2364 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2365 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2366 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2367 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2368 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2369 clock-names = "pipe",
2370 "aux",
2371 "cfg",
2372 "bus_master",
2373 "bus_slave",
2374 "slave_q2a",
2375 "ref",
2376 "tbu",
2377 "ddrss_sf_tbu";
2378
2379 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2380 assigned-clock-rates = <19200000>;
2381
2382 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2383 <0x100 &apps_smmu 0x1d01 0x1>;
2384
2385 resets = <&gcc GCC_PCIE_2_BCR>;
2386 reset-names = "pci";
2387
2388 power-domains = <&gcc PCIE_2_GDSC>;
2389
2390 phys = <&pcie2_phy>;
2391 phy-names = "pciephy";
2392
2393 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2394 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2395
2396 pinctrl-names = "default";
2397 pinctrl-0 = <&pcie2_default_state>;
2398 dma-coherent;
2399
2400 status = "disabled";
2401 };
2402
2403 pcie2_phy: phy@1c16000 {
2404 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2405 reg = <0 0x01c16000 0 0x1000>;
2406
2407 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2408 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2409 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2410 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
2411 <&gcc GCC_PCIE_2_PIPE_CLK>;
2412 clock-names = "aux",
2413 "cfg_ahb",
2414 "ref",
2415 "refgen",
2416 "pipe";
2417
2418 clock-output-names = "pcie_2_pipe_clk";
2419 #clock-cells = <0>;
2420
2421 #phy-cells = <0>;
2422
2423 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2424 reset-names = "phy";
2425
2426 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2427 assigned-clock-rates = <100000000>;
2428
2429 status = "disabled";
2430 };
2431
2432 ufs_mem_hc: ufshc@1d84000 {
2433 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2434 "jedec,ufs-2.0";
2435 reg = <0 0x01d84000 0 0x3000>;
2436 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2437 phys = <&ufs_mem_phy_lanes>;
2438 phy-names = "ufsphy";
2439 lanes-per-direction = <2>;
2440 #reset-cells = <1>;
2441 resets = <&gcc GCC_UFS_PHY_BCR>;
2442 reset-names = "rst";
2443
2444 power-domains = <&gcc UFS_PHY_GDSC>;
2445
2446 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2447
2448 clock-names =
2449 "core_clk",
2450 "bus_aggr_clk",
2451 "iface_clk",
2452 "core_clk_unipro",
2453 "ref_clk",
2454 "tx_lane0_sync_clk",
2455 "rx_lane0_sync_clk",
2456 "rx_lane1_sync_clk";
2457 clocks =
2458 <&gcc GCC_UFS_PHY_AXI_CLK>,
2459 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2460 <&gcc GCC_UFS_PHY_AHB_CLK>,
2461 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2462 <&rpmhcc RPMH_CXO_CLK>,
2463 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2464 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2465 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2466 freq-table-hz =
2467 <37500000 300000000>,
2468 <0 0>,
2469 <0 0>,
2470 <37500000 300000000>,
2471 <0 0>,
2472 <0 0>,
2473 <0 0>,
2474 <0 0>;
2475
2476 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>,
2477 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2478 interconnect-names = "ufs-ddr", "cpu-ufs";
2479
2480 status = "disabled";
2481 };
2482
2483 ufs_mem_phy: phy@1d87000 {
2484 compatible = "qcom,sm8250-qmp-ufs-phy";
2485 reg = <0 0x01d87000 0 0x1c0>;
2486 #address-cells = <2>;
2487 #size-cells = <2>;
2488 ranges;
2489 clock-names = "ref",
2490 "ref_aux";
2491 clocks = <&rpmhcc RPMH_CXO_CLK>,
2492 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2493
2494 resets = <&ufs_mem_hc 0>;
2495 reset-names = "ufsphy";
2496 status = "disabled";
2497
2498 ufs_mem_phy_lanes: phy@1d87400 {
2499 reg = <0 0x01d87400 0 0x16c>,
2500 <0 0x01d87600 0 0x200>,
2501 <0 0x01d87c00 0 0x200>,
2502 <0 0x01d87800 0 0x16c>,
2503 <0 0x01d87a00 0 0x200>;
2504 #phy-cells = <0>;
2505 };
2506 };
2507
2508 cryptobam: dma-controller@1dc4000 {
2509 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2510 reg = <0 0x01dc4000 0 0x24000>;
2511 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2512 #dma-cells = <1>;
2513 qcom,ee = <0>;
2514 qcom,controlled-remotely;
2515 num-channels = <8>;
2516 qcom,num-ees = <2>;
2517 iommus = <&apps_smmu 0x592 0x0000>,
2518 <&apps_smmu 0x598 0x0000>,
2519 <&apps_smmu 0x599 0x0000>,
2520 <&apps_smmu 0x59f 0x0000>,
2521 <&apps_smmu 0x586 0x0011>,
2522 <&apps_smmu 0x596 0x0011>;
2523 };
2524
2525 crypto: crypto@1dfa000 {
2526 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce";
2527 reg = <0 0x01dfa000 0 0x6000>;
2528 dmas = <&cryptobam 4>, <&cryptobam 5>;
2529 dma-names = "rx", "tx";
2530 iommus = <&apps_smmu 0x592 0x0000>,
2531 <&apps_smmu 0x598 0x0000>,
2532 <&apps_smmu 0x599 0x0000>,
2533 <&apps_smmu 0x59f 0x0000>,
2534 <&apps_smmu 0x586 0x0011>,
2535 <&apps_smmu 0x596 0x0011>;
2536 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2537 interconnect-names = "memory";
2538 };
2539
2540 tcsr_mutex: hwlock@1f40000 {
2541 compatible = "qcom,tcsr-mutex";
2542 reg = <0x0 0x01f40000 0x0 0x40000>;
2543 #hwlock-cells = <1>;
2544 };
2545
2546 wsamacro: codec@3240000 {
2547 compatible = "qcom,sm8250-lpass-wsa-macro";
2548 reg = <0 0x03240000 0 0x1000>;
2549 clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
2550 <&audiocc LPASS_CDC_WSA_NPL>,
2551 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2552 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2553 <&aoncc LPASS_CDC_VA_MCLK>,
2554 <&vamacro>;
2555
2556 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2557
2558 #clock-cells = <0>;
2559 clock-output-names = "mclk";
2560 #sound-dai-cells = <1>;
2561
2562 pinctrl-names = "default";
2563 pinctrl-0 = <&wsa_swr_active>;
2564
2565 status = "disabled";
2566 };
2567
2568 swr0: soundwire-controller@3250000 {
2569 reg = <0 0x03250000 0 0x2000>;
2570 compatible = "qcom,soundwire-v1.5.1";
2571 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2572 clocks = <&wsamacro>;
2573 clock-names = "iface";
2574
2575 qcom,din-ports = <2>;
2576 qcom,dout-ports = <6>;
2577
2578 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2579 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2580 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2581 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2582
2583 #sound-dai-cells = <1>;
2584 #address-cells = <2>;
2585 #size-cells = <0>;
2586
2587 status = "disabled";
2588 };
2589
2590 audiocc: clock-controller@3300000 {
2591 compatible = "qcom,sm8250-lpass-audiocc";
2592 reg = <0 0x03300000 0 0x30000>;
2593 #clock-cells = <1>;
2594 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2595 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2596 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2597 clock-names = "core", "audio", "bus";
2598 };
2599
2600 vamacro: codec@3370000 {
2601 compatible = "qcom,sm8250-lpass-va-macro";
2602 reg = <0 0x03370000 0 0x1000>;
2603 clocks = <&aoncc LPASS_CDC_VA_MCLK>,
2604 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2605 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2606
2607 clock-names = "mclk", "macro", "dcodec";
2608
2609 #clock-cells = <0>;
2610 clock-output-names = "fsgen";
2611 #sound-dai-cells = <1>;
2612 };
2613
2614 rxmacro: rxmacro@3200000 {
2615 pinctrl-names = "default";
2616 pinctrl-0 = <&rx_swr_active>;
2617 compatible = "qcom,sm8250-lpass-rx-macro";
2618 reg = <0 0x03200000 0 0x1000>;
2619 status = "disabled";
2620
2621 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2622 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2623 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2624 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2625 <&vamacro>;
2626
2627 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2628
2629 #clock-cells = <0>;
2630 clock-output-names = "mclk";
2631 #sound-dai-cells = <1>;
2632 };
2633
2634 swr1: soundwire-controller@3210000 {
2635 reg = <0 0x03210000 0 0x2000>;
2636 compatible = "qcom,soundwire-v1.5.1";
2637 status = "disabled";
2638 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
2639 clocks = <&rxmacro>;
2640 clock-names = "iface";
2641 label = "RX";
2642 qcom,din-ports = <0>;
2643 qcom,dout-ports = <5>;
2644
2645 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2646 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2647 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2648 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2649 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2650 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2651 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2652 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2653 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2654
2655 #sound-dai-cells = <1>;
2656 #address-cells = <2>;
2657 #size-cells = <0>;
2658 };
2659
2660 txmacro: txmacro@3220000 {
2661 pinctrl-names = "default";
2662 pinctrl-0 = <&tx_swr_active>;
2663 compatible = "qcom,sm8250-lpass-tx-macro";
2664 reg = <0 0x03220000 0 0x1000>;
2665 status = "disabled";
2666
2667 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2668 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2669 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2670 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2671 <&vamacro>;
2672
2673 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2674
2675 #clock-cells = <0>;
2676 clock-output-names = "mclk";
2677 #sound-dai-cells = <1>;
2678 };
2679
2680 /* tx macro */
2681 swr2: soundwire-controller@3230000 {
2682 reg = <0 0x03230000 0 0x2000>;
2683 compatible = "qcom,soundwire-v1.5.1";
2684 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
2685 interrupt-names = "core";
2686 status = "disabled";
2687
2688 clocks = <&txmacro>;
2689 clock-names = "iface";
2690 label = "TX";
2691
2692 qcom,din-ports = <5>;
2693 qcom,dout-ports = <0>;
2694 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
2695 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
2696 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
2697 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2698 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2699 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2700 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2701 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2702 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
2703 #sound-dai-cells = <1>;
2704 #address-cells = <2>;
2705 #size-cells = <0>;
2706 };
2707
2708 aoncc: clock-controller@3380000 {
2709 compatible = "qcom,sm8250-lpass-aoncc";
2710 reg = <0 0x03380000 0 0x40000>;
2711 #clock-cells = <1>;
2712 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2713 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2714 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2715 clock-names = "core", "audio", "bus";
2716 };
2717
2718 lpass_tlmm: pinctrl@33c0000 {
2719 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2720 reg = <0 0x033c0000 0x0 0x20000>,
2721 <0 0x03550000 0x0 0x10000>;
2722 gpio-controller;
2723 #gpio-cells = <2>;
2724 gpio-ranges = <&lpass_tlmm 0 0 14>;
2725
2726 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2727 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2728 clock-names = "core", "audio";
2729
2730 wsa_swr_active: wsa-swr-active-state {
2731 clk-pins {
2732 pins = "gpio10";
2733 function = "wsa_swr_clk";
2734 drive-strength = <2>;
2735 slew-rate = <1>;
2736 bias-disable;
2737 };
2738
2739 data-pins {
2740 pins = "gpio11";
2741 function = "wsa_swr_data";
2742 drive-strength = <2>;
2743 slew-rate = <1>;
2744 bias-bus-hold;
2745 };
2746 };
2747
2748 wsa_swr_sleep: wsa-swr-sleep-state {
2749 clk-pins {
2750 pins = "gpio10";
2751 function = "wsa_swr_clk";
2752 drive-strength = <2>;
2753 bias-pull-down;
2754 };
2755
2756 data-pins {
2757 pins = "gpio11";
2758 function = "wsa_swr_data";
2759 drive-strength = <2>;
2760 bias-pull-down;
2761 };
2762 };
2763
2764 dmic01_active: dmic01-active-state {
2765 clk-pins {
2766 pins = "gpio6";
2767 function = "dmic1_clk";
2768 drive-strength = <8>;
2769 output-high;
2770 };
2771 data-pins {
2772 pins = "gpio7";
2773 function = "dmic1_data";
2774 drive-strength = <8>;
2775 };
2776 };
2777
2778 dmic01_sleep: dmic01-sleep-state {
2779 clk-pins {
2780 pins = "gpio6";
2781 function = "dmic1_clk";
2782 drive-strength = <2>;
2783 bias-disable;
2784 output-low;
2785 };
2786
2787 data-pins {
2788 pins = "gpio7";
2789 function = "dmic1_data";
2790 drive-strength = <2>;
2791 bias-pull-down;
2792 };
2793 };
2794
2795 rx_swr_active: rx-swr-active-state {
2796 clk-pins {
2797 pins = "gpio3";
2798 function = "swr_rx_clk";
2799 drive-strength = <2>;
2800 slew-rate = <1>;
2801 bias-disable;
2802 };
2803
2804 data-pins {
2805 pins = "gpio4", "gpio5";
2806 function = "swr_rx_data";
2807 drive-strength = <2>;
2808 slew-rate = <1>;
2809 bias-bus-hold;
2810 };
2811 };
2812
2813 tx_swr_active: tx-swr-active-state {
2814 clk-pins {
2815 pins = "gpio0";
2816 function = "swr_tx_clk";
2817 drive-strength = <2>;
2818 slew-rate = <1>;
2819 bias-disable;
2820 };
2821
2822 data-pins {
2823 pins = "gpio1", "gpio2";
2824 function = "swr_tx_data";
2825 drive-strength = <2>;
2826 slew-rate = <1>;
2827 bias-bus-hold;
2828 };
2829 };
2830
2831 tx_swr_sleep: tx-swr-sleep-state {
2832 clk-pins {
2833 pins = "gpio0";
2834 function = "swr_tx_clk";
2835 drive-strength = <2>;
2836 bias-pull-down;
2837 };
2838
2839 data1-pins {
2840 pins = "gpio1";
2841 function = "swr_tx_data";
2842 drive-strength = <2>;
2843 bias-bus-hold;
2844 };
2845
2846 data2-pins {
2847 pins = "gpio2";
2848 function = "swr_tx_data";
2849 drive-strength = <2>;
2850 bias-pull-down;
2851 };
2852 };
2853 };
2854
2855 gpu: gpu@3d00000 {
2856 compatible = "qcom,adreno-650.2",
2857 "qcom,adreno";
2858
2859 reg = <0 0x03d00000 0 0x40000>;
2860 reg-names = "kgsl_3d0_reg_memory";
2861
2862 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2863
2864 iommus = <&adreno_smmu 0 0x401>;
2865
2866 operating-points-v2 = <&gpu_opp_table>;
2867
2868 qcom,gmu = <&gmu>;
2869
2870 nvmem-cells = <&gpu_speed_bin>;
2871 nvmem-cell-names = "speed_bin";
2872
2873 status = "disabled";
2874
2875 zap-shader {
2876 memory-region = <&gpu_mem>;
2877 };
2878
2879 gpu_opp_table: opp-table {
2880 compatible = "operating-points-v2";
2881
2882 opp-670000000 {
2883 opp-hz = /bits/ 64 <670000000>;
2884 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2885 opp-supported-hw = <0xa>;
2886 };
2887
2888 opp-587000000 {
2889 opp-hz = /bits/ 64 <587000000>;
2890 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2891 opp-supported-hw = <0xb>;
2892 };
2893
2894 opp-525000000 {
2895 opp-hz = /bits/ 64 <525000000>;
2896 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2897 opp-supported-hw = <0xf>;
2898 };
2899
2900 opp-490000000 {
2901 opp-hz = /bits/ 64 <490000000>;
2902 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2903 opp-supported-hw = <0xf>;
2904 };
2905
2906 opp-441600000 {
2907 opp-hz = /bits/ 64 <441600000>;
2908 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2909 opp-supported-hw = <0xf>;
2910 };
2911
2912 opp-400000000 {
2913 opp-hz = /bits/ 64 <400000000>;
2914 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2915 opp-supported-hw = <0xf>;
2916 };
2917
2918 opp-305000000 {
2919 opp-hz = /bits/ 64 <305000000>;
2920 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2921 opp-supported-hw = <0xf>;
2922 };
2923 };
2924 };
2925
2926 gmu: gmu@3d6a000 {
2927 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2928
2929 reg = <0 0x03d6a000 0 0x30000>,
2930 <0 0x3de0000 0 0x10000>,
2931 <0 0xb290000 0 0x10000>,
2932 <0 0xb490000 0 0x10000>;
2933 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2934
2935 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2936 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2937 interrupt-names = "hfi", "gmu";
2938
2939 clocks = <&gpucc GPU_CC_AHB_CLK>,
2940 <&gpucc GPU_CC_CX_GMU_CLK>,
2941 <&gpucc GPU_CC_CXO_CLK>,
2942 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2943 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2944 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2945
2946 power-domains = <&gpucc GPU_CX_GDSC>,
2947 <&gpucc GPU_GX_GDSC>;
2948 power-domain-names = "cx", "gx";
2949
2950 iommus = <&adreno_smmu 5 0x400>;
2951
2952 operating-points-v2 = <&gmu_opp_table>;
2953
2954 status = "disabled";
2955
2956 gmu_opp_table: opp-table {
2957 compatible = "operating-points-v2";
2958
2959 opp-200000000 {
2960 opp-hz = /bits/ 64 <200000000>;
2961 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2962 };
2963 };
2964 };
2965
2966 gpucc: clock-controller@3d90000 {
2967 compatible = "qcom,sm8250-gpucc";
2968 reg = <0 0x03d90000 0 0x9000>;
2969 clocks = <&rpmhcc RPMH_CXO_CLK>,
2970 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2971 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2972 clock-names = "bi_tcxo",
2973 "gcc_gpu_gpll0_clk_src",
2974 "gcc_gpu_gpll0_div_clk_src";
2975 #clock-cells = <1>;
2976 #reset-cells = <1>;
2977 #power-domain-cells = <1>;
2978 };
2979
2980 adreno_smmu: iommu@3da0000 {
2981 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu",
2982 "qcom,smmu-500", "arm,mmu-500";
2983 reg = <0 0x03da0000 0 0x10000>;
2984 #iommu-cells = <2>;
2985 #global-interrupts = <2>;
2986 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
2987 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2988 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2989 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2990 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2991 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2992 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2993 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2994 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2995 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
2996 clocks = <&gpucc GPU_CC_AHB_CLK>,
2997 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2998 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2999 clock-names = "ahb", "bus", "iface";
3000
3001 power-domains = <&gpucc GPU_CX_GDSC>;
3002 dma-coherent;
3003 };
3004
3005 slpi: remoteproc@5c00000 {
3006 compatible = "qcom,sm8250-slpi-pas";
3007 reg = <0 0x05c00000 0 0x4000>;
3008
3009 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
3010 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3011 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
3012 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
3013 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
3014 interrupt-names = "wdog", "fatal", "ready",
3015 "handover", "stop-ack";
3016
3017 clocks = <&rpmhcc RPMH_CXO_CLK>;
3018 clock-names = "xo";
3019
3020 power-domains = <&rpmhpd RPMHPD_LCX>,
3021 <&rpmhpd RPMHPD_LMX>;
3022 power-domain-names = "lcx", "lmx";
3023
3024 memory-region = <&slpi_mem>;
3025
3026 qcom,qmp = <&aoss_qmp>;
3027
3028 qcom,smem-states = <&smp2p_slpi_out 0>;
3029 qcom,smem-state-names = "stop";
3030
3031 status = "disabled";
3032
3033 glink-edge {
3034 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3035 IPCC_MPROC_SIGNAL_GLINK_QMP
3036 IRQ_TYPE_EDGE_RISING>;
3037 mboxes = <&ipcc IPCC_CLIENT_SLPI
3038 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3039
3040 label = "slpi";
3041 qcom,remote-pid = <3>;
3042
3043 fastrpc {
3044 compatible = "qcom,fastrpc";
3045 qcom,glink-channels = "fastrpcglink-apps-dsp";
3046 label = "sdsp";
3047 qcom,non-secure-domain;
3048 #address-cells = <1>;
3049 #size-cells = <0>;
3050
3051 compute-cb@1 {
3052 compatible = "qcom,fastrpc-compute-cb";
3053 reg = <1>;
3054 iommus = <&apps_smmu 0x0541 0x0>;
3055 };
3056
3057 compute-cb@2 {
3058 compatible = "qcom,fastrpc-compute-cb";
3059 reg = <2>;
3060 iommus = <&apps_smmu 0x0542 0x0>;
3061 };
3062
3063 compute-cb@3 {
3064 compatible = "qcom,fastrpc-compute-cb";
3065 reg = <3>;
3066 iommus = <&apps_smmu 0x0543 0x0>;
3067 /* note: shared-cb = <4> in downstream */
3068 };
3069 };
3070 };
3071 };
3072
3073 stm@6002000 {
3074 compatible = "arm,coresight-stm", "arm,primecell";
3075 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>;
3076 reg-names = "stm-base", "stm-stimulus-base";
3077
3078 clocks = <&aoss_qmp>;
3079 clock-names = "apb_pclk";
3080
3081 out-ports {
3082 port {
3083 stm_out: endpoint {
3084 remote-endpoint = <&funnel0_in7>;
3085 };
3086 };
3087 };
3088 };
3089
3090 tpda@6004000 {
3091 compatible = "qcom,coresight-tpda", "arm,primecell";
3092 reg = <0 0x06004000 0 0x1000>;
3093
3094 clocks = <&aoss_qmp>;
3095 clock-names = "apb_pclk";
3096
3097 out-ports {
3098 #address-cells = <1>;
3099 #size-cells = <0>;
3100
3101 port@0 {
3102 reg = <0>;
3103 tpda_out_funnel_qatb: endpoint {
3104 remote-endpoint = <&funnel_qatb_in_tpda>;
3105 };
3106 };
3107 };
3108
3109 in-ports {
3110 #address-cells = <1>;
3111 #size-cells = <0>;
3112
3113 port@9 {
3114 reg = <9>;
3115 tpda_9_in_tpdm_mm: endpoint {
3116 remote-endpoint = <&tpdm_mm_out_tpda9>;
3117 };
3118 };
3119
3120 port@17 {
3121 reg = <23>;
3122 tpda_23_in_tpdm_prng: endpoint {
3123 remote-endpoint = <&tpdm_prng_out_tpda_23>;
3124 };
3125 };
3126 };
3127 };
3128
3129 funnel@6005000 {
3130 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3131 reg = <0 0x06005000 0 0x1000>;
3132
3133 clocks = <&aoss_qmp>;
3134 clock-names = "apb_pclk";
3135
3136 out-ports {
3137 port {
3138 funnel_qatb_out_funnel_in0: endpoint {
3139 remote-endpoint = <&funnel_in0_in_funnel_qatb>;
3140 };
3141 };
3142 };
3143
3144 in-ports {
3145 #address-cells = <1>;
3146 #size-cells = <0>;
3147
3148 port@0 {
3149 reg = <0>;
3150 funnel_qatb_in_tpda: endpoint {
3151 remote-endpoint = <&tpda_out_funnel_qatb>;
3152 };
3153 };
3154 };
3155 };
3156
3157 funnel@6041000 {
3158 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3159 reg = <0 0x06041000 0 0x1000>;
3160
3161 clocks = <&aoss_qmp>;
3162 clock-names = "apb_pclk";
3163
3164 out-ports {
3165 port {
3166 funnel_in0_out_funnel_merg: endpoint {
3167 remote-endpoint = <&funnel_merg_in_funnel_in0>;
3168 };
3169 };
3170 };
3171
3172 in-ports {
3173 #address-cells = <1>;
3174 #size-cells = <0>;
3175
3176 port@6 {
3177 reg = <6>;
3178 funnel_in0_in_funnel_qatb: endpoint {
3179 remote-endpoint = <&funnel_qatb_out_funnel_in0>;
3180 };
3181 };
3182
3183 port@7 {
3184 reg = <7>;
3185 funnel0_in7: endpoint {
3186 remote-endpoint = <&stm_out>;
3187 };
3188 };
3189 };
3190 };
3191
3192 funnel@6042000 {
3193 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3194 reg = <0 0x06042000 0 0x1000>;
3195
3196 clocks = <&aoss_qmp>;
3197 clock-names = "apb_pclk";
3198
3199 out-ports {
3200 port {
3201 funnel_in1_out_funnel_merg: endpoint {
3202 remote-endpoint = <&funnel_merg_in_funnel_in1>;
3203 };
3204 };
3205 };
3206
3207 in-ports {
3208 #address-cells = <1>;
3209 #size-cells = <0>;
3210
3211 port@4 {
3212 reg = <4>;
3213 funnel_in1_in_funnel_apss_merg: endpoint {
3214 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>;
3215 };
3216 };
3217 };
3218 };
3219
3220 funnel@6045000 {
3221 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3222 reg = <0 0x06045000 0 0x1000>;
3223
3224 clocks = <&aoss_qmp>;
3225 clock-names = "apb_pclk";
3226
3227 out-ports {
3228 port {
3229 funnel_merg_out_funnel_swao: endpoint {
3230 remote-endpoint = <&funnel_swao_in_funnel_merg>;
3231 };
3232 };
3233 };
3234
3235 in-ports {
3236 #address-cells = <1>;
3237 #size-cells = <0>;
3238
3239 port@0 {
3240 reg = <0>;
3241 funnel_merg_in_funnel_in0: endpoint {
3242 remote-endpoint = <&funnel_in0_out_funnel_merg>;
3243 };
3244 };
3245
3246 port@1 {
3247 reg = <1>;
3248 funnel_merg_in_funnel_in1: endpoint {
3249 remote-endpoint = <&funnel_in1_out_funnel_merg>;
3250 };
3251 };
3252 };
3253 };
3254
3255 replicator@6046000 {
3256 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3257 reg = <0 0x06046000 0 0x1000>;
3258
3259 clocks = <&aoss_qmp>;
3260 clock-names = "apb_pclk";
3261
3262 out-ports {
3263 port {
3264 replicator_out: endpoint {
3265 remote-endpoint = <&etr_in>;
3266 };
3267 };
3268 };
3269
3270 in-ports {
3271 port {
3272 replicator_cx_in_swao_out: endpoint {
3273 remote-endpoint = <&replicator_swao_out_cx_in>;
3274 };
3275 };
3276 };
3277 };
3278
3279 etr@6048000 {
3280 compatible = "arm,coresight-tmc", "arm,primecell";
3281 reg = <0 0x06048000 0 0x1000>;
3282
3283 clocks = <&aoss_qmp>;
3284 clock-names = "apb_pclk";
3285 arm,scatter-gather;
3286
3287 in-ports {
3288 port {
3289 etr_in: endpoint {
3290 remote-endpoint = <&replicator_out>;
3291 };
3292 };
3293 };
3294 };
3295
3296 tpdm@684c000 {
3297 compatible = "qcom,coresight-tpdm", "arm,primecell";
3298 reg = <0 0x0684c000 0 0x1000>;
3299
3300 clocks = <&aoss_qmp>;
3301 clock-names = "apb_pclk";
3302
3303 out-ports {
3304 port {
3305 tpdm_prng_out_tpda_23: endpoint {
3306 remote-endpoint = <&tpda_23_in_tpdm_prng>;
3307 };
3308 };
3309 };
3310 };
3311
3312 funnel@6b04000 {
3313 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3314 arm,primecell-periphid = <0x000bb908>;
3315
3316 reg = <0 0x06b04000 0 0x1000>;
3317
3318 clocks = <&aoss_qmp>;
3319 clock-names = "apb_pclk";
3320
3321 out-ports {
3322 port {
3323 funnel_swao_out_etf: endpoint {
3324 remote-endpoint = <&etf_in_funnel_swao_out>;
3325 };
3326 };
3327 };
3328
3329 in-ports {
3330 #address-cells = <1>;
3331 #size-cells = <0>;
3332
3333 port@7 {
3334 reg = <7>;
3335 funnel_swao_in_funnel_merg: endpoint {
3336 remote-endpoint = <&funnel_merg_out_funnel_swao>;
3337 };
3338 };
3339 };
3340 };
3341
3342 etf@6b05000 {
3343 compatible = "arm,coresight-tmc", "arm,primecell";
3344 reg = <0 0x06b05000 0 0x1000>;
3345
3346 clocks = <&aoss_qmp>;
3347 clock-names = "apb_pclk";
3348
3349 out-ports {
3350 port {
3351 etf_out: endpoint {
3352 remote-endpoint = <&replicator_in>;
3353 };
3354 };
3355 };
3356
3357 in-ports {
3358 #address-cells = <1>;
3359 #size-cells = <0>;
3360
3361 port@0 {
3362 reg = <0>;
3363 etf_in_funnel_swao_out: endpoint {
3364 remote-endpoint = <&funnel_swao_out_etf>;
3365 };
3366 };
3367 };
3368 };
3369
3370 replicator@6b06000 {
3371 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3372 reg = <0 0x06b06000 0 0x1000>;
3373
3374 clocks = <&aoss_qmp>;
3375 clock-names = "apb_pclk";
3376
3377 out-ports {
3378 port {
3379 replicator_swao_out_cx_in: endpoint {
3380 remote-endpoint = <&replicator_cx_in_swao_out>;
3381 };
3382 };
3383 };
3384
3385 in-ports {
3386 port {
3387 replicator_in: endpoint {
3388 remote-endpoint = <&etf_out>;
3389 };
3390 };
3391 };
3392 };
3393
3394 tpdm@6c08000 {
3395 compatible = "qcom,coresight-tpdm", "arm,primecell";
3396 reg = <0 0x06c08000 0 0x1000>;
3397
3398 clocks = <&aoss_qmp>;
3399 clock-names = "apb_pclk";
3400
3401 out-ports {
3402 port {
3403 tpdm_mm_out_funnel_dl_mm: endpoint {
3404 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>;
3405 };
3406 };
3407 };
3408 };
3409
3410 funnel@6c0b000 {
3411 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3412 reg = <0 0x06c0b000 0 0x1000>;
3413
3414 clocks = <&aoss_qmp>;
3415 clock-names = "apb_pclk";
3416
3417 out-ports {
3418 port {
3419 funnel_dl_mm_out_funnel_dl_center: endpoint {
3420 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>;
3421 };
3422 };
3423 };
3424
3425 in-ports {
3426 #address-cells = <1>;
3427 #size-cells = <0>;
3428
3429 port@3 {
3430 reg = <3>;
3431 funnel_dl_mm_in_tpdm_mm: endpoint {
3432 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>;
3433 };
3434 };
3435 };
3436 };
3437
3438 funnel@6c2d000 {
3439 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3440 reg = <0 0x06c2d000 0 0x1000>;
3441
3442 clocks = <&aoss_qmp>;
3443 clock-names = "apb_pclk";
3444
3445 out-ports {
3446 #address-cells = <1>;
3447 #size-cells = <0>;
3448 port {
3449 tpdm_mm_out_tpda9: endpoint {
3450 remote-endpoint = <&tpda_9_in_tpdm_mm>;
3451 };
3452 };
3453 };
3454
3455 in-ports {
3456 #address-cells = <1>;
3457 #size-cells = <0>;
3458
3459 port@2 {
3460 reg = <2>;
3461 funnel_dl_center_in_funnel_dl_mm: endpoint {
3462 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>;
3463 };
3464 };
3465 };
3466 };
3467
3468 etm@7040000 {
3469 compatible = "arm,coresight-etm4x", "arm,primecell";
3470 reg = <0 0x07040000 0 0x1000>;
3471
3472 cpu = <&CPU0>;
3473
3474 clocks = <&aoss_qmp>;
3475 clock-names = "apb_pclk";
3476 arm,coresight-loses-context-with-cpu;
3477
3478 out-ports {
3479 port {
3480 etm0_out: endpoint {
3481 remote-endpoint = <&apss_funnel_in0>;
3482 };
3483 };
3484 };
3485 };
3486
3487 etm@7140000 {
3488 compatible = "arm,coresight-etm4x", "arm,primecell";
3489 reg = <0 0x07140000 0 0x1000>;
3490
3491 cpu = <&CPU1>;
3492
3493 clocks = <&aoss_qmp>;
3494 clock-names = "apb_pclk";
3495 arm,coresight-loses-context-with-cpu;
3496
3497 out-ports {
3498 port {
3499 etm1_out: endpoint {
3500 remote-endpoint = <&apss_funnel_in1>;
3501 };
3502 };
3503 };
3504 };
3505
3506 etm@7240000 {
3507 compatible = "arm,coresight-etm4x", "arm,primecell";
3508 reg = <0 0x07240000 0 0x1000>;
3509
3510 cpu = <&CPU2>;
3511
3512 clocks = <&aoss_qmp>;
3513 clock-names = "apb_pclk";
3514 arm,coresight-loses-context-with-cpu;
3515
3516 out-ports {
3517 port {
3518 etm2_out: endpoint {
3519 remote-endpoint = <&apss_funnel_in2>;
3520 };
3521 };
3522 };
3523 };
3524
3525 etm@7340000 {
3526 compatible = "arm,coresight-etm4x", "arm,primecell";
3527 reg = <0 0x07340000 0 0x1000>;
3528
3529 cpu = <&CPU3>;
3530
3531 clocks = <&aoss_qmp>;
3532 clock-names = "apb_pclk";
3533 arm,coresight-loses-context-with-cpu;
3534
3535 out-ports {
3536 port {
3537 etm3_out: endpoint {
3538 remote-endpoint = <&apss_funnel_in3>;
3539 };
3540 };
3541 };
3542 };
3543
3544 etm@7440000 {
3545 compatible = "arm,coresight-etm4x", "arm,primecell";
3546 reg = <0 0x07440000 0 0x1000>;
3547
3548 cpu = <&CPU4>;
3549
3550 clocks = <&aoss_qmp>;
3551 clock-names = "apb_pclk";
3552 arm,coresight-loses-context-with-cpu;
3553
3554 out-ports {
3555 port {
3556 etm4_out: endpoint {
3557 remote-endpoint = <&apss_funnel_in4>;
3558 };
3559 };
3560 };
3561 };
3562
3563 etm@7540000 {
3564 compatible = "arm,coresight-etm4x", "arm,primecell";
3565 reg = <0 0x07540000 0 0x1000>;
3566
3567 cpu = <&CPU5>;
3568
3569 clocks = <&aoss_qmp>;
3570 clock-names = "apb_pclk";
3571 arm,coresight-loses-context-with-cpu;
3572
3573 out-ports {
3574 port {
3575 etm5_out: endpoint {
3576 remote-endpoint = <&apss_funnel_in5>;
3577 };
3578 };
3579 };
3580 };
3581
3582 etm@7640000 {
3583 compatible = "arm,coresight-etm4x", "arm,primecell";
3584 reg = <0 0x07640000 0 0x1000>;
3585
3586 cpu = <&CPU6>;
3587
3588 clocks = <&aoss_qmp>;
3589 clock-names = "apb_pclk";
3590 arm,coresight-loses-context-with-cpu;
3591
3592 out-ports {
3593 port {
3594 etm6_out: endpoint {
3595 remote-endpoint = <&apss_funnel_in6>;
3596 };
3597 };
3598 };
3599 };
3600
3601 etm@7740000 {
3602 compatible = "arm,coresight-etm4x", "arm,primecell";
3603 reg = <0 0x07740000 0 0x1000>;
3604
3605 cpu = <&CPU7>;
3606
3607 clocks = <&aoss_qmp>;
3608 clock-names = "apb_pclk";
3609 arm,coresight-loses-context-with-cpu;
3610
3611 out-ports {
3612 port {
3613 etm7_out: endpoint {
3614 remote-endpoint = <&apss_funnel_in7>;
3615 };
3616 };
3617 };
3618 };
3619
3620 funnel@7800000 {
3621 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3622 reg = <0 0x07800000 0 0x1000>;
3623
3624 clocks = <&aoss_qmp>;
3625 clock-names = "apb_pclk";
3626
3627 out-ports {
3628 port {
3629 funnel_apss_out_funnel_apss_merg: endpoint {
3630 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>;
3631 };
3632 };
3633 };
3634
3635 in-ports {
3636 #address-cells = <1>;
3637 #size-cells = <0>;
3638
3639 port@0 {
3640 reg = <0>;
3641 apss_funnel_in0: endpoint {
3642 remote-endpoint = <&etm0_out>;
3643 };
3644 };
3645
3646 port@1 {
3647 reg = <1>;
3648 apss_funnel_in1: endpoint {
3649 remote-endpoint = <&etm1_out>;
3650 };
3651 };
3652
3653 port@2 {
3654 reg = <2>;
3655 apss_funnel_in2: endpoint {
3656 remote-endpoint = <&etm2_out>;
3657 };
3658 };
3659
3660 port@3 {
3661 reg = <3>;
3662 apss_funnel_in3: endpoint {
3663 remote-endpoint = <&etm3_out>;
3664 };
3665 };
3666
3667 port@4 {
3668 reg = <4>;
3669 apss_funnel_in4: endpoint {
3670 remote-endpoint = <&etm4_out>;
3671 };
3672 };
3673
3674 port@5 {
3675 reg = <5>;
3676 apss_funnel_in5: endpoint {
3677 remote-endpoint = <&etm5_out>;
3678 };
3679 };
3680
3681 port@6 {
3682 reg = <6>;
3683 apss_funnel_in6: endpoint {
3684 remote-endpoint = <&etm6_out>;
3685 };
3686 };
3687
3688 port@7 {
3689 reg = <7>;
3690 apss_funnel_in7: endpoint {
3691 remote-endpoint = <&etm7_out>;
3692 };
3693 };
3694 };
3695 };
3696
3697 funnel@7810000 {
3698 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3699 reg = <0 0x07810000 0 0x1000>;
3700
3701 clocks = <&aoss_qmp>;
3702 clock-names = "apb_pclk";
3703
3704 out-ports {
3705 port {
3706 funnel_apss_merg_out_funnel_in1: endpoint {
3707 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
3708 };
3709 };
3710 };
3711
3712 in-ports {
3713 #address-cells = <1>;
3714 #size-cells = <0>;
3715
3716 port@0 {
3717 reg = <0>;
3718 funnel_apss_merg_in_funnel_apss: endpoint {
3719 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
3720 };
3721 };
3722 };
3723 };
3724
3725 cdsp: remoteproc@8300000 {
3726 compatible = "qcom,sm8250-cdsp-pas";
3727 reg = <0 0x08300000 0 0x10000>;
3728
3729 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3730 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3731 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3732 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3733 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3734 interrupt-names = "wdog", "fatal", "ready",
3735 "handover", "stop-ack";
3736
3737 clocks = <&rpmhcc RPMH_CXO_CLK>;
3738 clock-names = "xo";
3739
3740 power-domains = <&rpmhpd RPMHPD_CX>;
3741
3742 memory-region = <&cdsp_mem>;
3743
3744 qcom,qmp = <&aoss_qmp>;
3745
3746 qcom,smem-states = <&smp2p_cdsp_out 0>;
3747 qcom,smem-state-names = "stop";
3748
3749 status = "disabled";
3750
3751 glink-edge {
3752 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3753 IPCC_MPROC_SIGNAL_GLINK_QMP
3754 IRQ_TYPE_EDGE_RISING>;
3755 mboxes = <&ipcc IPCC_CLIENT_CDSP
3756 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3757
3758 label = "cdsp";
3759 qcom,remote-pid = <5>;
3760
3761 fastrpc {
3762 compatible = "qcom,fastrpc";
3763 qcom,glink-channels = "fastrpcglink-apps-dsp";
3764 label = "cdsp";
3765 qcom,non-secure-domain;
3766 #address-cells = <1>;
3767 #size-cells = <0>;
3768
3769 compute-cb@1 {
3770 compatible = "qcom,fastrpc-compute-cb";
3771 reg = <1>;
3772 iommus = <&apps_smmu 0x1001 0x0460>;
3773 };
3774
3775 compute-cb@2 {
3776 compatible = "qcom,fastrpc-compute-cb";
3777 reg = <2>;
3778 iommus = <&apps_smmu 0x1002 0x0460>;
3779 };
3780
3781 compute-cb@3 {
3782 compatible = "qcom,fastrpc-compute-cb";
3783 reg = <3>;
3784 iommus = <&apps_smmu 0x1003 0x0460>;
3785 };
3786
3787 compute-cb@4 {
3788 compatible = "qcom,fastrpc-compute-cb";
3789 reg = <4>;
3790 iommus = <&apps_smmu 0x1004 0x0460>;
3791 };
3792
3793 compute-cb@5 {
3794 compatible = "qcom,fastrpc-compute-cb";
3795 reg = <5>;
3796 iommus = <&apps_smmu 0x1005 0x0460>;
3797 };
3798
3799 compute-cb@6 {
3800 compatible = "qcom,fastrpc-compute-cb";
3801 reg = <6>;
3802 iommus = <&apps_smmu 0x1006 0x0460>;
3803 };
3804
3805 compute-cb@7 {
3806 compatible = "qcom,fastrpc-compute-cb";
3807 reg = <7>;
3808 iommus = <&apps_smmu 0x1007 0x0460>;
3809 };
3810
3811 compute-cb@8 {
3812 compatible = "qcom,fastrpc-compute-cb";
3813 reg = <8>;
3814 iommus = <&apps_smmu 0x1008 0x0460>;
3815 };
3816
3817 /* note: secure cb9 in downstream */
3818 };
3819 };
3820 };
3821
3822 usb_1_hsphy: phy@88e3000 {
3823 compatible = "qcom,sm8250-usb-hs-phy",
3824 "qcom,usb-snps-hs-7nm-phy";
3825 reg = <0 0x088e3000 0 0x400>;
3826 status = "disabled";
3827 #phy-cells = <0>;
3828
3829 clocks = <&rpmhcc RPMH_CXO_CLK>;
3830 clock-names = "ref";
3831
3832 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3833 };
3834
3835 usb_2_hsphy: phy@88e4000 {
3836 compatible = "qcom,sm8250-usb-hs-phy",
3837 "qcom,usb-snps-hs-7nm-phy";
3838 reg = <0 0x088e4000 0 0x400>;
3839 status = "disabled";
3840 #phy-cells = <0>;
3841
3842 clocks = <&rpmhcc RPMH_CXO_CLK>;
3843 clock-names = "ref";
3844
3845 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3846 };
3847
3848 usb_1_qmpphy: phy@88e8000 {
3849 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3850 reg = <0 0x088e8000 0 0x3000>;
3851 status = "disabled";
3852
3853 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3854 <&rpmhcc RPMH_CXO_CLK>,
3855 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3856 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3857 clock-names = "aux",
3858 "ref",
3859 "com_aux",
3860 "usb3_pipe";
3861
3862 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3863 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3864 reset-names = "phy", "common";
3865
3866 #clock-cells = <1>;
3867 #phy-cells = <1>;
3868
3869 ports {
3870 #address-cells = <1>;
3871 #size-cells = <0>;
3872
3873 port@0 {
3874 reg = <0>;
3875 usb_1_qmpphy_out: endpoint {};
3876 };
3877
3878 port@1 {
3879 reg = <1>;
3880 };
3881
3882 port@2 {
3883 reg = <2>;
3884
3885 usb_1_qmpphy_dp_in: endpoint {};
3886 };
3887 };
3888 };
3889
3890 usb_2_qmpphy: phy@88eb000 {
3891 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3892 reg = <0 0x088eb000 0 0x200>;
3893 status = "disabled";
3894 #address-cells = <2>;
3895 #size-cells = <2>;
3896 ranges;
3897
3898 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3899 <&rpmhcc RPMH_CXO_CLK>,
3900 <&gcc GCC_USB3_SEC_CLKREF_EN>,
3901 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3902 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3903
3904 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3905 <&gcc GCC_USB3_PHY_SEC_BCR>;
3906 reset-names = "phy", "common";
3907
3908 usb_2_ssphy: phy@88eb200 {
3909 reg = <0 0x088eb200 0 0x200>,
3910 <0 0x088eb400 0 0x200>,
3911 <0 0x088eb800 0 0x800>;
3912 #clock-cells = <0>;
3913 #phy-cells = <0>;
3914 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3915 clock-names = "pipe0";
3916 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3917 };
3918 };
3919
3920 sdhc_2: mmc@8804000 {
3921 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3922 reg = <0 0x08804000 0 0x1000>;
3923
3924 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3925 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3926 interrupt-names = "hc_irq", "pwr_irq";
3927
3928 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3929 <&gcc GCC_SDCC2_APPS_CLK>,
3930 <&rpmhcc RPMH_CXO_CLK>;
3931 clock-names = "iface", "core", "xo";
3932 iommus = <&apps_smmu 0x4a0 0x0>;
3933 qcom,dll-config = <0x0007642c>;
3934 qcom,ddr-config = <0x80040868>;
3935 power-domains = <&rpmhpd RPMHPD_CX>;
3936 operating-points-v2 = <&sdhc2_opp_table>;
3937
3938 status = "disabled";
3939
3940 sdhc2_opp_table: opp-table {
3941 compatible = "operating-points-v2";
3942
3943 opp-19200000 {
3944 opp-hz = /bits/ 64 <19200000>;
3945 required-opps = <&rpmhpd_opp_min_svs>;
3946 };
3947
3948 opp-50000000 {
3949 opp-hz = /bits/ 64 <50000000>;
3950 required-opps = <&rpmhpd_opp_low_svs>;
3951 };
3952
3953 opp-100000000 {
3954 opp-hz = /bits/ 64 <100000000>;
3955 required-opps = <&rpmhpd_opp_svs>;
3956 };
3957
3958 opp-202000000 {
3959 opp-hz = /bits/ 64 <202000000>;
3960 required-opps = <&rpmhpd_opp_svs_l1>;
3961 };
3962 };
3963 };
3964
3965 pmu@9091000 {
3966 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3967 reg = <0 0x09091000 0 0x1000>;
3968
3969 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3970
3971 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI_CH0 3>;
3972
3973 operating-points-v2 = <&llcc_bwmon_opp_table>;
3974
3975 llcc_bwmon_opp_table: opp-table {
3976 compatible = "operating-points-v2";
3977
3978 opp-800000 {
3979 opp-peak-kBps = <(200 * 4 * 1000)>;
3980 };
3981
3982 opp-1200000 {
3983 opp-peak-kBps = <(300 * 4 * 1000)>;
3984 };
3985
3986 opp-1804000 {
3987 opp-peak-kBps = <(451 * 4 * 1000)>;
3988 };
3989
3990 opp-2188000 {
3991 opp-peak-kBps = <(547 * 4 * 1000)>;
3992 };
3993
3994 opp-2724000 {
3995 opp-peak-kBps = <(681 * 4 * 1000)>;
3996 };
3997
3998 opp-3072000 {
3999 opp-peak-kBps = <(768 * 4 * 1000)>;
4000 };
4001
4002 opp-4068000 {
4003 opp-peak-kBps = <(1017 * 4 * 1000)>;
4004 };
4005
4006 /* 1353 MHz, LPDDR4X */
4007
4008 opp-6220000 {
4009 opp-peak-kBps = <(1555 * 4 * 1000)>;
4010 };
4011
4012 opp-7216000 {
4013 opp-peak-kBps = <(1804 * 4 * 1000)>;
4014 };
4015
4016 opp-8368000 {
4017 opp-peak-kBps = <(2092 * 4 * 1000)>;
4018 };
4019
4020 /* LPDDR5 */
4021 opp-10944000 {
4022 opp-peak-kBps = <(2736 * 4 * 1000)>;
4023 };
4024 };
4025 };
4026
4027 pmu@90b6400 {
4028 compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon";
4029 reg = <0 0x090b6400 0 0x600>;
4030
4031 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
4032
4033 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &gem_noc SLAVE_LLCC 3>;
4034 operating-points-v2 = <&cpu_bwmon_opp_table>;
4035
4036 cpu_bwmon_opp_table: opp-table {
4037 compatible = "operating-points-v2";
4038
4039 opp-800000 {
4040 opp-peak-kBps = <(200 * 4 * 1000)>;
4041 };
4042
4043 opp-1804000 {
4044 opp-peak-kBps = <(451 * 4 * 1000)>;
4045 };
4046
4047 opp-2188000 {
4048 opp-peak-kBps = <(547 * 4 * 1000)>;
4049 };
4050
4051 opp-2724000 {
4052 opp-peak-kBps = <(681 * 4 * 1000)>;
4053 };
4054
4055 opp-3072000 {
4056 opp-peak-kBps = <(768 * 4 * 1000)>;
4057 };
4058
4059 /* 1017MHz, 1353 MHz, LPDDR4X */
4060
4061 opp-6220000 {
4062 opp-peak-kBps = <(1555 * 4 * 1000)>;
4063 };
4064
4065 opp-6832000 {
4066 opp-peak-kBps = <(1708 * 4 * 1000)>;
4067 };
4068
4069 opp-8368000 {
4070 opp-peak-kBps = <(2092 * 4 * 1000)>;
4071 };
4072
4073 /* 2133MHz, LPDDR4X */
4074
4075 /* LPDDR5 */
4076 opp-10944000 {
4077 opp-peak-kBps = <(2736 * 4 * 1000)>;
4078 };
4079
4080 /* LPDDR5 */
4081 opp-12784000 {
4082 opp-peak-kBps = <(3196 * 4 * 1000)>;
4083 };
4084 };
4085 };
4086
4087 dc_noc: interconnect@90c0000 {
4088 compatible = "qcom,sm8250-dc-noc";
4089 reg = <0 0x090c0000 0 0x4200>;
4090 #interconnect-cells = <2>;
4091 qcom,bcm-voters = <&apps_bcm_voter>;
4092 };
4093
4094 gem_noc: interconnect@9100000 {
4095 compatible = "qcom,sm8250-gem-noc";
4096 reg = <0 0x09100000 0 0xb4000>;
4097 #interconnect-cells = <2>;
4098 qcom,bcm-voters = <&apps_bcm_voter>;
4099 };
4100
4101 npu_noc: interconnect@9990000 {
4102 compatible = "qcom,sm8250-npu-noc";
4103 reg = <0 0x09990000 0 0x1600>;
4104 #interconnect-cells = <2>;
4105 qcom,bcm-voters = <&apps_bcm_voter>;
4106 };
4107
4108 usb_1: usb@a6f8800 {
4109 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4110 reg = <0 0x0a6f8800 0 0x400>;
4111 status = "disabled";
4112 #address-cells = <2>;
4113 #size-cells = <2>;
4114 ranges;
4115 dma-ranges;
4116
4117 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4118 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4119 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4120 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4121 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4122 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4123 clock-names = "cfg_noc",
4124 "core",
4125 "iface",
4126 "sleep",
4127 "mock_utmi",
4128 "xo";
4129
4130 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4131 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4132 assigned-clock-rates = <19200000>, <200000000>;
4133
4134 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4135 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
4136 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4137 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
4138 interrupt-names = "hs_phy_irq",
4139 "ss_phy_irq",
4140 "dm_hs_phy_irq",
4141 "dp_hs_phy_irq";
4142
4143 power-domains = <&gcc USB30_PRIM_GDSC>;
4144
4145 resets = <&gcc GCC_USB30_PRIM_BCR>;
4146
4147 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
4148 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
4149 interconnect-names = "usb-ddr", "apps-usb";
4150
4151 usb_1_dwc3: usb@a600000 {
4152 compatible = "snps,dwc3";
4153 reg = <0 0x0a600000 0 0xcd00>;
4154 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4155 iommus = <&apps_smmu 0x0 0x0>;
4156 snps,dis_u2_susphy_quirk;
4157 snps,dis_enblslpm_quirk;
4158 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4159 phy-names = "usb2-phy", "usb3-phy";
4160
4161 port {
4162 usb_1_role_switch_out: endpoint {};
4163 };
4164 };
4165 };
4166
4167 system-cache-controller@9200000 {
4168 compatible = "qcom,sm8250-llcc";
4169 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
4170 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
4171 <0 0x09600000 0 0x50000>;
4172 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4173 "llcc3_base", "llcc_broadcast_base";
4174 };
4175
4176 usb_2: usb@a8f8800 {
4177 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4178 reg = <0 0x0a8f8800 0 0x400>;
4179 status = "disabled";
4180 #address-cells = <2>;
4181 #size-cells = <2>;
4182 ranges;
4183 dma-ranges;
4184
4185 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4186 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4187 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4188 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4189 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4190 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4191 clock-names = "cfg_noc",
4192 "core",
4193 "iface",
4194 "sleep",
4195 "mock_utmi",
4196 "xo";
4197
4198 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4199 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4200 assigned-clock-rates = <19200000>, <200000000>;
4201
4202 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4203 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
4204 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
4205 <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
4206 interrupt-names = "hs_phy_irq",
4207 "ss_phy_irq",
4208 "dm_hs_phy_irq",
4209 "dp_hs_phy_irq";
4210
4211 power-domains = <&gcc USB30_SEC_GDSC>;
4212
4213 resets = <&gcc GCC_USB30_SEC_BCR>;
4214
4215 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
4216 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
4217 interconnect-names = "usb-ddr", "apps-usb";
4218
4219 usb_2_dwc3: usb@a800000 {
4220 compatible = "snps,dwc3";
4221 reg = <0 0x0a800000 0 0xcd00>;
4222 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4223 iommus = <&apps_smmu 0x20 0>;
4224 snps,dis_u2_susphy_quirk;
4225 snps,dis_enblslpm_quirk;
4226 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4227 phy-names = "usb2-phy", "usb3-phy";
4228 };
4229 };
4230
4231 venus: video-codec@aa00000 {
4232 compatible = "qcom,sm8250-venus";
4233 reg = <0 0x0aa00000 0 0x100000>;
4234 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4235 power-domains = <&videocc MVS0C_GDSC>,
4236 <&videocc MVS0_GDSC>,
4237 <&rpmhpd RPMHPD_MX>;
4238 power-domain-names = "venus", "vcodec0", "mx";
4239 operating-points-v2 = <&venus_opp_table>;
4240
4241 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
4242 <&videocc VIDEO_CC_MVS0C_CLK>,
4243 <&videocc VIDEO_CC_MVS0_CLK>;
4244 clock-names = "iface", "core", "vcodec0_core";
4245
4246 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>,
4247 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>;
4248 interconnect-names = "cpu-cfg", "video-mem";
4249
4250 iommus = <&apps_smmu 0x2100 0x0400>;
4251 memory-region = <&video_mem>;
4252
4253 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
4254 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
4255 reset-names = "bus", "core";
4256
4257 status = "disabled";
4258
4259 video-decoder {
4260 compatible = "venus-decoder";
4261 };
4262
4263 video-encoder {
4264 compatible = "venus-encoder";
4265 };
4266
4267 venus_opp_table: opp-table {
4268 compatible = "operating-points-v2";
4269
4270 opp-720000000 {
4271 opp-hz = /bits/ 64 <720000000>;
4272 required-opps = <&rpmhpd_opp_low_svs>;
4273 };
4274
4275 opp-1014000000 {
4276 opp-hz = /bits/ 64 <1014000000>;
4277 required-opps = <&rpmhpd_opp_svs>;
4278 };
4279
4280 opp-1098000000 {
4281 opp-hz = /bits/ 64 <1098000000>;
4282 required-opps = <&rpmhpd_opp_svs_l1>;
4283 };
4284
4285 opp-1332000000 {
4286 opp-hz = /bits/ 64 <1332000000>;
4287 required-opps = <&rpmhpd_opp_nom>;
4288 };
4289 };
4290 };
4291
4292 videocc: clock-controller@abf0000 {
4293 compatible = "qcom,sm8250-videocc";
4294 reg = <0 0x0abf0000 0 0x10000>;
4295 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
4296 <&rpmhcc RPMH_CXO_CLK>,
4297 <&rpmhcc RPMH_CXO_CLK_A>;
4298 power-domains = <&rpmhpd RPMHPD_MMCX>;
4299 required-opps = <&rpmhpd_opp_low_svs>;
4300 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4301 #clock-cells = <1>;
4302 #reset-cells = <1>;
4303 #power-domain-cells = <1>;
4304 };
4305
4306 cci0: cci@ac4f000 {
4307 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4308 #address-cells = <1>;
4309 #size-cells = <0>;
4310
4311 reg = <0 0x0ac4f000 0 0x1000>;
4312 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4313 power-domains = <&camcc TITAN_TOP_GDSC>;
4314
4315 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4316 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4317 <&camcc CAM_CC_CPAS_AHB_CLK>,
4318 <&camcc CAM_CC_CCI_0_CLK>,
4319 <&camcc CAM_CC_CCI_0_CLK_SRC>;
4320 clock-names = "camnoc_axi",
4321 "slow_ahb_src",
4322 "cpas_ahb",
4323 "cci",
4324 "cci_src";
4325
4326 pinctrl-0 = <&cci0_default>;
4327 pinctrl-1 = <&cci0_sleep>;
4328 pinctrl-names = "default", "sleep";
4329
4330 status = "disabled";
4331
4332 cci0_i2c0: i2c-bus@0 {
4333 reg = <0>;
4334 clock-frequency = <1000000>;
4335 #address-cells = <1>;
4336 #size-cells = <0>;
4337 };
4338
4339 cci0_i2c1: i2c-bus@1 {
4340 reg = <1>;
4341 clock-frequency = <1000000>;
4342 #address-cells = <1>;
4343 #size-cells = <0>;
4344 };
4345 };
4346
4347 cci1: cci@ac50000 {
4348 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4349 #address-cells = <1>;
4350 #size-cells = <0>;
4351
4352 reg = <0 0x0ac50000 0 0x1000>;
4353 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
4354 power-domains = <&camcc TITAN_TOP_GDSC>;
4355
4356 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4357 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4358 <&camcc CAM_CC_CPAS_AHB_CLK>,
4359 <&camcc CAM_CC_CCI_1_CLK>,
4360 <&camcc CAM_CC_CCI_1_CLK_SRC>;
4361 clock-names = "camnoc_axi",
4362 "slow_ahb_src",
4363 "cpas_ahb",
4364 "cci",
4365 "cci_src";
4366
4367 pinctrl-0 = <&cci1_default>;
4368 pinctrl-1 = <&cci1_sleep>;
4369 pinctrl-names = "default", "sleep";
4370
4371 status = "disabled";
4372
4373 cci1_i2c0: i2c-bus@0 {
4374 reg = <0>;
4375 clock-frequency = <1000000>;
4376 #address-cells = <1>;
4377 #size-cells = <0>;
4378 };
4379
4380 cci1_i2c1: i2c-bus@1 {
4381 reg = <1>;
4382 clock-frequency = <1000000>;
4383 #address-cells = <1>;
4384 #size-cells = <0>;
4385 };
4386 };
4387
4388 camss: camss@ac6a000 {
4389 compatible = "qcom,sm8250-camss";
4390 status = "disabled";
4391
4392 reg = <0 0x0ac6a000 0 0x2000>,
4393 <0 0x0ac6c000 0 0x2000>,
4394 <0 0x0ac6e000 0 0x1000>,
4395 <0 0x0ac70000 0 0x1000>,
4396 <0 0x0ac72000 0 0x1000>,
4397 <0 0x0ac74000 0 0x1000>,
4398 <0 0x0acb4000 0 0xd000>,
4399 <0 0x0acc3000 0 0xd000>,
4400 <0 0x0acd9000 0 0x2200>,
4401 <0 0x0acdb200 0 0x2200>;
4402 reg-names = "csiphy0",
4403 "csiphy1",
4404 "csiphy2",
4405 "csiphy3",
4406 "csiphy4",
4407 "csiphy5",
4408 "vfe0",
4409 "vfe1",
4410 "vfe_lite0",
4411 "vfe_lite1";
4412
4413 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4414 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4415 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4416 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4417 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
4418 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
4419 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4420 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4421 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4422 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
4423 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4424 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4425 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
4426 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
4427 interrupt-names = "csiphy0",
4428 "csiphy1",
4429 "csiphy2",
4430 "csiphy3",
4431 "csiphy4",
4432 "csiphy5",
4433 "csid0",
4434 "csid1",
4435 "csid2",
4436 "csid3",
4437 "vfe0",
4438 "vfe1",
4439 "vfe_lite0",
4440 "vfe_lite1";
4441
4442 power-domains = <&camcc IFE_0_GDSC>,
4443 <&camcc IFE_1_GDSC>,
4444 <&camcc TITAN_TOP_GDSC>;
4445
4446 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4447 <&gcc GCC_CAMERA_HF_AXI_CLK>,
4448 <&gcc GCC_CAMERA_SF_AXI_CLK>,
4449 <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4450 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
4451 <&camcc CAM_CC_CORE_AHB_CLK>,
4452 <&camcc CAM_CC_CPAS_AHB_CLK>,
4453 <&camcc CAM_CC_CSIPHY0_CLK>,
4454 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
4455 <&camcc CAM_CC_CSIPHY1_CLK>,
4456 <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
4457 <&camcc CAM_CC_CSIPHY2_CLK>,
4458 <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
4459 <&camcc CAM_CC_CSIPHY3_CLK>,
4460 <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
4461 <&camcc CAM_CC_CSIPHY4_CLK>,
4462 <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
4463 <&camcc CAM_CC_CSIPHY5_CLK>,
4464 <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
4465 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4466 <&camcc CAM_CC_IFE_0_AHB_CLK>,
4467 <&camcc CAM_CC_IFE_0_AXI_CLK>,
4468 <&camcc CAM_CC_IFE_0_CLK>,
4469 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4470 <&camcc CAM_CC_IFE_0_CSID_CLK>,
4471 <&camcc CAM_CC_IFE_0_AREG_CLK>,
4472 <&camcc CAM_CC_IFE_1_AHB_CLK>,
4473 <&camcc CAM_CC_IFE_1_AXI_CLK>,
4474 <&camcc CAM_CC_IFE_1_CLK>,
4475 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4476 <&camcc CAM_CC_IFE_1_CSID_CLK>,
4477 <&camcc CAM_CC_IFE_1_AREG_CLK>,
4478 <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
4479 <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
4480 <&camcc CAM_CC_IFE_LITE_CLK>,
4481 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4482 <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
4483
4484 clock-names = "cam_ahb_clk",
4485 "cam_hf_axi",
4486 "cam_sf_axi",
4487 "camnoc_axi",
4488 "camnoc_axi_src",
4489 "core_ahb",
4490 "cpas_ahb",
4491 "csiphy0",
4492 "csiphy0_timer",
4493 "csiphy1",
4494 "csiphy1_timer",
4495 "csiphy2",
4496 "csiphy2_timer",
4497 "csiphy3",
4498 "csiphy3_timer",
4499 "csiphy4",
4500 "csiphy4_timer",
4501 "csiphy5",
4502 "csiphy5_timer",
4503 "slow_ahb_src",
4504 "vfe0_ahb",
4505 "vfe0_axi",
4506 "vfe0",
4507 "vfe0_cphy_rx",
4508 "vfe0_csid",
4509 "vfe0_areg",
4510 "vfe1_ahb",
4511 "vfe1_axi",
4512 "vfe1",
4513 "vfe1_cphy_rx",
4514 "vfe1_csid",
4515 "vfe1_areg",
4516 "vfe_lite_ahb",
4517 "vfe_lite_axi",
4518 "vfe_lite",
4519 "vfe_lite_cphy_rx",
4520 "vfe_lite_csid";
4521
4522 iommus = <&apps_smmu 0x800 0x400>,
4523 <&apps_smmu 0x801 0x400>,
4524 <&apps_smmu 0x840 0x400>,
4525 <&apps_smmu 0x841 0x400>,
4526 <&apps_smmu 0xc00 0x400>,
4527 <&apps_smmu 0xc01 0x400>,
4528 <&apps_smmu 0xc40 0x400>,
4529 <&apps_smmu 0xc41 0x400>;
4530
4531 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>,
4532 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>,
4533 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>,
4534 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>;
4535 interconnect-names = "cam_ahb",
4536 "cam_hf_0_mnoc",
4537 "cam_sf_0_mnoc",
4538 "cam_sf_icp_mnoc";
4539
4540 ports {
4541 #address-cells = <1>;
4542 #size-cells = <0>;
4543
4544 port@0 {
4545 reg = <0>;
4546 };
4547
4548 port@1 {
4549 reg = <1>;
4550 };
4551
4552 port@2 {
4553 reg = <2>;
4554 };
4555
4556 port@3 {
4557 reg = <3>;
4558 };
4559
4560 port@4 {
4561 reg = <4>;
4562 };
4563
4564 port@5 {
4565 reg = <5>;
4566 };
4567 };
4568 };
4569
4570 camcc: clock-controller@ad00000 {
4571 compatible = "qcom,sm8250-camcc";
4572 reg = <0 0x0ad00000 0 0x10000>;
4573 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4574 <&rpmhcc RPMH_CXO_CLK>,
4575 <&rpmhcc RPMH_CXO_CLK_A>,
4576 <&sleep_clk>;
4577 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4578 power-domains = <&rpmhpd RPMHPD_MMCX>;
4579 required-opps = <&rpmhpd_opp_low_svs>;
4580 status = "disabled";
4581 #clock-cells = <1>;
4582 #reset-cells = <1>;
4583 #power-domain-cells = <1>;
4584 };
4585
4586 mdss: display-subsystem@ae00000 {
4587 compatible = "qcom,sm8250-mdss";
4588 reg = <0 0x0ae00000 0 0x1000>;
4589 reg-names = "mdss";
4590
4591 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
4592 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
4593 interconnect-names = "mdp0-mem", "mdp1-mem";
4594
4595 power-domains = <&dispcc MDSS_GDSC>;
4596
4597 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4598 <&gcc GCC_DISP_HF_AXI_CLK>,
4599 <&gcc GCC_DISP_SF_AXI_CLK>,
4600 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4601 clock-names = "iface", "bus", "nrt_bus", "core";
4602
4603 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4604 interrupt-controller;
4605 #interrupt-cells = <1>;
4606
4607 iommus = <&apps_smmu 0x820 0x402>;
4608
4609 status = "disabled";
4610
4611 #address-cells = <2>;
4612 #size-cells = <2>;
4613 ranges;
4614
4615 mdss_mdp: display-controller@ae01000 {
4616 compatible = "qcom,sm8250-dpu";
4617 reg = <0 0x0ae01000 0 0x8f000>,
4618 <0 0x0aeb0000 0 0x2008>;
4619 reg-names = "mdp", "vbif";
4620
4621 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4622 <&gcc GCC_DISP_HF_AXI_CLK>,
4623 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4624 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4625 clock-names = "iface", "bus", "core", "vsync";
4626
4627 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4628 assigned-clock-rates = <19200000>;
4629
4630 operating-points-v2 = <&mdp_opp_table>;
4631 power-domains = <&rpmhpd RPMHPD_MMCX>;
4632
4633 interrupt-parent = <&mdss>;
4634 interrupts = <0>;
4635
4636 ports {
4637 #address-cells = <1>;
4638 #size-cells = <0>;
4639
4640 port@0 {
4641 reg = <0>;
4642 dpu_intf1_out: endpoint {
4643 remote-endpoint = <&mdss_dsi0_in>;
4644 };
4645 };
4646
4647 port@1 {
4648 reg = <1>;
4649 dpu_intf2_out: endpoint {
4650 remote-endpoint = <&mdss_dsi1_in>;
4651 };
4652 };
4653
4654 port@2 {
4655 reg = <2>;
4656
4657 dpu_intf0_out: endpoint {
4658 remote-endpoint = <&mdss_dp_in>;
4659 };
4660 };
4661 };
4662
4663 mdp_opp_table: opp-table {
4664 compatible = "operating-points-v2";
4665
4666 opp-200000000 {
4667 opp-hz = /bits/ 64 <200000000>;
4668 required-opps = <&rpmhpd_opp_low_svs>;
4669 };
4670
4671 opp-300000000 {
4672 opp-hz = /bits/ 64 <300000000>;
4673 required-opps = <&rpmhpd_opp_svs>;
4674 };
4675
4676 opp-345000000 {
4677 opp-hz = /bits/ 64 <345000000>;
4678 required-opps = <&rpmhpd_opp_svs_l1>;
4679 };
4680
4681 opp-460000000 {
4682 opp-hz = /bits/ 64 <460000000>;
4683 required-opps = <&rpmhpd_opp_nom>;
4684 };
4685 };
4686 };
4687
4688 mdss_dp: displayport-controller@ae90000 {
4689 compatible = "qcom,sm8250-dp", "qcom,sm8350-dp";
4690 reg = <0 0xae90000 0 0x200>,
4691 <0 0xae90200 0 0x200>,
4692 <0 0xae90400 0 0x600>,
4693 <0 0xae91000 0 0x400>,
4694 <0 0xae91400 0 0x400>;
4695 interrupt-parent = <&mdss>;
4696 interrupts = <12>;
4697 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4698 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
4699 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
4700 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
4701 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
4702 clock-names = "core_iface",
4703 "core_aux",
4704 "ctrl_link",
4705 "ctrl_link_iface",
4706 "stream_pixel";
4707
4708 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4709 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
4710 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4711 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4712
4713 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
4714 phy-names = "dp";
4715
4716 #sound-dai-cells = <0>;
4717
4718 operating-points-v2 = <&dp_opp_table>;
4719 power-domains = <&rpmhpd SM8250_MMCX>;
4720
4721 status = "disabled";
4722
4723 ports {
4724 #address-cells = <1>;
4725 #size-cells = <0>;
4726
4727 port@0 {
4728 reg = <0>;
4729 mdss_dp_in: endpoint {
4730 remote-endpoint = <&dpu_intf0_out>;
4731 };
4732 };
4733
4734 port@1 {
4735 reg = <1>;
4736
4737 mdss_dp_out: endpoint {
4738 };
4739 };
4740 };
4741
4742 dp_opp_table: opp-table {
4743 compatible = "operating-points-v2";
4744
4745 opp-160000000 {
4746 opp-hz = /bits/ 64 <160000000>;
4747 required-opps = <&rpmhpd_opp_low_svs>;
4748 };
4749
4750 opp-270000000 {
4751 opp-hz = /bits/ 64 <270000000>;
4752 required-opps = <&rpmhpd_opp_svs>;
4753 };
4754
4755 opp-540000000 {
4756 opp-hz = /bits/ 64 <540000000>;
4757 required-opps = <&rpmhpd_opp_svs_l1>;
4758 };
4759
4760 opp-810000000 {
4761 opp-hz = /bits/ 64 <810000000>;
4762 required-opps = <&rpmhpd_opp_nom>;
4763 };
4764 };
4765 };
4766
4767 mdss_dsi0: dsi@ae94000 {
4768 compatible = "qcom,sm8250-dsi-ctrl",
4769 "qcom,mdss-dsi-ctrl";
4770 reg = <0 0x0ae94000 0 0x400>;
4771 reg-names = "dsi_ctrl";
4772
4773 interrupt-parent = <&mdss>;
4774 interrupts = <4>;
4775
4776 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4777 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4778 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4779 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4780 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4781 <&gcc GCC_DISP_HF_AXI_CLK>;
4782 clock-names = "byte",
4783 "byte_intf",
4784 "pixel",
4785 "core",
4786 "iface",
4787 "bus";
4788
4789 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4790 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4791
4792 operating-points-v2 = <&dsi_opp_table>;
4793 power-domains = <&rpmhpd RPMHPD_MMCX>;
4794
4795 phys = <&mdss_dsi0_phy>;
4796
4797 status = "disabled";
4798
4799 #address-cells = <1>;
4800 #size-cells = <0>;
4801
4802 ports {
4803 #address-cells = <1>;
4804 #size-cells = <0>;
4805
4806 port@0 {
4807 reg = <0>;
4808 mdss_dsi0_in: endpoint {
4809 remote-endpoint = <&dpu_intf1_out>;
4810 };
4811 };
4812
4813 port@1 {
4814 reg = <1>;
4815 mdss_dsi0_out: endpoint {
4816 };
4817 };
4818 };
4819
4820 dsi_opp_table: opp-table {
4821 compatible = "operating-points-v2";
4822
4823 opp-187500000 {
4824 opp-hz = /bits/ 64 <187500000>;
4825 required-opps = <&rpmhpd_opp_low_svs>;
4826 };
4827
4828 opp-300000000 {
4829 opp-hz = /bits/ 64 <300000000>;
4830 required-opps = <&rpmhpd_opp_svs>;
4831 };
4832
4833 opp-358000000 {
4834 opp-hz = /bits/ 64 <358000000>;
4835 required-opps = <&rpmhpd_opp_svs_l1>;
4836 };
4837 };
4838 };
4839
4840 mdss_dsi0_phy: phy@ae94400 {
4841 compatible = "qcom,dsi-phy-7nm";
4842 reg = <0 0x0ae94400 0 0x200>,
4843 <0 0x0ae94600 0 0x280>,
4844 <0 0x0ae94900 0 0x260>;
4845 reg-names = "dsi_phy",
4846 "dsi_phy_lane",
4847 "dsi_pll";
4848
4849 #clock-cells = <1>;
4850 #phy-cells = <0>;
4851
4852 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4853 <&rpmhcc RPMH_CXO_CLK>;
4854 clock-names = "iface", "ref";
4855
4856 status = "disabled";
4857 };
4858
4859 mdss_dsi1: dsi@ae96000 {
4860 compatible = "qcom,sm8250-dsi-ctrl",
4861 "qcom,mdss-dsi-ctrl";
4862 reg = <0 0x0ae96000 0 0x400>;
4863 reg-names = "dsi_ctrl";
4864
4865 interrupt-parent = <&mdss>;
4866 interrupts = <5>;
4867
4868 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4869 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4870 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4871 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4872 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4873 <&gcc GCC_DISP_HF_AXI_CLK>;
4874 clock-names = "byte",
4875 "byte_intf",
4876 "pixel",
4877 "core",
4878 "iface",
4879 "bus";
4880
4881 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4882 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4883
4884 operating-points-v2 = <&dsi_opp_table>;
4885 power-domains = <&rpmhpd RPMHPD_MMCX>;
4886
4887 phys = <&mdss_dsi1_phy>;
4888
4889 status = "disabled";
4890
4891 #address-cells = <1>;
4892 #size-cells = <0>;
4893
4894 ports {
4895 #address-cells = <1>;
4896 #size-cells = <0>;
4897
4898 port@0 {
4899 reg = <0>;
4900 mdss_dsi1_in: endpoint {
4901 remote-endpoint = <&dpu_intf2_out>;
4902 };
4903 };
4904
4905 port@1 {
4906 reg = <1>;
4907 mdss_dsi1_out: endpoint {
4908 };
4909 };
4910 };
4911 };
4912
4913 mdss_dsi1_phy: phy@ae96400 {
4914 compatible = "qcom,dsi-phy-7nm";
4915 reg = <0 0x0ae96400 0 0x200>,
4916 <0 0x0ae96600 0 0x280>,
4917 <0 0x0ae96900 0 0x260>;
4918 reg-names = "dsi_phy",
4919 "dsi_phy_lane",
4920 "dsi_pll";
4921
4922 #clock-cells = <1>;
4923 #phy-cells = <0>;
4924
4925 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4926 <&rpmhcc RPMH_CXO_CLK>;
4927 clock-names = "iface", "ref";
4928
4929 status = "disabled";
4930 };
4931 };
4932
4933 dispcc: clock-controller@af00000 {
4934 compatible = "qcom,sm8250-dispcc";
4935 reg = <0 0x0af00000 0 0x10000>;
4936 power-domains = <&rpmhpd RPMHPD_MMCX>;
4937 required-opps = <&rpmhpd_opp_low_svs>;
4938 clocks = <&rpmhcc RPMH_CXO_CLK>,
4939 <&mdss_dsi0_phy 0>,
4940 <&mdss_dsi0_phy 1>,
4941 <&mdss_dsi1_phy 0>,
4942 <&mdss_dsi1_phy 1>,
4943 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4944 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4945 clock-names = "bi_tcxo",
4946 "dsi0_phy_pll_out_byteclk",
4947 "dsi0_phy_pll_out_dsiclk",
4948 "dsi1_phy_pll_out_byteclk",
4949 "dsi1_phy_pll_out_dsiclk",
4950 "dp_phy_pll_link_clk",
4951 "dp_phy_pll_vco_div_clk";
4952 #clock-cells = <1>;
4953 #reset-cells = <1>;
4954 #power-domain-cells = <1>;
4955 };
4956
4957 pdc: interrupt-controller@b220000 {
4958 compatible = "qcom,sm8250-pdc", "qcom,pdc";
4959 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
4960 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4961 <125 63 1>, <126 716 12>;
4962 #interrupt-cells = <2>;
4963 interrupt-parent = <&intc>;
4964 interrupt-controller;
4965 };
4966
4967 tsens0: thermal-sensor@c263000 {
4968 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
4969 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4970 <0 0x0c222000 0 0x1ff>; /* SROT */
4971 #qcom,sensors = <16>;
4972 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4973 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4974 interrupt-names = "uplow", "critical";
4975 #thermal-sensor-cells = <1>;
4976 };
4977
4978 tsens1: thermal-sensor@c265000 {
4979 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
4980 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4981 <0 0x0c223000 0 0x1ff>; /* SROT */
4982 #qcom,sensors = <9>;
4983 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4984 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4985 interrupt-names = "uplow", "critical";
4986 #thermal-sensor-cells = <1>;
4987 };
4988
4989 aoss_qmp: power-management@c300000 {
4990 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
4991 reg = <0 0x0c300000 0 0x400>;
4992 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4993 IPCC_MPROC_SIGNAL_GLINK_QMP
4994 IRQ_TYPE_EDGE_RISING>;
4995 mboxes = <&ipcc IPCC_CLIENT_AOP
4996 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4997
4998 #clock-cells = <0>;
4999 };
5000
5001 sram@c3f0000 {
5002 compatible = "qcom,rpmh-stats";
5003 reg = <0 0x0c3f0000 0 0x400>;
5004 };
5005
5006 spmi_bus: spmi@c440000 {
5007 compatible = "qcom,spmi-pmic-arb";
5008 reg = <0x0 0x0c440000 0x0 0x0001100>,
5009 <0x0 0x0c600000 0x0 0x2000000>,
5010 <0x0 0x0e600000 0x0 0x0100000>,
5011 <0x0 0x0e700000 0x0 0x00a0000>,
5012 <0x0 0x0c40a000 0x0 0x0026000>;
5013 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5014 interrupt-names = "periph_irq";
5015 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5016 qcom,ee = <0>;
5017 qcom,channel = <0>;
5018 #address-cells = <2>;
5019 #size-cells = <0>;
5020 interrupt-controller;
5021 #interrupt-cells = <4>;
5022 };
5023
5024 tlmm: pinctrl@f100000 {
5025 compatible = "qcom,sm8250-pinctrl";
5026 reg = <0 0x0f100000 0 0x300000>,
5027 <0 0x0f500000 0 0x300000>,
5028 <0 0x0f900000 0 0x300000>;
5029 reg-names = "west", "south", "north";
5030 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5031 gpio-controller;
5032 #gpio-cells = <2>;
5033 interrupt-controller;
5034 #interrupt-cells = <2>;
5035 gpio-ranges = <&tlmm 0 0 181>;
5036 wakeup-parent = <&pdc>;
5037
5038 cam2_default: cam2-default-state {
5039 rst-pins {
5040 pins = "gpio78";
5041 function = "gpio";
5042 drive-strength = <2>;
5043 bias-disable;
5044 };
5045
5046 mclk-pins {
5047 pins = "gpio96";
5048 function = "cam_mclk";
5049 drive-strength = <16>;
5050 bias-disable;
5051 };
5052 };
5053
5054 cam2_suspend: cam2-suspend-state {
5055 rst-pins {
5056 pins = "gpio78";
5057 function = "gpio";
5058 drive-strength = <2>;
5059 bias-pull-down;
5060 output-low;
5061 };
5062
5063 mclk-pins {
5064 pins = "gpio96";
5065 function = "cam_mclk";
5066 drive-strength = <2>;
5067 bias-disable;
5068 };
5069 };
5070
5071 cci0_default: cci0-default-state {
5072 cci0_i2c0_default: cci0-i2c0-default-pins {
5073 /* SDA, SCL */
5074 pins = "gpio101", "gpio102";
5075 function = "cci_i2c";
5076
5077 bias-pull-up;
5078 drive-strength = <2>; /* 2 mA */
5079 };
5080
5081 cci0_i2c1_default: cci0-i2c1-default-pins {
5082 /* SDA, SCL */
5083 pins = "gpio103", "gpio104";
5084 function = "cci_i2c";
5085
5086 bias-pull-up;
5087 drive-strength = <2>; /* 2 mA */
5088 };
5089 };
5090
5091 cci0_sleep: cci0-sleep-state {
5092 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
5093 /* SDA, SCL */
5094 pins = "gpio101", "gpio102";
5095 function = "cci_i2c";
5096
5097 drive-strength = <2>; /* 2 mA */
5098 bias-pull-down;
5099 };
5100
5101 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
5102 /* SDA, SCL */
5103 pins = "gpio103", "gpio104";
5104 function = "cci_i2c";
5105
5106 drive-strength = <2>; /* 2 mA */
5107 bias-pull-down;
5108 };
5109 };
5110
5111 cci1_default: cci1-default-state {
5112 cci1_i2c0_default: cci1-i2c0-default-pins {
5113 /* SDA, SCL */
5114 pins = "gpio105","gpio106";
5115 function = "cci_i2c";
5116
5117 bias-pull-up;
5118 drive-strength = <2>; /* 2 mA */
5119 };
5120
5121 cci1_i2c1_default: cci1-i2c1-default-pins {
5122 /* SDA, SCL */
5123 pins = "gpio107","gpio108";
5124 function = "cci_i2c";
5125
5126 bias-pull-up;
5127 drive-strength = <2>; /* 2 mA */
5128 };
5129 };
5130
5131 cci1_sleep: cci1-sleep-state {
5132 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
5133 /* SDA, SCL */
5134 pins = "gpio105","gpio106";
5135 function = "cci_i2c";
5136
5137 bias-pull-down;
5138 drive-strength = <2>; /* 2 mA */
5139 };
5140
5141 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
5142 /* SDA, SCL */
5143 pins = "gpio107","gpio108";
5144 function = "cci_i2c";
5145
5146 bias-pull-down;
5147 drive-strength = <2>; /* 2 mA */
5148 };
5149 };
5150
5151 pri_mi2s_active: pri-mi2s-active-state {
5152 sclk-pins {
5153 pins = "gpio138";
5154 function = "mi2s0_sck";
5155 drive-strength = <8>;
5156 bias-disable;
5157 };
5158
5159 ws-pins {
5160 pins = "gpio141";
5161 function = "mi2s0_ws";
5162 drive-strength = <8>;
5163 output-high;
5164 };
5165
5166 data0-pins {
5167 pins = "gpio139";
5168 function = "mi2s0_data0";
5169 drive-strength = <8>;
5170 bias-disable;
5171 output-high;
5172 };
5173
5174 data1-pins {
5175 pins = "gpio140";
5176 function = "mi2s0_data1";
5177 drive-strength = <8>;
5178 output-high;
5179 };
5180 };
5181
5182 qup_i2c0_default: qup-i2c0-default-state {
5183 pins = "gpio28", "gpio29";
5184 function = "qup0";
5185 drive-strength = <2>;
5186 bias-disable;
5187 };
5188
5189 qup_i2c1_default: qup-i2c1-default-state {
5190 pins = "gpio4", "gpio5";
5191 function = "qup1";
5192 drive-strength = <2>;
5193 bias-disable;
5194 };
5195
5196 qup_i2c2_default: qup-i2c2-default-state {
5197 pins = "gpio115", "gpio116";
5198 function = "qup2";
5199 drive-strength = <2>;
5200 bias-disable;
5201 };
5202
5203 qup_i2c3_default: qup-i2c3-default-state {
5204 pins = "gpio119", "gpio120";
5205 function = "qup3";
5206 drive-strength = <2>;
5207 bias-disable;
5208 };
5209
5210 qup_i2c4_default: qup-i2c4-default-state {
5211 pins = "gpio8", "gpio9";
5212 function = "qup4";
5213 drive-strength = <2>;
5214 bias-disable;
5215 };
5216
5217 qup_i2c5_default: qup-i2c5-default-state {
5218 pins = "gpio12", "gpio13";
5219 function = "qup5";
5220 drive-strength = <2>;
5221 bias-disable;
5222 };
5223
5224 qup_i2c6_default: qup-i2c6-default-state {
5225 pins = "gpio16", "gpio17";
5226 function = "qup6";
5227 drive-strength = <2>;
5228 bias-disable;
5229 };
5230
5231 qup_i2c7_default: qup-i2c7-default-state {
5232 pins = "gpio20", "gpio21";
5233 function = "qup7";
5234 drive-strength = <2>;
5235 bias-disable;
5236 };
5237
5238 qup_i2c8_default: qup-i2c8-default-state {
5239 pins = "gpio24", "gpio25";
5240 function = "qup8";
5241 drive-strength = <2>;
5242 bias-disable;
5243 };
5244
5245 qup_i2c9_default: qup-i2c9-default-state {
5246 pins = "gpio125", "gpio126";
5247 function = "qup9";
5248 drive-strength = <2>;
5249 bias-disable;
5250 };
5251
5252 qup_i2c10_default: qup-i2c10-default-state {
5253 pins = "gpio129", "gpio130";
5254 function = "qup10";
5255 drive-strength = <2>;
5256 bias-disable;
5257 };
5258
5259 qup_i2c11_default: qup-i2c11-default-state {
5260 pins = "gpio60", "gpio61";
5261 function = "qup11";
5262 drive-strength = <2>;
5263 bias-disable;
5264 };
5265
5266 qup_i2c12_default: qup-i2c12-default-state {
5267 pins = "gpio32", "gpio33";
5268 function = "qup12";
5269 drive-strength = <2>;
5270 bias-disable;
5271 };
5272
5273 qup_i2c13_default: qup-i2c13-default-state {
5274 pins = "gpio36", "gpio37";
5275 function = "qup13";
5276 drive-strength = <2>;
5277 bias-disable;
5278 };
5279
5280 qup_i2c14_default: qup-i2c14-default-state {
5281 pins = "gpio40", "gpio41";
5282 function = "qup14";
5283 drive-strength = <2>;
5284 bias-disable;
5285 };
5286
5287 qup_i2c15_default: qup-i2c15-default-state {
5288 pins = "gpio44", "gpio45";
5289 function = "qup15";
5290 drive-strength = <2>;
5291 bias-disable;
5292 };
5293
5294 qup_i2c16_default: qup-i2c16-default-state {
5295 pins = "gpio48", "gpio49";
5296 function = "qup16";
5297 drive-strength = <2>;
5298 bias-disable;
5299 };
5300
5301 qup_i2c17_default: qup-i2c17-default-state {
5302 pins = "gpio52", "gpio53";
5303 function = "qup17";
5304 drive-strength = <2>;
5305 bias-disable;
5306 };
5307
5308 qup_i2c18_default: qup-i2c18-default-state {
5309 pins = "gpio56", "gpio57";
5310 function = "qup18";
5311 drive-strength = <2>;
5312 bias-disable;
5313 };
5314
5315 qup_i2c19_default: qup-i2c19-default-state {
5316 pins = "gpio0", "gpio1";
5317 function = "qup19";
5318 drive-strength = <2>;
5319 bias-disable;
5320 };
5321
5322 qup_spi0_cs: qup-spi0-cs-state {
5323 pins = "gpio31";
5324 function = "qup0";
5325 };
5326
5327 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
5328 pins = "gpio31";
5329 function = "gpio";
5330 };
5331
5332 qup_spi0_data_clk: qup-spi0-data-clk-state {
5333 pins = "gpio28", "gpio29",
5334 "gpio30";
5335 function = "qup0";
5336 };
5337
5338 qup_spi1_cs: qup-spi1-cs-state {
5339 pins = "gpio7";
5340 function = "qup1";
5341 };
5342
5343 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
5344 pins = "gpio7";
5345 function = "gpio";
5346 };
5347
5348 qup_spi1_data_clk: qup-spi1-data-clk-state {
5349 pins = "gpio4", "gpio5",
5350 "gpio6";
5351 function = "qup1";
5352 };
5353
5354 qup_spi2_cs: qup-spi2-cs-state {
5355 pins = "gpio118";
5356 function = "qup2";
5357 };
5358
5359 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5360 pins = "gpio118";
5361 function = "gpio";
5362 };
5363
5364 qup_spi2_data_clk: qup-spi2-data-clk-state {
5365 pins = "gpio115", "gpio116",
5366 "gpio117";
5367 function = "qup2";
5368 };
5369
5370 qup_spi3_cs: qup-spi3-cs-state {
5371 pins = "gpio122";
5372 function = "qup3";
5373 };
5374
5375 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5376 pins = "gpio122";
5377 function = "gpio";
5378 };
5379
5380 qup_spi3_data_clk: qup-spi3-data-clk-state {
5381 pins = "gpio119", "gpio120",
5382 "gpio121";
5383 function = "qup3";
5384 };
5385
5386 qup_spi4_cs: qup-spi4-cs-state {
5387 pins = "gpio11";
5388 function = "qup4";
5389 };
5390
5391 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5392 pins = "gpio11";
5393 function = "gpio";
5394 };
5395
5396 qup_spi4_data_clk: qup-spi4-data-clk-state {
5397 pins = "gpio8", "gpio9",
5398 "gpio10";
5399 function = "qup4";
5400 };
5401
5402 qup_spi5_cs: qup-spi5-cs-state {
5403 pins = "gpio15";
5404 function = "qup5";
5405 };
5406
5407 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5408 pins = "gpio15";
5409 function = "gpio";
5410 };
5411
5412 qup_spi5_data_clk: qup-spi5-data-clk-state {
5413 pins = "gpio12", "gpio13",
5414 "gpio14";
5415 function = "qup5";
5416 };
5417
5418 qup_spi6_cs: qup-spi6-cs-state {
5419 pins = "gpio19";
5420 function = "qup6";
5421 };
5422
5423 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5424 pins = "gpio19";
5425 function = "gpio";
5426 };
5427
5428 qup_spi6_data_clk: qup-spi6-data-clk-state {
5429 pins = "gpio16", "gpio17",
5430 "gpio18";
5431 function = "qup6";
5432 };
5433
5434 qup_spi7_cs: qup-spi7-cs-state {
5435 pins = "gpio23";
5436 function = "qup7";
5437 };
5438
5439 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5440 pins = "gpio23";
5441 function = "gpio";
5442 };
5443
5444 qup_spi7_data_clk: qup-spi7-data-clk-state {
5445 pins = "gpio20", "gpio21",
5446 "gpio22";
5447 function = "qup7";
5448 };
5449
5450 qup_spi8_cs: qup-spi8-cs-state {
5451 pins = "gpio27";
5452 function = "qup8";
5453 };
5454
5455 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5456 pins = "gpio27";
5457 function = "gpio";
5458 };
5459
5460 qup_spi8_data_clk: qup-spi8-data-clk-state {
5461 pins = "gpio24", "gpio25",
5462 "gpio26";
5463 function = "qup8";
5464 };
5465
5466 qup_spi9_cs: qup-spi9-cs-state {
5467 pins = "gpio128";
5468 function = "qup9";
5469 };
5470
5471 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5472 pins = "gpio128";
5473 function = "gpio";
5474 };
5475
5476 qup_spi9_data_clk: qup-spi9-data-clk-state {
5477 pins = "gpio125", "gpio126",
5478 "gpio127";
5479 function = "qup9";
5480 };
5481
5482 qup_spi10_cs: qup-spi10-cs-state {
5483 pins = "gpio132";
5484 function = "qup10";
5485 };
5486
5487 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5488 pins = "gpio132";
5489 function = "gpio";
5490 };
5491
5492 qup_spi10_data_clk: qup-spi10-data-clk-state {
5493 pins = "gpio129", "gpio130",
5494 "gpio131";
5495 function = "qup10";
5496 };
5497
5498 qup_spi11_cs: qup-spi11-cs-state {
5499 pins = "gpio63";
5500 function = "qup11";
5501 };
5502
5503 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5504 pins = "gpio63";
5505 function = "gpio";
5506 };
5507
5508 qup_spi11_data_clk: qup-spi11-data-clk-state {
5509 pins = "gpio60", "gpio61",
5510 "gpio62";
5511 function = "qup11";
5512 };
5513
5514 qup_spi12_cs: qup-spi12-cs-state {
5515 pins = "gpio35";
5516 function = "qup12";
5517 };
5518
5519 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5520 pins = "gpio35";
5521 function = "gpio";
5522 };
5523
5524 qup_spi12_data_clk: qup-spi12-data-clk-state {
5525 pins = "gpio32", "gpio33",
5526 "gpio34";
5527 function = "qup12";
5528 };
5529
5530 qup_spi13_cs: qup-spi13-cs-state {
5531 pins = "gpio39";
5532 function = "qup13";
5533 };
5534
5535 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5536 pins = "gpio39";
5537 function = "gpio";
5538 };
5539
5540 qup_spi13_data_clk: qup-spi13-data-clk-state {
5541 pins = "gpio36", "gpio37",
5542 "gpio38";
5543 function = "qup13";
5544 };
5545
5546 qup_spi14_cs: qup-spi14-cs-state {
5547 pins = "gpio43";
5548 function = "qup14";
5549 };
5550
5551 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5552 pins = "gpio43";
5553 function = "gpio";
5554 };
5555
5556 qup_spi14_data_clk: qup-spi14-data-clk-state {
5557 pins = "gpio40", "gpio41",
5558 "gpio42";
5559 function = "qup14";
5560 };
5561
5562 qup_spi15_cs: qup-spi15-cs-state {
5563 pins = "gpio47";
5564 function = "qup15";
5565 };
5566
5567 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5568 pins = "gpio47";
5569 function = "gpio";
5570 };
5571
5572 qup_spi15_data_clk: qup-spi15-data-clk-state {
5573 pins = "gpio44", "gpio45",
5574 "gpio46";
5575 function = "qup15";
5576 };
5577
5578 qup_spi16_cs: qup-spi16-cs-state {
5579 pins = "gpio51";
5580 function = "qup16";
5581 };
5582
5583 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
5584 pins = "gpio51";
5585 function = "gpio";
5586 };
5587
5588 qup_spi16_data_clk: qup-spi16-data-clk-state {
5589 pins = "gpio48", "gpio49",
5590 "gpio50";
5591 function = "qup16";
5592 };
5593
5594 qup_spi17_cs: qup-spi17-cs-state {
5595 pins = "gpio55";
5596 function = "qup17";
5597 };
5598
5599 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state {
5600 pins = "gpio55";
5601 function = "gpio";
5602 };
5603
5604 qup_spi17_data_clk: qup-spi17-data-clk-state {
5605 pins = "gpio52", "gpio53",
5606 "gpio54";
5607 function = "qup17";
5608 };
5609
5610 qup_spi18_cs: qup-spi18-cs-state {
5611 pins = "gpio59";
5612 function = "qup18";
5613 };
5614
5615 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state {
5616 pins = "gpio59";
5617 function = "gpio";
5618 };
5619
5620 qup_spi18_data_clk: qup-spi18-data-clk-state {
5621 pins = "gpio56", "gpio57",
5622 "gpio58";
5623 function = "qup18";
5624 };
5625
5626 qup_spi19_cs: qup-spi19-cs-state {
5627 pins = "gpio3";
5628 function = "qup19";
5629 };
5630
5631 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state {
5632 pins = "gpio3";
5633 function = "gpio";
5634 };
5635
5636 qup_spi19_data_clk: qup-spi19-data-clk-state {
5637 pins = "gpio0", "gpio1",
5638 "gpio2";
5639 function = "qup19";
5640 };
5641
5642 qup_uart2_default: qup-uart2-default-state {
5643 pins = "gpio117", "gpio118";
5644 function = "qup2";
5645 };
5646
5647 qup_uart6_default: qup-uart6-default-state {
5648 pins = "gpio16", "gpio17", "gpio18", "gpio19";
5649 function = "qup6";
5650 };
5651
5652 qup_uart12_default: qup-uart12-default-state {
5653 pins = "gpio34", "gpio35";
5654 function = "qup12";
5655 };
5656
5657 qup_uart17_default: qup-uart17-default-state {
5658 pins = "gpio52", "gpio53", "gpio54", "gpio55";
5659 function = "qup17";
5660 };
5661
5662 qup_uart18_default: qup-uart18-default-state {
5663 pins = "gpio58", "gpio59";
5664 function = "qup18";
5665 };
5666
5667 tert_mi2s_active: tert-mi2s-active-state {
5668 sck-pins {
5669 pins = "gpio133";
5670 function = "mi2s2_sck";
5671 drive-strength = <8>;
5672 bias-disable;
5673 };
5674
5675 data0-pins {
5676 pins = "gpio134";
5677 function = "mi2s2_data0";
5678 drive-strength = <8>;
5679 bias-disable;
5680 output-high;
5681 };
5682
5683 ws-pins {
5684 pins = "gpio135";
5685 function = "mi2s2_ws";
5686 drive-strength = <8>;
5687 output-high;
5688 };
5689 };
5690
5691 sdc2_sleep_state: sdc2-sleep-state {
5692 clk-pins {
5693 pins = "sdc2_clk";
5694 drive-strength = <2>;
5695 bias-disable;
5696 };
5697
5698 cmd-pins {
5699 pins = "sdc2_cmd";
5700 drive-strength = <2>;
5701 bias-pull-up;
5702 };
5703
5704 data-pins {
5705 pins = "sdc2_data";
5706 drive-strength = <2>;
5707 bias-pull-up;
5708 };
5709 };
5710
5711 pcie0_default_state: pcie0-default-state {
5712 perst-pins {
5713 pins = "gpio79";
5714 function = "gpio";
5715 drive-strength = <2>;
5716 bias-pull-down;
5717 };
5718
5719 clkreq-pins {
5720 pins = "gpio80";
5721 function = "pci_e0";
5722 drive-strength = <2>;
5723 bias-pull-up;
5724 };
5725
5726 wake-pins {
5727 pins = "gpio81";
5728 function = "gpio";
5729 drive-strength = <2>;
5730 bias-pull-up;
5731 };
5732 };
5733
5734 pcie1_default_state: pcie1-default-state {
5735 perst-pins {
5736 pins = "gpio82";
5737 function = "gpio";
5738 drive-strength = <2>;
5739 bias-pull-down;
5740 };
5741
5742 clkreq-pins {
5743 pins = "gpio83";
5744 function = "pci_e1";
5745 drive-strength = <2>;
5746 bias-pull-up;
5747 };
5748
5749 wake-pins {
5750 pins = "gpio84";
5751 function = "gpio";
5752 drive-strength = <2>;
5753 bias-pull-up;
5754 };
5755 };
5756
5757 pcie2_default_state: pcie2-default-state {
5758 perst-pins {
5759 pins = "gpio85";
5760 function = "gpio";
5761 drive-strength = <2>;
5762 bias-pull-down;
5763 };
5764
5765 clkreq-pins {
5766 pins = "gpio86";
5767 function = "pci_e2";
5768 drive-strength = <2>;
5769 bias-pull-up;
5770 };
5771
5772 wake-pins {
5773 pins = "gpio87";
5774 function = "gpio";
5775 drive-strength = <2>;
5776 bias-pull-up;
5777 };
5778 };
5779 };
5780
5781 apps_smmu: iommu@15000000 {
5782 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5783 reg = <0 0x15000000 0 0x100000>;
5784 #iommu-cells = <2>;
5785 #global-interrupts = <2>;
5786 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5787 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5788 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5789 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5790 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5791 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5792 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5793 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5794 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5795 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5796 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5797 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5798 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5799 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5800 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5801 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5802 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5803 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5804 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5805 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5806 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5807 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5808 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5809 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5810 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5811 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5812 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5813 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5814 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5815 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5816 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5817 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5818 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5819 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5820 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5821 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5822 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5823 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5824 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5825 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5826 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5827 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5828 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5829 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5830 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5831 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5832 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5833 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5834 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5835 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5836 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5837 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5838 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5839 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5840 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5841 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5842 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5843 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5844 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5845 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5846 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5847 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5848 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5849 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5850 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5851 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5852 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5853 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5854 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5855 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5856 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5857 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5858 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5859 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5860 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5861 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5862 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5863 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5864 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5865 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5866 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5867 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5868 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5869 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5870 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5871 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5872 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5873 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5874 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5875 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5876 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5877 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5878 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5879 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5880 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5881 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5882 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5883 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5884 dma-coherent;
5885 };
5886
5887 adsp: remoteproc@17300000 {
5888 compatible = "qcom,sm8250-adsp-pas";
5889 reg = <0 0x17300000 0 0x100>;
5890
5891 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
5892 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5893 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5894 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5895 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5896 interrupt-names = "wdog", "fatal", "ready",
5897 "handover", "stop-ack";
5898
5899 clocks = <&rpmhcc RPMH_CXO_CLK>;
5900 clock-names = "xo";
5901
5902 power-domains = <&rpmhpd RPMHPD_LCX>,
5903 <&rpmhpd RPMHPD_LMX>;
5904 power-domain-names = "lcx", "lmx";
5905
5906 memory-region = <&adsp_mem>;
5907
5908 qcom,qmp = <&aoss_qmp>;
5909
5910 qcom,smem-states = <&smp2p_adsp_out 0>;
5911 qcom,smem-state-names = "stop";
5912
5913 status = "disabled";
5914
5915 glink-edge {
5916 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5917 IPCC_MPROC_SIGNAL_GLINK_QMP
5918 IRQ_TYPE_EDGE_RISING>;
5919 mboxes = <&ipcc IPCC_CLIENT_LPASS
5920 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5921
5922 label = "lpass";
5923 qcom,remote-pid = <2>;
5924
5925 apr {
5926 compatible = "qcom,apr-v2";
5927 qcom,glink-channels = "apr_audio_svc";
5928 qcom,domain = <APR_DOMAIN_ADSP>;
5929 #address-cells = <1>;
5930 #size-cells = <0>;
5931
5932 service@3 {
5933 reg = <APR_SVC_ADSP_CORE>;
5934 compatible = "qcom,q6core";
5935 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5936 };
5937
5938 q6afe: service@4 {
5939 compatible = "qcom,q6afe";
5940 reg = <APR_SVC_AFE>;
5941 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5942 q6afedai: dais {
5943 compatible = "qcom,q6afe-dais";
5944 #address-cells = <1>;
5945 #size-cells = <0>;
5946 #sound-dai-cells = <1>;
5947 };
5948
5949 q6afecc: clock-controller {
5950 compatible = "qcom,q6afe-clocks";
5951 #clock-cells = <2>;
5952 };
5953 };
5954
5955 q6asm: service@7 {
5956 compatible = "qcom,q6asm";
5957 reg = <APR_SVC_ASM>;
5958 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5959 q6asmdai: dais {
5960 compatible = "qcom,q6asm-dais";
5961 #address-cells = <1>;
5962 #size-cells = <0>;
5963 #sound-dai-cells = <1>;
5964 iommus = <&apps_smmu 0x1801 0x0>;
5965 };
5966 };
5967
5968 q6adm: service@8 {
5969 compatible = "qcom,q6adm";
5970 reg = <APR_SVC_ADM>;
5971 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5972 q6routing: routing {
5973 compatible = "qcom,q6adm-routing";
5974 #sound-dai-cells = <0>;
5975 };
5976 };
5977 };
5978
5979 fastrpc {
5980 compatible = "qcom,fastrpc";
5981 qcom,glink-channels = "fastrpcglink-apps-dsp";
5982 label = "adsp";
5983 qcom,non-secure-domain;
5984 #address-cells = <1>;
5985 #size-cells = <0>;
5986
5987 compute-cb@3 {
5988 compatible = "qcom,fastrpc-compute-cb";
5989 reg = <3>;
5990 iommus = <&apps_smmu 0x1803 0x0>;
5991 };
5992
5993 compute-cb@4 {
5994 compatible = "qcom,fastrpc-compute-cb";
5995 reg = <4>;
5996 iommus = <&apps_smmu 0x1804 0x0>;
5997 };
5998
5999 compute-cb@5 {
6000 compatible = "qcom,fastrpc-compute-cb";
6001 reg = <5>;
6002 iommus = <&apps_smmu 0x1805 0x0>;
6003 };
6004 };
6005 };
6006 };
6007
6008 intc: interrupt-controller@17a00000 {
6009 compatible = "arm,gic-v3";
6010 #interrupt-cells = <3>;
6011 interrupt-controller;
6012 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
6013 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
6014 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
6015 };
6016
6017 watchdog@17c10000 {
6018 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6019 reg = <0 0x17c10000 0 0x1000>;
6020 clocks = <&sleep_clk>;
6021 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
6022 };
6023
6024 timer@17c20000 {
6025 #address-cells = <1>;
6026 #size-cells = <1>;
6027 ranges = <0 0 0 0x20000000>;
6028 compatible = "arm,armv7-timer-mem";
6029 reg = <0x0 0x17c20000 0x0 0x1000>;
6030 clock-frequency = <19200000>;
6031
6032 frame@17c21000 {
6033 frame-number = <0>;
6034 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
6035 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
6036 reg = <0x17c21000 0x1000>,
6037 <0x17c22000 0x1000>;
6038 };
6039
6040 frame@17c23000 {
6041 frame-number = <1>;
6042 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
6043 reg = <0x17c23000 0x1000>;
6044 status = "disabled";
6045 };
6046
6047 frame@17c25000 {
6048 frame-number = <2>;
6049 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6050 reg = <0x17c25000 0x1000>;
6051 status = "disabled";
6052 };
6053
6054 frame@17c27000 {
6055 frame-number = <3>;
6056 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6057 reg = <0x17c27000 0x1000>;
6058 status = "disabled";
6059 };
6060
6061 frame@17c29000 {
6062 frame-number = <4>;
6063 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
6064 reg = <0x17c29000 0x1000>;
6065 status = "disabled";
6066 };
6067
6068 frame@17c2b000 {
6069 frame-number = <5>;
6070 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
6071 reg = <0x17c2b000 0x1000>;
6072 status = "disabled";
6073 };
6074
6075 frame@17c2d000 {
6076 frame-number = <6>;
6077 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
6078 reg = <0x17c2d000 0x1000>;
6079 status = "disabled";
6080 };
6081 };
6082
6083 apps_rsc: rsc@18200000 {
6084 label = "apps_rsc";
6085 compatible = "qcom,rpmh-rsc";
6086 reg = <0x0 0x18200000 0x0 0x10000>,
6087 <0x0 0x18210000 0x0 0x10000>,
6088 <0x0 0x18220000 0x0 0x10000>;
6089 reg-names = "drv-0", "drv-1", "drv-2";
6090 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
6091 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
6092 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
6093 qcom,tcs-offset = <0xd00>;
6094 qcom,drv-id = <2>;
6095 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6096 <WAKE_TCS 3>, <CONTROL_TCS 1>;
6097 power-domains = <&CLUSTER_PD>;
6098
6099 rpmhcc: clock-controller {
6100 compatible = "qcom,sm8250-rpmh-clk";
6101 #clock-cells = <1>;
6102 clock-names = "xo";
6103 clocks = <&xo_board>;
6104 };
6105
6106 rpmhpd: power-controller {
6107 compatible = "qcom,sm8250-rpmhpd";
6108 #power-domain-cells = <1>;
6109 operating-points-v2 = <&rpmhpd_opp_table>;
6110
6111 rpmhpd_opp_table: opp-table {
6112 compatible = "operating-points-v2";
6113
6114 rpmhpd_opp_ret: opp1 {
6115 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6116 };
6117
6118 rpmhpd_opp_min_svs: opp2 {
6119 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6120 };
6121
6122 rpmhpd_opp_low_svs: opp3 {
6123 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6124 };
6125
6126 rpmhpd_opp_svs: opp4 {
6127 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6128 };
6129
6130 rpmhpd_opp_svs_l1: opp5 {
6131 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6132 };
6133
6134 rpmhpd_opp_nom: opp6 {
6135 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6136 };
6137
6138 rpmhpd_opp_nom_l1: opp7 {
6139 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6140 };
6141
6142 rpmhpd_opp_nom_l2: opp8 {
6143 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6144 };
6145
6146 rpmhpd_opp_turbo: opp9 {
6147 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6148 };
6149
6150 rpmhpd_opp_turbo_l1: opp10 {
6151 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6152 };
6153 };
6154 };
6155
6156 apps_bcm_voter: bcm-voter {
6157 compatible = "qcom,bcm-voter";
6158 };
6159 };
6160
6161 epss_l3: interconnect@18590000 {
6162 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
6163 reg = <0 0x18590000 0 0x1000>;
6164
6165 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6166 clock-names = "xo", "alternate";
6167
6168 #interconnect-cells = <1>;
6169 };
6170
6171 cpufreq_hw: cpufreq@18591000 {
6172 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6173 reg = <0 0x18591000 0 0x1000>,
6174 <0 0x18592000 0 0x1000>,
6175 <0 0x18593000 0 0x1000>;
6176 reg-names = "freq-domain0", "freq-domain1",
6177 "freq-domain2";
6178
6179 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6180 clock-names = "xo", "alternate";
6181 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
6182 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
6183 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
6184 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
6185 #freq-domain-cells = <1>;
6186 #clock-cells = <1>;
6187 };
6188 };
6189
6190 sound: sound {
6191 };
6192
6193 timer {
6194 compatible = "arm,armv8-timer";
6195 interrupts = <GIC_PPI 13
6196 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6197 <GIC_PPI 14
6198 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6199 <GIC_PPI 11
6200 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6201 <GIC_PPI 10
6202 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6203 };
6204
6205 thermal-zones {
6206 cpu0-thermal {
6207 polling-delay-passive = <250>;
6208 polling-delay = <1000>;
6209
6210 thermal-sensors = <&tsens0 1>;
6211
6212 trips {
6213 cpu0_alert0: trip-point0 {
6214 temperature = <90000>;
6215 hysteresis = <2000>;
6216 type = "passive";
6217 };
6218
6219 cpu0_alert1: trip-point1 {
6220 temperature = <95000>;
6221 hysteresis = <2000>;
6222 type = "passive";
6223 };
6224
6225 cpu0_crit: cpu-crit {
6226 temperature = <110000>;
6227 hysteresis = <1000>;
6228 type = "critical";
6229 };
6230 };
6231
6232 cooling-maps {
6233 map0 {
6234 trip = <&cpu0_alert0>;
6235 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6236 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6237 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6238 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6239 };
6240 map1 {
6241 trip = <&cpu0_alert1>;
6242 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6243 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6244 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6245 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6246 };
6247 };
6248 };
6249
6250 cpu1-thermal {
6251 polling-delay-passive = <250>;
6252 polling-delay = <1000>;
6253
6254 thermal-sensors = <&tsens0 2>;
6255
6256 trips {
6257 cpu1_alert0: trip-point0 {
6258 temperature = <90000>;
6259 hysteresis = <2000>;
6260 type = "passive";
6261 };
6262
6263 cpu1_alert1: trip-point1 {
6264 temperature = <95000>;
6265 hysteresis = <2000>;
6266 type = "passive";
6267 };
6268
6269 cpu1_crit: cpu-crit {
6270 temperature = <110000>;
6271 hysteresis = <1000>;
6272 type = "critical";
6273 };
6274 };
6275
6276 cooling-maps {
6277 map0 {
6278 trip = <&cpu1_alert0>;
6279 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6280 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6281 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6282 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6283 };
6284 map1 {
6285 trip = <&cpu1_alert1>;
6286 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6287 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6288 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6289 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6290 };
6291 };
6292 };
6293
6294 cpu2-thermal {
6295 polling-delay-passive = <250>;
6296 polling-delay = <1000>;
6297
6298 thermal-sensors = <&tsens0 3>;
6299
6300 trips {
6301 cpu2_alert0: trip-point0 {
6302 temperature = <90000>;
6303 hysteresis = <2000>;
6304 type = "passive";
6305 };
6306
6307 cpu2_alert1: trip-point1 {
6308 temperature = <95000>;
6309 hysteresis = <2000>;
6310 type = "passive";
6311 };
6312
6313 cpu2_crit: cpu-crit {
6314 temperature = <110000>;
6315 hysteresis = <1000>;
6316 type = "critical";
6317 };
6318 };
6319
6320 cooling-maps {
6321 map0 {
6322 trip = <&cpu2_alert0>;
6323 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6324 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6325 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6326 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6327 };
6328 map1 {
6329 trip = <&cpu2_alert1>;
6330 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6331 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6332 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6333 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6334 };
6335 };
6336 };
6337
6338 cpu3-thermal {
6339 polling-delay-passive = <250>;
6340 polling-delay = <1000>;
6341
6342 thermal-sensors = <&tsens0 4>;
6343
6344 trips {
6345 cpu3_alert0: trip-point0 {
6346 temperature = <90000>;
6347 hysteresis = <2000>;
6348 type = "passive";
6349 };
6350
6351 cpu3_alert1: trip-point1 {
6352 temperature = <95000>;
6353 hysteresis = <2000>;
6354 type = "passive";
6355 };
6356
6357 cpu3_crit: cpu-crit {
6358 temperature = <110000>;
6359 hysteresis = <1000>;
6360 type = "critical";
6361 };
6362 };
6363
6364 cooling-maps {
6365 map0 {
6366 trip = <&cpu3_alert0>;
6367 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6368 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6369 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6370 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6371 };
6372 map1 {
6373 trip = <&cpu3_alert1>;
6374 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6375 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6376 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6377 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6378 };
6379 };
6380 };
6381
6382 cpu4-top-thermal {
6383 polling-delay-passive = <250>;
6384 polling-delay = <1000>;
6385
6386 thermal-sensors = <&tsens0 7>;
6387
6388 trips {
6389 cpu4_top_alert0: trip-point0 {
6390 temperature = <90000>;
6391 hysteresis = <2000>;
6392 type = "passive";
6393 };
6394
6395 cpu4_top_alert1: trip-point1 {
6396 temperature = <95000>;
6397 hysteresis = <2000>;
6398 type = "passive";
6399 };
6400
6401 cpu4_top_crit: cpu-crit {
6402 temperature = <110000>;
6403 hysteresis = <1000>;
6404 type = "critical";
6405 };
6406 };
6407
6408 cooling-maps {
6409 map0 {
6410 trip = <&cpu4_top_alert0>;
6411 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6412 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6413 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6414 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6415 };
6416 map1 {
6417 trip = <&cpu4_top_alert1>;
6418 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6419 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6420 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6421 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6422 };
6423 };
6424 };
6425
6426 cpu5-top-thermal {
6427 polling-delay-passive = <250>;
6428 polling-delay = <1000>;
6429
6430 thermal-sensors = <&tsens0 8>;
6431
6432 trips {
6433 cpu5_top_alert0: trip-point0 {
6434 temperature = <90000>;
6435 hysteresis = <2000>;
6436 type = "passive";
6437 };
6438
6439 cpu5_top_alert1: trip-point1 {
6440 temperature = <95000>;
6441 hysteresis = <2000>;
6442 type = "passive";
6443 };
6444
6445 cpu5_top_crit: cpu-crit {
6446 temperature = <110000>;
6447 hysteresis = <1000>;
6448 type = "critical";
6449 };
6450 };
6451
6452 cooling-maps {
6453 map0 {
6454 trip = <&cpu5_top_alert0>;
6455 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6456 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6457 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6458 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6459 };
6460 map1 {
6461 trip = <&cpu5_top_alert1>;
6462 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6463 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6464 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6465 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6466 };
6467 };
6468 };
6469
6470 cpu6-top-thermal {
6471 polling-delay-passive = <250>;
6472 polling-delay = <1000>;
6473
6474 thermal-sensors = <&tsens0 9>;
6475
6476 trips {
6477 cpu6_top_alert0: trip-point0 {
6478 temperature = <90000>;
6479 hysteresis = <2000>;
6480 type = "passive";
6481 };
6482
6483 cpu6_top_alert1: trip-point1 {
6484 temperature = <95000>;
6485 hysteresis = <2000>;
6486 type = "passive";
6487 };
6488
6489 cpu6_top_crit: cpu-crit {
6490 temperature = <110000>;
6491 hysteresis = <1000>;
6492 type = "critical";
6493 };
6494 };
6495
6496 cooling-maps {
6497 map0 {
6498 trip = <&cpu6_top_alert0>;
6499 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6500 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6501 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6502 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6503 };
6504 map1 {
6505 trip = <&cpu6_top_alert1>;
6506 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6507 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6508 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6509 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6510 };
6511 };
6512 };
6513
6514 cpu7-top-thermal {
6515 polling-delay-passive = <250>;
6516 polling-delay = <1000>;
6517
6518 thermal-sensors = <&tsens0 10>;
6519
6520 trips {
6521 cpu7_top_alert0: trip-point0 {
6522 temperature = <90000>;
6523 hysteresis = <2000>;
6524 type = "passive";
6525 };
6526
6527 cpu7_top_alert1: trip-point1 {
6528 temperature = <95000>;
6529 hysteresis = <2000>;
6530 type = "passive";
6531 };
6532
6533 cpu7_top_crit: cpu-crit {
6534 temperature = <110000>;
6535 hysteresis = <1000>;
6536 type = "critical";
6537 };
6538 };
6539
6540 cooling-maps {
6541 map0 {
6542 trip = <&cpu7_top_alert0>;
6543 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6544 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6545 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6546 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6547 };
6548 map1 {
6549 trip = <&cpu7_top_alert1>;
6550 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6551 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6552 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6553 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6554 };
6555 };
6556 };
6557
6558 cpu4-bottom-thermal {
6559 polling-delay-passive = <250>;
6560 polling-delay = <1000>;
6561
6562 thermal-sensors = <&tsens0 11>;
6563
6564 trips {
6565 cpu4_bottom_alert0: trip-point0 {
6566 temperature = <90000>;
6567 hysteresis = <2000>;
6568 type = "passive";
6569 };
6570
6571 cpu4_bottom_alert1: trip-point1 {
6572 temperature = <95000>;
6573 hysteresis = <2000>;
6574 type = "passive";
6575 };
6576
6577 cpu4_bottom_crit: cpu-crit {
6578 temperature = <110000>;
6579 hysteresis = <1000>;
6580 type = "critical";
6581 };
6582 };
6583
6584 cooling-maps {
6585 map0 {
6586 trip = <&cpu4_bottom_alert0>;
6587 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6588 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6589 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6590 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6591 };
6592 map1 {
6593 trip = <&cpu4_bottom_alert1>;
6594 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6595 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6596 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6597 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6598 };
6599 };
6600 };
6601
6602 cpu5-bottom-thermal {
6603 polling-delay-passive = <250>;
6604 polling-delay = <1000>;
6605
6606 thermal-sensors = <&tsens0 12>;
6607
6608 trips {
6609 cpu5_bottom_alert0: trip-point0 {
6610 temperature = <90000>;
6611 hysteresis = <2000>;
6612 type = "passive";
6613 };
6614
6615 cpu5_bottom_alert1: trip-point1 {
6616 temperature = <95000>;
6617 hysteresis = <2000>;
6618 type = "passive";
6619 };
6620
6621 cpu5_bottom_crit: cpu-crit {
6622 temperature = <110000>;
6623 hysteresis = <1000>;
6624 type = "critical";
6625 };
6626 };
6627
6628 cooling-maps {
6629 map0 {
6630 trip = <&cpu5_bottom_alert0>;
6631 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6632 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6633 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6634 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6635 };
6636 map1 {
6637 trip = <&cpu5_bottom_alert1>;
6638 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6639 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6640 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6641 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6642 };
6643 };
6644 };
6645
6646 cpu6-bottom-thermal {
6647 polling-delay-passive = <250>;
6648 polling-delay = <1000>;
6649
6650 thermal-sensors = <&tsens0 13>;
6651
6652 trips {
6653 cpu6_bottom_alert0: trip-point0 {
6654 temperature = <90000>;
6655 hysteresis = <2000>;
6656 type = "passive";
6657 };
6658
6659 cpu6_bottom_alert1: trip-point1 {
6660 temperature = <95000>;
6661 hysteresis = <2000>;
6662 type = "passive";
6663 };
6664
6665 cpu6_bottom_crit: cpu-crit {
6666 temperature = <110000>;
6667 hysteresis = <1000>;
6668 type = "critical";
6669 };
6670 };
6671
6672 cooling-maps {
6673 map0 {
6674 trip = <&cpu6_bottom_alert0>;
6675 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6676 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6677 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6678 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6679 };
6680 map1 {
6681 trip = <&cpu6_bottom_alert1>;
6682 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6683 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6684 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6685 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6686 };
6687 };
6688 };
6689
6690 cpu7-bottom-thermal {
6691 polling-delay-passive = <250>;
6692 polling-delay = <1000>;
6693
6694 thermal-sensors = <&tsens0 14>;
6695
6696 trips {
6697 cpu7_bottom_alert0: trip-point0 {
6698 temperature = <90000>;
6699 hysteresis = <2000>;
6700 type = "passive";
6701 };
6702
6703 cpu7_bottom_alert1: trip-point1 {
6704 temperature = <95000>;
6705 hysteresis = <2000>;
6706 type = "passive";
6707 };
6708
6709 cpu7_bottom_crit: cpu-crit {
6710 temperature = <110000>;
6711 hysteresis = <1000>;
6712 type = "critical";
6713 };
6714 };
6715
6716 cooling-maps {
6717 map0 {
6718 trip = <&cpu7_bottom_alert0>;
6719 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6720 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6721 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6722 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6723 };
6724 map1 {
6725 trip = <&cpu7_bottom_alert1>;
6726 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6727 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6728 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6729 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6730 };
6731 };
6732 };
6733
6734 aoss0-thermal {
6735 polling-delay-passive = <250>;
6736 polling-delay = <1000>;
6737
6738 thermal-sensors = <&tsens0 0>;
6739
6740 trips {
6741 aoss0_alert0: trip-point0 {
6742 temperature = <90000>;
6743 hysteresis = <2000>;
6744 type = "hot";
6745 };
6746 };
6747 };
6748
6749 cluster0-thermal {
6750 polling-delay-passive = <250>;
6751 polling-delay = <1000>;
6752
6753 thermal-sensors = <&tsens0 5>;
6754
6755 trips {
6756 cluster0_alert0: trip-point0 {
6757 temperature = <90000>;
6758 hysteresis = <2000>;
6759 type = "hot";
6760 };
6761 cluster0_crit: cluster0_crit {
6762 temperature = <110000>;
6763 hysteresis = <2000>;
6764 type = "critical";
6765 };
6766 };
6767 };
6768
6769 cluster1-thermal {
6770 polling-delay-passive = <250>;
6771 polling-delay = <1000>;
6772
6773 thermal-sensors = <&tsens0 6>;
6774
6775 trips {
6776 cluster1_alert0: trip-point0 {
6777 temperature = <90000>;
6778 hysteresis = <2000>;
6779 type = "hot";
6780 };
6781 cluster1_crit: cluster1_crit {
6782 temperature = <110000>;
6783 hysteresis = <2000>;
6784 type = "critical";
6785 };
6786 };
6787 };
6788
6789 gpu-top-thermal {
6790 polling-delay-passive = <250>;
6791 polling-delay = <1000>;
6792
6793 thermal-sensors = <&tsens0 15>;
6794
6795 trips {
6796 gpu1_alert0: trip-point0 {
6797 temperature = <90000>;
6798 hysteresis = <2000>;
6799 type = "hot";
6800 };
6801 };
6802 };
6803
6804 aoss1-thermal {
6805 polling-delay-passive = <250>;
6806 polling-delay = <1000>;
6807
6808 thermal-sensors = <&tsens1 0>;
6809
6810 trips {
6811 aoss1_alert0: trip-point0 {
6812 temperature = <90000>;
6813 hysteresis = <2000>;
6814 type = "hot";
6815 };
6816 };
6817 };
6818
6819 wlan-thermal {
6820 polling-delay-passive = <250>;
6821 polling-delay = <1000>;
6822
6823 thermal-sensors = <&tsens1 1>;
6824
6825 trips {
6826 wlan_alert0: trip-point0 {
6827 temperature = <90000>;
6828 hysteresis = <2000>;
6829 type = "hot";
6830 };
6831 };
6832 };
6833
6834 video-thermal {
6835 polling-delay-passive = <250>;
6836 polling-delay = <1000>;
6837
6838 thermal-sensors = <&tsens1 2>;
6839
6840 trips {
6841 video_alert0: trip-point0 {
6842 temperature = <90000>;
6843 hysteresis = <2000>;
6844 type = "hot";
6845 };
6846 };
6847 };
6848
6849 mem-thermal {
6850 polling-delay-passive = <250>;
6851 polling-delay = <1000>;
6852
6853 thermal-sensors = <&tsens1 3>;
6854
6855 trips {
6856 mem_alert0: trip-point0 {
6857 temperature = <90000>;
6858 hysteresis = <2000>;
6859 type = "hot";
6860 };
6861 };
6862 };
6863
6864 q6-hvx-thermal {
6865 polling-delay-passive = <250>;
6866 polling-delay = <1000>;
6867
6868 thermal-sensors = <&tsens1 4>;
6869
6870 trips {
6871 q6_hvx_alert0: trip-point0 {
6872 temperature = <90000>;
6873 hysteresis = <2000>;
6874 type = "hot";
6875 };
6876 };
6877 };
6878
6879 camera-thermal {
6880 polling-delay-passive = <250>;
6881 polling-delay = <1000>;
6882
6883 thermal-sensors = <&tsens1 5>;
6884
6885 trips {
6886 camera_alert0: trip-point0 {
6887 temperature = <90000>;
6888 hysteresis = <2000>;
6889 type = "hot";
6890 };
6891 };
6892 };
6893
6894 compute-thermal {
6895 polling-delay-passive = <250>;
6896 polling-delay = <1000>;
6897
6898 thermal-sensors = <&tsens1 6>;
6899
6900 trips {
6901 compute_alert0: trip-point0 {
6902 temperature = <90000>;
6903 hysteresis = <2000>;
6904 type = "hot";
6905 };
6906 };
6907 };
6908
6909 npu-thermal {
6910 polling-delay-passive = <250>;
6911 polling-delay = <1000>;
6912
6913 thermal-sensors = <&tsens1 7>;
6914
6915 trips {
6916 npu_alert0: trip-point0 {
6917 temperature = <90000>;
6918 hysteresis = <2000>;
6919 type = "hot";
6920 };
6921 };
6922 };
6923
6924 gpu-bottom-thermal {
6925 polling-delay-passive = <250>;
6926 polling-delay = <1000>;
6927
6928 thermal-sensors = <&tsens1 8>;
6929
6930 trips {
6931 gpu2_alert0: trip-point0 {
6932 temperature = <90000>;
6933 hysteresis = <2000>;
6934 type = "hot";
6935 };
6936 };
6937 };
6938 };
6939};