Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / e84b8f6ce0e7daf4e9781172c4ffd74d7d525dbb / . / board / amcc / luan / init.S
blob: 9514fb8b8a6ea3036e743ebc9ec7752317c40121 [file] [log] [blame]
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100[diff] [blame]1/*
Stefan Roese00cdb4c2007-03-08 10:13:16 +0100[diff] [blame]2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]7 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese00cdb4c2007-03-08 10:13:16 +0100[diff] [blame]8 */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100[diff] [blame]9
10#include <ppc_asm.tmpl>
11#include <config.h>
Peter Tyser61f2b382010-04-12 22:28:07 -0500[diff] [blame]12#include <asm/mmu.h>
Stefan Roese550650d2010-09-20 16:05:31 +0200[diff] [blame]13#include <asm/ppc4xx.h>
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100[diff] [blame]14
15/**************************************************************************
16 * TLB TABLE
17 *
18 * This table is used by the cpu boot code to setup the initial tlb
19 * entries. Rather than make broad assumptions in the cpu source tree,
20 * this table lets each board set things up however they like.
21 *
22 * Pointer to the table is returned in r1
23 *
24 *************************************************************************/
25
Stefan Roese00cdb4c2007-03-08 10:13:16 +0100[diff] [blame]26 .section .bootpg,"ax"
27 .globl tlbtab
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100[diff] [blame]28
29tlbtab:
Stefan Roese00cdb4c2007-03-08 10:13:16 +0100[diff] [blame]30 tlbtab_start
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100[diff] [blame]31
Stefan Roese00cdb4c2007-03-08 10:13:16 +0100[diff] [blame]32 /*
33 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
34 * speed up boot process. It is patched after relocation to enable SA_I
35 */
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]36 tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_RWX | SA_G)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100[diff] [blame]37
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]38 tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_RWX | SA_IG)
39 tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_RWX | SA_IG)
40 tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_RWX | SA_IG)
41 tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_RWX | SA_IG)
42 tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_RW | SA_IG)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100[diff] [blame]43
Stefan Roese00cdb4c2007-03-08 10:13:16 +0100[diff] [blame]44 /*
45 * TLB entries for SDRAM are not needed on this platform.
46 * They are dynamically generated in the SPD DDR(2) detection
47 * routine.
48 */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100[diff] [blame]49
Stefan Roese00cdb4c2007-03-08 10:13:16 +0100[diff] [blame]50 /* internal ram (l2 cache) */
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]51 tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_I)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100[diff] [blame]52
Stefan Roese00cdb4c2007-03-08 10:13:16 +0100[diff] [blame]53 /* peripherals at f0000000 */
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]54 tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_RW | SA_IG)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100[diff] [blame]55
Stefan Roese00cdb4c2007-03-08 10:13:16 +0100[diff] [blame]56 /* PCI */
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]57 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_RW | SA_IG)
58 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_RW | SA_IG)
Stefan Roese00cdb4c2007-03-08 10:13:16 +0100[diff] [blame]59 tlbtab_end