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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 6e7fb6eaa515e15c2b86451d7853c2611713e872 / . / board / amcc / luan / init.S
blob: 7830ebdfa6db365ddeaf19c2fc19e2bbbd6a270c [file] [log] [blame]
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100[diff] [blame^]1/*
2*
3* See file CREDITS for list of people who contributed to this
4* project.
5*
6* This program is free software; you can redistribute it and/or
7* modify it under the terms of the GNU General Public License as
8* published by the Free Software Foundation; either version 2 of
9* the License, or (at your option) any later version.
10*
11* This program is distributed in the hope that it will be useful,
12* but WITHOUT ANY WARRANTY; without even the implied warranty of
13* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14* GNU General Public License for more details.
15*
16* You should have received a copy of the GNU General Public License
17* along with this program; if not, write to the Free Software
18* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19* MA 02111-1307 USA
20*/
21
22#include <ppc_asm.tmpl>
23#include <config.h>
24
25/* General */
26#define TLB_VALID 0x00000200
27
28/* Supported page sizes */
29
30#define SZ_1K 0x00000000
31#define SZ_4K 0x00000010
32#define SZ_16K 0x00000020
33#define SZ_64K 0x00000030
34#define SZ_256K 0x00000040
35#define SZ_1M 0x00000050
36#define SZ_16M 0x00000070
37#define SZ_256M 0x00000090
38
39/* Storage attributes */
40#define SA_W 0x00000800 /* Write-through */
41#define SA_I 0x00000400 /* Caching inhibited */
42#define SA_M 0x00000200 /* Memory coherence */
43#define SA_G 0x00000100 /* Guarded */
44#define SA_E 0x00000080 /* Endian */
45
46/* Access control */
47#define AC_X 0x00000024 /* Execute */
48#define AC_W 0x00000012 /* Write */
49#define AC_R 0x00000009 /* Read */
50
51/* Some handy macros */
52
53#define EPN(e) ((e) & 0xfffffc00)
54#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
55#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
56#define TLB2(a) ( (a)&0x00000fbf )
57
58#define tlbtab_start\
59 mflr r1 ;\
60 bl 0f ;
61
62#define tlbtab_end\
63 .long 0, 0, 0 ; \
640: mflr r0 ; \
65 mtlr r1 ; \
66 blr ;
67
68#define tlbentry(epn,sz,rpn,erpn,attr)\
69 .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
70
71
72/**************************************************************************
73 * TLB TABLE
74 *
75 * This table is used by the cpu boot code to setup the initial tlb
76 * entries. Rather than make broad assumptions in the cpu source tree,
77 * this table lets each board set things up however they like.
78 *
79 * Pointer to the table is returned in r1
80 *
81 *************************************************************************/
82
83 .section .bootpg,"ax"
84 .globl tlbtab
85
86tlbtab:
87 tlbtab_start
88
89#if (CFG_LARGE_FLASH == 0xffc00000) /* if booting from large flash */
90 /* large flash */
91 tlbentry( 0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
92 tlbentry( 0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
93 tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
94 tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
95
96 tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
97 tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
98#else /* else booting from small flash */
99 tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
100 tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
101
102 tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
103 tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
104 tlbentry( 0xffa00000, SZ_1M, 0xffa00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
105 tlbentry( 0xffb00000, SZ_1M, 0xffb00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
106#endif
107
108 tlbentry( CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I )
109
110#if (CFG_SRAM_BASE != 0) /* if SRAM up high and SDRAM at zero */
111 tlbentry( 0x00000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
112 tlbentry( 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
113#elif (CFG_SMALL_FLASH == 0xff900000) /* else SRAM at 0 */
114 tlbentry( 0x00000000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
115#elif (CFG_SMALL_FLASH == 0xfff00000)
116 tlbentry( 0x00000000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
117#else
118 #error DONT KNOW SRAM LOCATION
119#endif
120
121 /* internal ram (l2 cache) */
122 tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I )
123
124 /* peripherals at f0000000 */
125 tlbentry( CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I )
126
127 /* PCI */
128#if (CONFIG_COMMANDS & CFG_CMD_PCI)
129 tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I )
130 tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I )
131#endif
132 tlbtab_end