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wdenk12f34242003-09-02 22:48:03 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
4 *
wdenkfbe4b5c2003-10-06 21:55:32 +00005 * (C) Copyright 2003
6 * DAVE Srl
wdenk12f34242003-09-02 22:48:03 +00007 *
wdenkfbe4b5c2003-10-06 21:55:32 +00008 * http://www.dave-tech.it
9 * http://www.wawnet.biz
10 * mailto:info@wawnet.biz
11 *
12 * Credits: Stefan Roese, Wolfgang Denk
wdenk12f34242003-09-02 22:48:03 +000013 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020014 * SPDX-License-Identifier: GPL-2.0+
wdenk12f34242003-09-02 22:48:03 +000015 */
16
17/*
18 * board/config.h - configuration options, board specific
19 */
20
21#ifndef __CONFIG_H
22#define __CONFIG_H
23
wdenk42d1f032003-10-15 23:53:47 +000024#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
wdenkfbe4b5c2003-10-06 21:55:32 +000025#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
26#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
wdenkc837dcb2004-01-20 23:12:12 +000027#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
28#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
wdenkfbe4b5c2003-10-06 21:55:32 +000029#endif
30
wdenke55ca7e2004-07-01 21:40:08 +000031
32/* Only one of the following two symbols must be defined (default is 25 MHz)
33 * CONFIG_PPCHAMELEON_CLK_25
34 * CONFIG_PPCHAMELEON_CLK_33
35 */
wdenk281e00a2004-08-01 22:48:16 +000036#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
Wolfgang Denk0f18cb62005-07-31 00:30:09 +020037#define CONFIG_PPCHAMELEON_CLK_25
wdenk281e00a2004-08-01 22:48:16 +000038#endif
wdenke55ca7e2004-07-01 21:40:08 +000039
40#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
41#error "* Two external frequencies (SysClk) are defined! *"
42#endif
43
44#undef CONFIG_PPCHAMELEON_SMI712
45
wdenk12f34242003-09-02 22:48:03 +000046/*
47 * Debug stuff
48 */
wdenkc837dcb2004-01-20 23:12:12 +000049#undef __DEBUG_START_FROM_SRAM__
wdenk12f34242003-09-02 22:48:03 +000050#define __DISABLE_MACHINE_EXCEPTION__
51
52#ifdef __DEBUG_START_FROM_SRAM__
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4
wdenk12f34242003-09-02 22:48:03 +000054#endif
55
56/*
57 * High Level Configuration Options
58 * (easy to change)
59 */
60
61#define CONFIG_405EP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000062#define CONFIG_4xx 1 /* ...member of PPC4xx family */
63#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
wdenk12f34242003-09-02 22:48:03 +000064
Wolfgang Denk2ae18242010-10-06 09:05:45 +020065#define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */
Wolfgang Denkaa72d8b2010-11-21 17:04:17 +010066#define CONFIG_SYS_LDSCRIPT "board/dave/PPChameleonEVB/u-boot.lds"
Wolfgang Denk2ae18242010-10-06 09:05:45 +020067
wdenkc837dcb2004-01-20 23:12:12 +000068#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
69#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
wdenk12f34242003-09-02 22:48:03 +000070
wdenke55ca7e2004-07-01 21:40:08 +000071
72#ifdef CONFIG_PPCHAMELEON_CLK_25
wdenk281e00a2004-08-01 22:48:16 +000073# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
wdenke55ca7e2004-07-01 21:40:08 +000074#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
wdenk281e00a2004-08-01 22:48:16 +000075# define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
wdenke55ca7e2004-07-01 21:40:08 +000076#else
wdenk281e00a2004-08-01 22:48:16 +000077# error "* External frequency (SysClk) not defined! *"
wdenke55ca7e2004-07-01 21:40:08 +000078#endif
wdenk12f34242003-09-02 22:48:03 +000079
wdenk12f34242003-09-02 22:48:03 +000080#define CONFIG_BAUDRATE 115200
wdenk4d816772003-09-03 14:03:26 +000081#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenk12f34242003-09-02 22:48:03 +000082
wdenk12f34242003-09-02 22:48:03 +000083#undef CONFIG_BOOTARGS
wdenk12f34242003-09-02 22:48:03 +000084
wdenk200f8c72003-09-13 19:13:29 +000085/* Ethernet stuff */
86#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
87#define CONFIG_ETHADDR 00:50:c2:1e:af:fe
wdenke2ffd592004-12-31 09:32:47 +000088#define CONFIG_HAS_ETH1
wdenkc837dcb2004-01-20 23:12:12 +000089#define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
wdenk12f34242003-09-02 22:48:03 +000090
91#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk12f34242003-09-02 22:48:03 +000093
wdenk12f34242003-09-02 22:48:03 +000094#undef CONFIG_EXT_PHY
wdenk4d816772003-09-03 14:03:26 +000095
Ben Warren96e21f82008-10-27 23:50:15 -070096#define CONFIG_PPC4xx_EMAC
wdenk12f34242003-09-02 22:48:03 +000097#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000098#ifndef CONFIG_EXT_PHY
stroesebf418862005-06-30 13:06:07 +000099#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
100#define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */
wdenk12f34242003-09-02 22:48:03 +0000101#else
wdenkc837dcb2004-01-20 23:12:12 +0000102#define CONFIG_PHY_ADDR 2 /* PHY address */
wdenk12f34242003-09-02 22:48:03 +0000103#endif
wdenkc837dcb2004-01-20 23:12:12 +0000104#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
wdenk12f34242003-09-02 22:48:03 +0000105
Jon Loeligeracf02692007-07-08 14:49:44 -0500106
107/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500108 * BOOTP options
109 */
110#define CONFIG_BOOTP_BOOTFILESIZE
111#define CONFIG_BOOTP_BOOTPATH
112#define CONFIG_BOOTP_GATEWAY
113#define CONFIG_BOOTP_HOSTNAME
114
115
116/*
Jon Loeligeracf02692007-07-08 14:49:44 -0500117 * Command line configuration.
118 */
119#include <config_cmd_default.h>
120
121#define CONFIG_CMD_DATE
122#define CONFIG_CMD_DHCP
123#define CONFIG_CMD_ELF
124#define CONFIG_CMD_EEPROM
125#define CONFIG_CMD_I2C
126#define CONFIG_CMD_IRQ
127#define CONFIG_CMD_JFFS2
128#define CONFIG_CMD_MII
129#define CONFIG_CMD_NAND
130#define CONFIG_CMD_NFS
131#define CONFIG_CMD_PCI
132#define CONFIG_CMD_SNTP
133
wdenk12f34242003-09-02 22:48:03 +0000134
135#define CONFIG_MAC_PARTITION
136#define CONFIG_DOS_PARTITION
137
wdenkc837dcb2004-01-20 23:12:12 +0000138#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk12f34242003-09-02 22:48:03 +0000139
wdenke6325152005-03-17 16:43:10 +0000140#define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_I2C_RTC_ADDR 0x68
142#define CONFIG_SYS_M41T11_BASE_YEAR 1900
wdenk12f34242003-09-02 22:48:03 +0000143
Stefan Roese62534be2006-03-17 10:28:24 +0100144/*
145 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
146 */
wdenkc837dcb2004-01-20 23:12:12 +0000147#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
wdenk12f34242003-09-02 22:48:03 +0000148
Stefan Roese62534be2006-03-17 10:28:24 +0100149/* SDRAM timings used in datasheet */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_SDRAM_CL 2
151#define CONFIG_SYS_SDRAM_tRP 20
152#define CONFIG_SYS_SDRAM_tRC 65
153#define CONFIG_SYS_SDRAM_tRCD 20
154#undef CONFIG_SYS_SDRAM_tRFC
Stefan Roese62534be2006-03-17 10:28:24 +0100155
wdenk12f34242003-09-02 22:48:03 +0000156/*
157 * Miscellaneous configurable options
158 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_LONGHELP /* undef to save memory */
160#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk12f34242003-09-02 22:48:03 +0000161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
wdenk12f34242003-09-02 22:48:03 +0000163
Jon Loeligeracf02692007-07-08 14:49:44 -0500164#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk12f34242003-09-02 22:48:03 +0000166#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk12f34242003-09-02 22:48:03 +0000168#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
170#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
171#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk12f34242003-09-02 22:48:03 +0000172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
wdenk12f34242003-09-02 22:48:03 +0000174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenk12f34242003-09-02 22:48:03 +0000176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
178#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk12f34242003-09-02 22:48:03 +0000179
Stefan Roese550650d2010-09-20 16:05:31 +0200180#define CONFIG_CONS_INDEX 1 /* Use UART0 */
181#define CONFIG_SYS_NS16550
182#define CONFIG_SYS_NS16550_SERIAL
183#define CONFIG_SYS_NS16550_REG_SIZE 1
184#define CONFIG_SYS_NS16550_CLK get_serial_clock()
185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_BASE_BAUD 691200
wdenk12f34242003-09-02 22:48:03 +0000188
189/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk42d1f032003-10-15 23:53:47 +0000191 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
192 57600, 115200, 230400, 460800, 921600 }
wdenk12f34242003-09-02 22:48:03 +0000193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
195#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenk12f34242003-09-02 22:48:03 +0000196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk12f34242003-09-02 22:48:03 +0000198
199#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
200
201/*-----------------------------------------------------------------------
202 * NAND-FLASH stuff
203 *-----------------------------------------------------------------------
204 */
Wolfgang Denk170c1972009-07-18 15:32:10 +0200205
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100206/*
207 * nand device 1 on dave (PPChameleonEVB) needs more time,
208 * so we just introduce additional wait in nand_wait(),
209 * effectively for both devices.
210 */
211#define PPCHAMELON_NAND_TIMER_HACK
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_NAND0_BASE 0xFF400000
214#define CONFIG_SYS_NAND1_BASE 0xFF000000
215#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, CONFIG_SYS_NAND1_BASE }
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100216#define NAND_BIG_DELAY_US 25
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
wdenk12f34242003-09-02 22:48:03 +0000218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
220#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
221#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
222#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
wdenk12f34242003-09-02 22:48:03 +0000223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
225#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
226#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
227#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
wdenk12f34242003-09-02 22:48:03 +0000228
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100229#define MACRO_NAND_DISABLE_CE(nandptr) do \
230{ \
231 switch((unsigned long)nandptr) \
232 { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233 case CONFIG_SYS_NAND0_BASE: \
234 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100235 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236 case CONFIG_SYS_NAND1_BASE: \
237 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100238 break; \
239 } \
240} while(0)
241
242#define MACRO_NAND_ENABLE_CE(nandptr) do \
243{ \
244 switch((unsigned long)nandptr) \
245 { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246 case CONFIG_SYS_NAND0_BASE: \
247 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100248 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249 case CONFIG_SYS_NAND1_BASE: \
250 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100251 break; \
252 } \
253} while(0)
254
255#define MACRO_NAND_CTL_CLRALE(nandptr) do \
256{ \
257 switch((unsigned long)nandptr) \
258 { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259 case CONFIG_SYS_NAND0_BASE: \
260 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100261 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262 case CONFIG_SYS_NAND1_BASE: \
263 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100264 break; \
265 } \
266} while(0)
267
268#define MACRO_NAND_CTL_SETALE(nandptr) do \
269{ \
270 switch((unsigned long)nandptr) \
271 { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272 case CONFIG_SYS_NAND0_BASE: \
273 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100274 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275 case CONFIG_SYS_NAND1_BASE: \
276 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100277 break; \
278 } \
279} while(0)
280
281#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
282{ \
283 switch((unsigned long)nandptr) \
284 { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285 case CONFIG_SYS_NAND0_BASE: \
286 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100287 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288 case CONFIG_SYS_NAND1_BASE: \
289 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100290 break; \
291 } \
292} while(0)
293
294#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
295 switch((unsigned long)nandptr) { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296 case CONFIG_SYS_NAND0_BASE: \
297 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100298 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299 case CONFIG_SYS_NAND1_BASE: \
300 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100301 break; \
302 } \
303} while(0)
wdenk12f34242003-09-02 22:48:03 +0000304
wdenk12f34242003-09-02 22:48:03 +0000305/*-----------------------------------------------------------------------
306 * PCI stuff
307 *-----------------------------------------------------------------------
308 */
wdenkc837dcb2004-01-20 23:12:12 +0000309#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
310#define PCI_HOST_FORCE 1 /* configure as pci host */
311#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenk12f34242003-09-02 22:48:03 +0000312
wdenkc837dcb2004-01-20 23:12:12 +0000313#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000314#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenkc837dcb2004-01-20 23:12:12 +0000315#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
316#undef CONFIG_PCI_PNP /* do pci plug-and-play */
317 /* resource configuration */
wdenk12f34242003-09-02 22:48:03 +0000318
wdenkc837dcb2004-01-20 23:12:12 +0000319#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
wdenk12f34242003-09-02 22:48:03 +0000320
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
322#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */
323#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
wdenke55ca7e2004-07-01 21:40:08 +0000324
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
326#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
327#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
328#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
329#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
330#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenk12f34242003-09-02 22:48:03 +0000331
332/*-----------------------------------------------------------------------
333 * Start addresses for the final memory configuration
334 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk12f34242003-09-02 22:48:03 +0000336 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_SDRAM_BASE 0x00000000
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200338
339/* Reserve 256 kB for Monitor */
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100340/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
342#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
343#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
Bartlomiej Sieka038ccac2006-02-24 09:37:22 +0100344*/
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200345
346/* Reserve 320 kB for Monitor */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_FLASH_BASE 0xFFFB0000
348#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
349#define CONFIG_SYS_MONITOR_LEN (320 * 1024)
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200350
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
wdenk12f34242003-09-02 22:48:03 +0000352
353/*
354 * For booting Linux, the board info and command line data
355 * have to be in the first 8 MB of memory, since this is
356 * the maximum mapped by the Linux kernel during initialization.
357 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk12f34242003-09-02 22:48:03 +0000359/*-----------------------------------------------------------------------
360 * FLASH organization
361 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
363#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenk12f34242003-09-02 22:48:03 +0000364
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
366#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
wdenk12f34242003-09-02 22:48:03 +0000367
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
369#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
370#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenk12f34242003-09-02 22:48:03 +0000371/*
372 * The following defines are added for buggy IOP480 byte interface.
373 * All other boards should use the standard values (CPCI405 etc.)
374 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
376#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
377#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
wdenk12f34242003-09-02 22:48:03 +0000378
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenk12f34242003-09-02 22:48:03 +0000380
wdenk12f34242003-09-02 22:48:03 +0000381/*-----------------------------------------------------------------------
382 * Environment Variable setup
383 */
wdenke55ca7e2004-07-01 21:40:08 +0000384#ifdef ENVIRONMENT_IN_EEPROM
385
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200386#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200387#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
388#define CONFIG_ENV_SIZE 0x700 /* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/
wdenke55ca7e2004-07-01 21:40:08 +0000389
390#else /* DEFAULT: environment in flash, using redundand flash sectors */
391
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200392#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200393#define CONFIG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
394#define CONFIG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
395#define CONFIG_ENV_ADDR_REDUND 0xFFFFA000
396#define CONFIG_ENV_SIZE_REDUND 0x2000
wdenk12f34242003-09-02 22:48:03 +0000397
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200399
wdenke55ca7e2004-07-01 21:40:08 +0000400#endif /* ENVIRONMENT_IN_EEPROM */
401
402
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
404#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
wdenk12f34242003-09-02 22:48:03 +0000405
406/*-----------------------------------------------------------------------
407 * I2C EEPROM (CAT24WC16) for environment
408 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000409#define CONFIG_SYS_I2C
410#define CONFIG_SYS_I2C_PPC4XX
411#define CONFIG_SYS_I2C_PPC4XX_CH0
412#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
413#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
wdenk12f34242003-09-02 22:48:03 +0000414
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
416#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
wdenkc837dcb2004-01-20 23:12:12 +0000417/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
419#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
wdenk12f34242003-09-02 22:48:03 +0000420 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000421 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenk12f34242003-09-02 22:48:03 +0000423
wdenk12f34242003-09-02 22:48:03 +0000424/*
425 * Init Memory Controller:
426 *
427 * BR0/1 and OR0/1 (FLASH)
428 */
429
430#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
431
432/*-----------------------------------------------------------------------
433 * External Bus Controller (EBC) Setup
434 */
435
wdenkc837dcb2004-01-20 23:12:12 +0000436/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437#define CONFIG_SYS_EBC_PB0AP 0x92015480
438#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenk12f34242003-09-02 22:48:03 +0000439
wdenkc837dcb2004-01-20 23:12:12 +0000440/* Memory Bank 1 (External SRAM) initialization */
wdenk12f34242003-09-02 22:48:03 +0000441/* Since this must replace NOR Flash, we use the same settings for CS0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#define CONFIG_SYS_EBC_PB1AP 0x92015480
443#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
wdenk12f34242003-09-02 22:48:03 +0000444
wdenkc837dcb2004-01-20 23:12:12 +0000445/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200446#define CONFIG_SYS_EBC_PB2AP 0x92015480
447#define CONFIG_SYS_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
wdenk12f34242003-09-02 22:48:03 +0000448
wdenkc837dcb2004-01-20 23:12:12 +0000449/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450#define CONFIG_SYS_EBC_PB3AP 0x92015480
451#define CONFIG_SYS_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
wdenk12f34242003-09-02 22:48:03 +0000452
wdenke55ca7e2004-07-01 21:40:08 +0000453#ifdef CONFIG_PPCHAMELEON_SMI712
454/*
455 * Video console (graphic: SMI LynxEM)
456 */
457#define CONFIG_VIDEO
458#define CONFIG_CFB_CONSOLE
459#define CONFIG_VIDEO_SMI_LYNXEM
460#define CONFIG_VIDEO_LOGO
461/*#define CONFIG_VIDEO_BMP_LOGO*/
462#define CONFIG_CONSOLE_EXTRA_INFO
463#define CONFIG_VGA_AS_SINGLE_DEVICE
464/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465#define CONFIG_SYS_ISA_IO 0xE8000000
Marcel Ziswiler7817cb22007-12-30 03:30:46 +0100466/* see also drivers/video/videomodes.c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
wdenk12f34242003-09-02 22:48:03 +0000468#endif
469
470/*-----------------------------------------------------------------------
471 * FPGA stuff
472 */
473/* FPGA internal regs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474#define CONFIG_SYS_FPGA_MODE 0x00
475#define CONFIG_SYS_FPGA_STATUS 0x02
476#define CONFIG_SYS_FPGA_TS 0x04
477#define CONFIG_SYS_FPGA_TS_LOW 0x06
478#define CONFIG_SYS_FPGA_TS_CAP0 0x10
479#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
480#define CONFIG_SYS_FPGA_TS_CAP1 0x14
481#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
482#define CONFIG_SYS_FPGA_TS_CAP2 0x18
483#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
484#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
485#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
wdenk12f34242003-09-02 22:48:03 +0000486
487/* FPGA Mode Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200488#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
489#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
490#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
491#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
wdenk12f34242003-09-02 22:48:03 +0000492
493/* FPGA Status Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200494#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
495#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
496#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
497#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
498#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
wdenk12f34242003-09-02 22:48:03 +0000499
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200500#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
501#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
wdenk12f34242003-09-02 22:48:03 +0000502
503/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200504#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
505#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
506#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
507#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
508#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
wdenk12f34242003-09-02 22:48:03 +0000509
510/*-----------------------------------------------------------------------
511 * Definitions for initial stack pointer and data area (in data cache)
512 */
wdenk12f34242003-09-02 22:48:03 +0000513/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200514#define CONFIG_SYS_TEMP_STACK_OCM 1
wdenk12f34242003-09-02 22:48:03 +0000515
516/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200517#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
518#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
519#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200520#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
wdenk12f34242003-09-02 22:48:03 +0000521
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200522#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200523#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk12f34242003-09-02 22:48:03 +0000524
525/*-----------------------------------------------------------------------
526 * Definitions for GPIO setup (PPC405EP specific)
527 *
wdenkc837dcb2004-01-20 23:12:12 +0000528 * GPIO0[0] - External Bus Controller BLAST output
529 * GPIO0[1-9] - Instruction trace outputs -> GPIO
wdenk12f34242003-09-02 22:48:03 +0000530 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
531 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
532 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
533 * GPIO0[24-27] - UART0 control signal inputs/outputs
534 * GPIO0[28-29] - UART1 data signal input/output
wdenkc837dcb2004-01-20 23:12:12 +0000535 * GPIO0[30] - EMAC0 input
536 * GPIO0[31] - EMAC1 reject packet as output
wdenk12f34242003-09-02 22:48:03 +0000537 */
Stefan Roeseafabb492010-09-12 06:21:37 +0200538#define CONFIG_SYS_GPIO0_OSRL 0x40000550
539#define CONFIG_SYS_GPIO0_OSRH 0x00000110
540#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
541/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/
542#define CONFIG_SYS_GPIO0_ISR1H 0x15555444
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200543#define CONFIG_SYS_GPIO0_TSRL 0x00000000
Stefan Roeseafabb492010-09-12 06:21:37 +0200544#define CONFIG_SYS_GPIO0_TSRH 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200545#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
wdenk12f34242003-09-02 22:48:03 +0000546
wdenk12f34242003-09-02 22:48:03 +0000547#define CONFIG_NO_SERIAL_EEPROM
wdenk1d6f9722004-09-09 17:44:35 +0000548
wdenk200f8c72003-09-13 19:13:29 +0000549/*--------------------------------------------------------------------*/
wdenk1d6f9722004-09-09 17:44:35 +0000550
wdenk12f34242003-09-02 22:48:03 +0000551#ifdef CONFIG_NO_SERIAL_EEPROM
552
wdenk12f34242003-09-02 22:48:03 +0000553/*
wdenk200f8c72003-09-13 19:13:29 +0000554!-----------------------------------------------------------------------
wdenk12f34242003-09-02 22:48:03 +0000555! Defines for entry options.
556! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
wdenkc837dcb2004-01-20 23:12:12 +0000557! are plugged in the board will be utilized as non-ECC DIMMs.
wdenk200f8c72003-09-13 19:13:29 +0000558!-----------------------------------------------------------------------
wdenk12f34242003-09-02 22:48:03 +0000559*/
wdenk10767cc2004-05-13 13:23:58 +0000560#undef AUTO_MEMORY_CONFIG
561#define DIMM_READ_ADDR 0xAB
562#define DIMM_WRITE_ADDR 0xAA
wdenk12f34242003-09-02 22:48:03 +0000563
wdenk12f34242003-09-02 22:48:03 +0000564/* Defines for CPC0_PLLMR1 Register fields */
wdenk10767cc2004-05-13 13:23:58 +0000565#define PLL_ACTIVE 0x80000000
566#define CPC0_PLLMR1_SSCS 0x80000000
567#define PLL_RESET 0x40000000
568#define CPC0_PLLMR1_PLLR 0x40000000
wdenk12f34242003-09-02 22:48:03 +0000569 /* Feedback multiplier */
wdenk10767cc2004-05-13 13:23:58 +0000570#define PLL_FBKDIV 0x00F00000
571#define CPC0_PLLMR1_FBDV 0x00F00000
572#define PLL_FBKDIV_16 0x00000000
573#define PLL_FBKDIV_1 0x00100000
574#define PLL_FBKDIV_2 0x00200000
575#define PLL_FBKDIV_3 0x00300000
576#define PLL_FBKDIV_4 0x00400000
577#define PLL_FBKDIV_5 0x00500000
578#define PLL_FBKDIV_6 0x00600000
579#define PLL_FBKDIV_7 0x00700000
580#define PLL_FBKDIV_8 0x00800000
581#define PLL_FBKDIV_9 0x00900000
582#define PLL_FBKDIV_10 0x00A00000
583#define PLL_FBKDIV_11 0x00B00000
584#define PLL_FBKDIV_12 0x00C00000
585#define PLL_FBKDIV_13 0x00D00000
586#define PLL_FBKDIV_14 0x00E00000
587#define PLL_FBKDIV_15 0x00F00000
wdenk12f34242003-09-02 22:48:03 +0000588 /* Forward A divisor */
wdenk10767cc2004-05-13 13:23:58 +0000589#define PLL_FWDDIVA 0x00070000
590#define CPC0_PLLMR1_FWDVA 0x00070000
591#define PLL_FWDDIVA_8 0x00000000
592#define PLL_FWDDIVA_7 0x00010000
593#define PLL_FWDDIVA_6 0x00020000
594#define PLL_FWDDIVA_5 0x00030000
595#define PLL_FWDDIVA_4 0x00040000
596#define PLL_FWDDIVA_3 0x00050000
597#define PLL_FWDDIVA_2 0x00060000
598#define PLL_FWDDIVA_1 0x00070000
wdenk12f34242003-09-02 22:48:03 +0000599 /* Forward B divisor */
wdenk10767cc2004-05-13 13:23:58 +0000600#define PLL_FWDDIVB 0x00007000
601#define CPC0_PLLMR1_FWDVB 0x00007000
602#define PLL_FWDDIVB_8 0x00000000
603#define PLL_FWDDIVB_7 0x00001000
604#define PLL_FWDDIVB_6 0x00002000
605#define PLL_FWDDIVB_5 0x00003000
606#define PLL_FWDDIVB_4 0x00004000
607#define PLL_FWDDIVB_3 0x00005000
608#define PLL_FWDDIVB_2 0x00006000
609#define PLL_FWDDIVB_1 0x00007000
wdenk12f34242003-09-02 22:48:03 +0000610 /* PLL tune bits */
wdenk10767cc2004-05-13 13:23:58 +0000611#define PLL_TUNE_MASK 0x000003FF
612#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
613#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
614#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
615#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
616#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
617#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
618#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
wdenk12f34242003-09-02 22:48:03 +0000619
620/* Defines for CPC0_PLLMR0 Register fields */
621 /* CPU divisor */
wdenk10767cc2004-05-13 13:23:58 +0000622#define PLL_CPUDIV 0x00300000
623#define CPC0_PLLMR0_CCDV 0x00300000
624#define PLL_CPUDIV_1 0x00000000
625#define PLL_CPUDIV_2 0x00100000
626#define PLL_CPUDIV_3 0x00200000
627#define PLL_CPUDIV_4 0x00300000
wdenk12f34242003-09-02 22:48:03 +0000628 /* PLB divisor */
wdenk10767cc2004-05-13 13:23:58 +0000629#define PLL_PLBDIV 0x00030000
630#define CPC0_PLLMR0_CBDV 0x00030000
631#define PLL_PLBDIV_1 0x00000000
632#define PLL_PLBDIV_2 0x00010000
633#define PLL_PLBDIV_3 0x00020000
634#define PLL_PLBDIV_4 0x00030000
wdenk12f34242003-09-02 22:48:03 +0000635 /* OPB divisor */
wdenk10767cc2004-05-13 13:23:58 +0000636#define PLL_OPBDIV 0x00003000
637#define CPC0_PLLMR0_OPDV 0x00003000
638#define PLL_OPBDIV_1 0x00000000
639#define PLL_OPBDIV_2 0x00001000
640#define PLL_OPBDIV_3 0x00002000
641#define PLL_OPBDIV_4 0x00003000
wdenk12f34242003-09-02 22:48:03 +0000642 /* EBC divisor */
wdenk10767cc2004-05-13 13:23:58 +0000643#define PLL_EXTBUSDIV 0x00000300
644#define CPC0_PLLMR0_EPDV 0x00000300
645#define PLL_EXTBUSDIV_2 0x00000000
646#define PLL_EXTBUSDIV_3 0x00000100
647#define PLL_EXTBUSDIV_4 0x00000200
648#define PLL_EXTBUSDIV_5 0x00000300
wdenk12f34242003-09-02 22:48:03 +0000649 /* MAL divisor */
wdenk10767cc2004-05-13 13:23:58 +0000650#define PLL_MALDIV 0x00000030
651#define CPC0_PLLMR0_MPDV 0x00000030
652#define PLL_MALDIV_1 0x00000000
653#define PLL_MALDIV_2 0x00000010
654#define PLL_MALDIV_3 0x00000020
655#define PLL_MALDIV_4 0x00000030
wdenk12f34242003-09-02 22:48:03 +0000656 /* PCI divisor */
wdenk10767cc2004-05-13 13:23:58 +0000657#define PLL_PCIDIV 0x00000003
658#define CPC0_PLLMR0_PPFD 0x00000003
659#define PLL_PCIDIV_1 0x00000000
660#define PLL_PCIDIV_2 0x00000001
661#define PLL_PCIDIV_3 0x00000002
662#define PLL_PCIDIV_4 0x00000003
wdenk12f34242003-09-02 22:48:03 +0000663
wdenke55ca7e2004-07-01 21:40:08 +0000664#ifdef CONFIG_PPCHAMELEON_CLK_25
665/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
666#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
667 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
668 PLL_MALDIV_1 | PLL_PCIDIV_4)
669#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
670 PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
671 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
672
673#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
674 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
675 PLL_MALDIV_1 | PLL_PCIDIV_4)
676#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
677 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
678 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
679
680#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
681 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
682 PLL_MALDIV_1 | PLL_PCIDIV_4)
683#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
684 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
685 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
686
687#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
688 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
689 PLL_MALDIV_1 | PLL_PCIDIV_2)
690#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
691 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
692 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
693
694#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
695
wdenk180d3f72004-01-04 16:28:35 +0000696/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
wdenke55ca7e2004-07-01 21:40:08 +0000697#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
wdenk10767cc2004-05-13 13:23:58 +0000698 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
699 PLL_MALDIV_1 | PLL_PCIDIV_4)
wdenke55ca7e2004-07-01 21:40:08 +0000700#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
wdenk10767cc2004-05-13 13:23:58 +0000701 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
702 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
wdenke55ca7e2004-07-01 21:40:08 +0000703
704#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
wdenk10767cc2004-05-13 13:23:58 +0000705 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
706 PLL_MALDIV_1 | PLL_PCIDIV_4)
wdenke55ca7e2004-07-01 21:40:08 +0000707#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
wdenk10767cc2004-05-13 13:23:58 +0000708 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
709 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
wdenke55ca7e2004-07-01 21:40:08 +0000710
711#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
wdenk10767cc2004-05-13 13:23:58 +0000712 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
713 PLL_MALDIV_1 | PLL_PCIDIV_4)
wdenke55ca7e2004-07-01 21:40:08 +0000714#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
wdenk10767cc2004-05-13 13:23:58 +0000715 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
716 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
wdenke55ca7e2004-07-01 21:40:08 +0000717
718#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
wdenk10767cc2004-05-13 13:23:58 +0000719 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
720 PLL_MALDIV_1 | PLL_PCIDIV_2)
wdenke55ca7e2004-07-01 21:40:08 +0000721#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
wdenk10767cc2004-05-13 13:23:58 +0000722 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
723 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
wdenk180d3f72004-01-04 16:28:35 +0000724
wdenke55ca7e2004-07-01 21:40:08 +0000725#else
726#error "* External frequency (SysClk) not defined! *"
727#endif
728
wdenk180d3f72004-01-04 16:28:35 +0000729#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
730/* Model HI */
wdenk1d6f9722004-09-09 17:44:35 +0000731#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
732#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200733#define CONFIG_SYS_OPB_FREQ 55555555
wdenk180d3f72004-01-04 16:28:35 +0000734/* Model ME */
735#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
wdenk1d6f9722004-09-09 17:44:35 +0000736#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
737#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200738#define CONFIG_SYS_OPB_FREQ 66666666
wdenk180d3f72004-01-04 16:28:35 +0000739#else
740/* Model BA (default) */
wdenk1d6f9722004-09-09 17:44:35 +0000741#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
742#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200743#define CONFIG_SYS_OPB_FREQ 66666666
wdenke55ca7e2004-07-01 21:40:08 +0000744#endif
wdenk12f34242003-09-02 22:48:03 +0000745
wdenk1d6f9722004-09-09 17:44:35 +0000746#endif /* CONFIG_NO_SERIAL_EEPROM */
wdenk180d3f72004-01-04 16:28:35 +0000747
wdenk1d6f9722004-09-09 17:44:35 +0000748#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
wdenk998eaae2004-04-18 19:43:36 +0000749#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
750
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200751/*
752 * JFFS2 partitions
753 */
754
755/* No command line, one static partition */
Stefan Roese68d7d652009-03-19 13:30:36 +0100756#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200757#define CONFIG_JFFS2_DEV "nand0"
758#define CONFIG_JFFS2_PART_SIZE 0x00400000
759#define CONFIG_JFFS2_PART_OFFSET 0x00000000
760
761/* mtdparts command line support */
762/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100763#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200764#define MTDIDS_DEFAULT "nor0=PPChameleon-0,nand0=ppchameleonevb-nand"
765*/
766
767/* 256 kB U-boot image */
768/*
769#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
770 "1792k(user),256k(u-boot);" \
771 "ppchameleonevb-nand:-(nand)"
772*/
773
774/* 320 kB U-boot image */
775/*
776#define MTDPARTS_DEFAULT "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
777 "1728k(user),320k(u-boot);" \
778 "ppchameleonevb-nand:-(nand)"
779*/
780
wdenk12f34242003-09-02 22:48:03 +0000781#endif /* __CONFIG_H */