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wdenk5b1d7132002-11-03 00:07:02 +00001/*
2 * (C) Copyright 2001-2002
3 * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk5b1d7132002-11-03 00:07:02 +00006 */
7
8/************************************************************************/
9/* ** HEADER FILES */
10/************************************************************************/
11
wdenk8564acf2003-07-14 22:13:32 +000012/* #define DEBUG */
13
wdenk5b1d7132002-11-03 00:07:02 +000014#include <config.h>
15#include <common.h>
wdenkc3f4d172004-06-25 23:35:58 +000016#include <command.h>
wdenk7aa78612003-05-03 15:50:43 +000017#include <watchdog.h>
wdenk5b1d7132002-11-03 00:07:02 +000018#include <version.h>
19#include <stdarg.h>
20#include <lcdvideo.h>
21#include <linux/types.h>
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +020022#include <stdio_dev.h>
wdenk4532cb62003-04-27 22:52:51 +000023#if defined(CONFIG_POST)
24#include <post.h>
25#endif
wdenk682011f2003-06-03 23:54:09 +000026#include <lcd.h>
wdenk5b1d7132002-11-03 00:07:02 +000027
28#ifdef CONFIG_LCD
29
30/************************************************************************/
31/* ** CONFIG STUFF -- should be moved to board config file */
32/************************************************************************/
wdenk88804d12005-07-04 00:03:16 +000033#ifndef CONFIG_LCD_INFO
34#define CONFIG_LCD_INFO /* Display Logo, (C) and system info */
35#endif
wdenk608c9142003-01-13 23:54:46 +000036
wdenkd791b1d2003-04-20 14:04:18 +000037#if defined(CONFIG_V37) || defined(CONFIG_EDT32F10)
wdenk608c9142003-01-13 23:54:46 +000038#undef CONFIG_LCD_LOGO
wdenk88804d12005-07-04 00:03:16 +000039#undef CONFIG_LCD_INFO
wdenk608c9142003-01-13 23:54:46 +000040#endif
41
wdenk5b1d7132002-11-03 00:07:02 +000042/*----------------------------------------------------------------------*/
43#ifdef CONFIG_KYOCERA_KCS057QV1AJ
44/*
45 * Kyocera KCS057QV1AJ-G23. Passive, color, single scan.
46 */
47#define LCD_BPP LCD_COLOR4
48
wdenk8655b6f2004-10-09 23:25:58 +000049vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
wdenk5b1d7132002-11-03 00:07:02 +000051 LCD_BPP, 1, 0, 1, 0, 5, 0, 0, 0
52 /* wbl, vpw, lcdac, wbf */
53};
54#endif /* CONFIG_KYOCERA_KCS057QV1AJ */
55/*----------------------------------------------------------------------*/
56
57/*----------------------------------------------------------------------*/
wdenk682011f2003-06-03 23:54:09 +000058#ifdef CONFIG_HITACHI_SP19X001_Z1A
59/*
60 * Hitachi SP19X001-. Active, color, single scan.
61 */
wdenk8655b6f2004-10-09 23:25:58 +000062vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063 640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
wdenk682011f2003-06-03 23:54:09 +000064 LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0
65 /* wbl, vpw, lcdac, wbf */
66};
67#endif /* CONFIG_HITACHI_SP19X001_Z1A */
68/*----------------------------------------------------------------------*/
69
70/*----------------------------------------------------------------------*/
wdenkfd3103b2003-11-25 16:55:19 +000071#ifdef CONFIG_NEC_NL6448AC33
wdenk5b1d7132002-11-03 00:07:02 +000072/*
wdenkfd3103b2003-11-25 16:55:19 +000073 * NEC NL6448AC33-18. Active, color, single scan.
wdenk5b1d7132002-11-03 00:07:02 +000074 */
wdenk8655b6f2004-10-09 23:25:58 +000075vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
wdenk5b1d7132002-11-03 00:07:02 +000077 3, 0, 0, 1, 1, 144, 2, 0, 33
78 /* wbl, vpw, lcdac, wbf */
79};
wdenkfd3103b2003-11-25 16:55:19 +000080#endif /* CONFIG_NEC_NL6448AC33 */
wdenk5b1d7132002-11-03 00:07:02 +000081/*----------------------------------------------------------------------*/
82
wdenkfd3103b2003-11-25 16:55:19 +000083#ifdef CONFIG_NEC_NL6448BC20
wdenk5b1d7132002-11-03 00:07:02 +000084/*
wdenkfd3103b2003-11-25 16:55:19 +000085 * NEC NL6448BC20-08. 6.5", 640x480. Active, color, single scan.
wdenk5b1d7132002-11-03 00:07:02 +000086 */
wdenk8655b6f2004-10-09 23:25:58 +000087vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
wdenk5b1d7132002-11-03 00:07:02 +000089 3, 0, 0, 1, 1, 144, 2, 0, 33
90 /* wbl, vpw, lcdac, wbf */
91};
wdenkfd3103b2003-11-25 16:55:19 +000092#endif /* CONFIG_NEC_NL6448BC20 */
93/*----------------------------------------------------------------------*/
94
95#ifdef CONFIG_NEC_NL6448BC33_54
96/*
97 * NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan.
98 */
wdenk8655b6f2004-10-09 23:25:58 +000099vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100 640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
wdenkfd3103b2003-11-25 16:55:19 +0000101 3, 0, 0, 1, 1, 144, 2, 0, 33
102 /* wbl, vpw, lcdac, wbf */
103};
104#endif /* CONFIG_NEC_NL6448BC33_54 */
wdenk5b1d7132002-11-03 00:07:02 +0000105/*----------------------------------------------------------------------*/
106
107#ifdef CONFIG_SHARP_LQ104V7DS01
108/*
109 * SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan.
110 */
wdenk8655b6f2004-10-09 23:25:58 +0000111vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
wdenk5b1d7132002-11-03 00:07:02 +0000113 3, 0, 0, 1, 1, 25, 1, 0, 33
114 /* wbl, vpw, lcdac, wbf */
115};
116#endif /* CONFIG_SHARP_LQ104V7DS01 */
117/*----------------------------------------------------------------------*/
118
119#ifdef CONFIG_SHARP_16x9
120/*
121 * Sharp 320x240. Active, color, single scan. It isn't 16x9, and I am
122 * not sure what it is.......
123 */
wdenk8655b6f2004-10-09 23:25:58 +0000124vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
wdenk5b1d7132002-11-03 00:07:02 +0000126 3, 0, 0, 1, 1, 15, 4, 0, 3
127};
128#endif /* CONFIG_SHARP_16x9 */
129/*----------------------------------------------------------------------*/
130
131#ifdef CONFIG_SHARP_LQ057Q3DC02
132/*
133 * Sharp LQ057Q3DC02 display. Active, color, single scan.
134 */
wdenk8655b6f2004-10-09 23:25:58 +0000135#undef LCD_DF
wdenk4a6fd342003-04-12 23:38:12 +0000136#define LCD_DF 12
137
wdenk8655b6f2004-10-09 23:25:58 +0000138vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
wdenk5b1d7132002-11-03 00:07:02 +0000140 3, 0, 0, 1, 1, 15, 4, 0, 3
141 /* wbl, vpw, lcdac, wbf */
142};
wdenk88804d12005-07-04 00:03:16 +0000143#define CONFIG_LCD_INFO_BELOW_LOGO
wdenk5b1d7132002-11-03 00:07:02 +0000144#endif /* CONFIG_SHARP_LQ057Q3DC02 */
145/*----------------------------------------------------------------------*/
146
147#ifdef CONFIG_SHARP_LQ64D341
148/*
149 * Sharp LQ64D341 display, 640x480. Active, color, single scan.
150 */
wdenk8655b6f2004-10-09 23:25:58 +0000151vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
wdenk5b1d7132002-11-03 00:07:02 +0000153 3, 0, 0, 1, 1, 128, 16, 0, 32
154 /* wbl, vpw, lcdac, wbf */
155};
156#endif /* CONFIG_SHARP_LQ64D341 */
wdenk608c9142003-01-13 23:54:46 +0000157
dzu29127b62003-09-25 22:30:12 +0000158#ifdef CONFIG_SHARP_LQ065T9DR51U
159/*
160 * Sharp LQ065T9DR51U display, 400x240. Active, color, single scan.
161 */
wdenk8655b6f2004-10-09 23:25:58 +0000162vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163 400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
dzu29127b62003-09-25 22:30:12 +0000164 3, 0, 0, 1, 1, 248, 4, 0, 35
165 /* wbl, vpw, lcdac, wbf */
166};
wdenk88804d12005-07-04 00:03:16 +0000167#define CONFIG_LCD_INFO_BELOW_LOGO
dzu29127b62003-09-25 22:30:12 +0000168#endif /* CONFIG_SHARP_LQ065T9DR51U */
169
wdenk608c9142003-01-13 23:54:46 +0000170#ifdef CONFIG_SHARP_LQ084V1DG21
171/*
172 * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan.
173 */
wdenk8655b6f2004-10-09 23:25:58 +0000174vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175 640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
wdenk608c9142003-01-13 23:54:46 +0000176 3, 0, 0, 1, 1, 160, 3, 0, 48
177 /* wbl, vpw, lcdac, wbf */
178};
179#endif /* CONFIG_SHARP_LQ084V1DG21 */
180
wdenk5b1d7132002-11-03 00:07:02 +0000181/*----------------------------------------------------------------------*/
182
183#ifdef CONFIG_HLD1045
184/*
185 * HLD1045 display, 640x480. Active, color, single scan.
186 */
wdenk8655b6f2004-10-09 23:25:58 +0000187vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
wdenk5b1d7132002-11-03 00:07:02 +0000189 3, 0, 0, 1, 1, 160, 3, 0, 48
190 /* wbl, vpw, lcdac, wbf */
191};
192#endif /* CONFIG_HLD1045 */
193/*----------------------------------------------------------------------*/
194
195#ifdef CONFIG_PRIMEVIEW_V16C6448AC
196/*
197 * Prime View V16C6448AC
198 */
wdenk8655b6f2004-10-09 23:25:58 +0000199vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200 640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
wdenk5b1d7132002-11-03 00:07:02 +0000201 3, 0, 0, 1, 1, 144, 2, 0, 35
202 /* wbl, vpw, lcdac, wbf */
203};
204#endif /* CONFIG_PRIMEVIEW_V16C6448AC */
205
206/*----------------------------------------------------------------------*/
207
208#ifdef CONFIG_OPTREX_BW
209/*
210 * Optrex CBL50840-2 NF-FW 99 22 M5
211 * or
212 * Hitachi LMG6912RPFC-00T
213 * or
214 * Hitachi SP14Q002
215 *
216 * 320x240. Black & white.
217 */
218#define OPTREX_BPP 0 /* 0 - monochrome, 1 bpp */
219 /* 1 - 4 grey levels, 2 bpp */
220 /* 2 - 16 grey levels, 4 bpp */
wdenk8655b6f2004-10-09 23:25:58 +0000221vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
wdenk5b1d7132002-11-03 00:07:02 +0000223 OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4
224};
225#endif /* CONFIG_OPTREX_BW */
226
227/*-----------------------------------------------------------------*/
228#ifdef CONFIG_EDT32F10
229/*
230 * Emerging Display Technologies 320x240. Passive, monochrome, single scan.
231 */
232#define LCD_BPP LCD_MONOCHROME
wdenk4a6fd342003-04-12 23:38:12 +0000233#define LCD_DF 10
wdenk5b1d7132002-11-03 00:07:02 +0000234
wdenk8655b6f2004-10-09 23:25:58 +0000235vidinfo_t panel_info = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
wdenk4a6fd342003-04-12 23:38:12 +0000237 LCD_BPP, 0, 0, 0, 0, 33, 0, 0, 0
wdenk5b1d7132002-11-03 00:07:02 +0000238};
239#endif
wdenk5b1d7132002-11-03 00:07:02 +0000240
wdenk5b1d7132002-11-03 00:07:02 +0000241/************************************************************************/
242/* ----------------- chipset specific functions ----------------------- */
243/************************************************************************/
244
wdenk8655b6f2004-10-09 23:25:58 +0000245/*
246 * Calculate fb size for VIDEOLFB_ATAG.
247 */
248ulong calc_fbsize (void)
249{
250 ulong size;
251 int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
252
253 size = line_length * panel_info.vl_row;
254
255 return size;
256}
257
258void lcd_ctrl_init (void *lcdbase)
wdenk5b1d7132002-11-03 00:07:02 +0000259{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
wdenk5b1d7132002-11-03 00:07:02 +0000261 volatile lcd823_t *lcdp = &immr->im_lcd;
262
263 uint lccrtmp;
wdenk682011f2003-06-03 23:54:09 +0000264 uint lchcr_hpc_tmp;
wdenk5b1d7132002-11-03 00:07:02 +0000265
266 /* Initialize the LCD control register according to the LCD
267 * parameters defined. We do everything here but enable
268 * the controller.
269 */
270
wdenke63c8ee2004-06-09 21:04:48 +0000271#ifdef CONFIG_RPXLITE
272 /* This is special for RPXlite_DW Software Development Platform **[Sam]** */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273 panel_info.vl_dp = CONFIG_SYS_LOW;
wdenke63c8ee2004-06-09 21:04:48 +0000274#endif
275
wdenk5b1d7132002-11-03 00:07:02 +0000276 lccrtmp = LCDBIT (LCCR_BNUM_BIT,
277 (((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128));
278
279 lccrtmp |= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp) |
280 LCDBIT (LCCR_OEP_BIT, panel_info.vl_oep) |
281 LCDBIT (LCCR_HSP_BIT, panel_info.vl_hsp) |
282 LCDBIT (LCCR_VSP_BIT, panel_info.vl_vsp) |
283 LCDBIT (LCCR_DP_BIT, panel_info.vl_dp) |
284 LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix) |
285 LCDBIT (LCCR_LBW_BIT, panel_info.vl_lbw) |
286 LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt) |
287 LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor) |
288 LCDBIT (LCCR_TFT_BIT, panel_info.vl_tft);
289
290#if 0
291 lccrtmp |= ((SIU_LEVEL5 / 2) << 12);
292 lccrtmp |= LCCR_EIEN;
293#endif
294
295 lcdp->lcd_lccr = lccrtmp;
296 lcdp->lcd_lcsr = 0xFF; /* Clear pending interrupts */
297
298 /* Initialize LCD controller bus priorities.
299 */
wdenk682011f2003-06-03 23:54:09 +0000300#ifdef CONFIG_RBC823
301 immr->im_siu_conf.sc_sdcr = (immr->im_siu_conf.sc_sdcr & ~0x0f) | 1; /* RAID = 01, LAID = 00 */
302#else
wdenk5b1d7132002-11-03 00:07:02 +0000303 immr->im_siu_conf.sc_sdcr &= ~0x0f; /* RAID = LAID = 0 */
304
305 /* set SHFT/CLOCK division factor 4
306 * This needs to be set based upon display type and processor
307 * speed. The TFT displays run about 20 to 30 MHz.
308 * I was running 64 MHz processor speed.
309 * The value for this divider must be chosen so the result is
310 * an integer of the processor speed (i.e., divide by 3 with
311 * 64 MHz would be bad).
312 */
313 immr->im_clkrst.car_sccr &= ~0x1F;
314 immr->im_clkrst.car_sccr |= LCD_DF; /* was 8 */
315
wdenk682011f2003-06-03 23:54:09 +0000316#endif /* CONFIG_RBC823 */
317
318#if defined(CONFIG_RBC823)
319 /* Enable LCD on port D.
320 */
321 immr->im_ioport.iop_pddat &= 0x0300;
322 immr->im_ioport.iop_pdpar |= 0x1CFF;
323 immr->im_ioport.iop_pddir |= 0x1CFF;
324
325 /* Configure LCD_ON, VEE_ON, CCFL_ON on port B.
326 */
327 immr->im_cpm.cp_pbdat &= ~0x00005001;
328 immr->im_cpm.cp_pbpar &= ~0x00005001;
329 immr->im_cpm.cp_pbdir |= 0x00005001;
330#elif !defined(CONFIG_EDT32F10)
wdenk5b1d7132002-11-03 00:07:02 +0000331 /* Enable LCD on port D.
332 */
333 immr->im_ioport.iop_pdpar |= 0x1FFF;
334 immr->im_ioport.iop_pddir |= 0x1FFF;
335
336 /* Enable LCD_A/B/C on port B.
337 */
338 immr->im_cpm.cp_pbpar |= 0x00005001;
339 immr->im_cpm.cp_pbdir |= 0x00005001;
340#else
341 /* Enable LCD on port D.
342 */
343 immr->im_ioport.iop_pdpar |= 0x1DFF;
344 immr->im_ioport.iop_pdpar &= ~0x0200;
345 immr->im_ioport.iop_pddir |= 0x1FFF;
346 immr->im_ioport.iop_pddat |= 0x0200;
347#endif
348
349 /* Load the physical address of the linear frame buffer
350 * into the LCD controller.
351 * BIG NOTE: This has to be modified to load A and B depending
352 * upon the split mode of the LCD.
353 */
Jeroen Hofstee00a0ca52013-01-22 10:44:12 +0000354 lcdp->lcd_lcfaa = (ulong)lcdbase;
355 lcdp->lcd_lcfba = (ulong)lcdbase;
wdenk5b1d7132002-11-03 00:07:02 +0000356
357 /* MORE HACKS...This must be updated according to 823 manual
358 * for different panels.
wdenk682011f2003-06-03 23:54:09 +0000359 * Udi Finkelstein - done - see below:
360 * Note: You better not try unsupported combinations such as
361 * 4-bit wide passive dual scan LCD at 4/8 Bit color.
wdenk5b1d7132002-11-03 00:07:02 +0000362 */
wdenk682011f2003-06-03 23:54:09 +0000363 lchcr_hpc_tmp =
wdenk8bde7f72003-06-27 21:31:46 +0000364 (panel_info.vl_col *
wdenk682011f2003-06-03 23:54:09 +0000365 (panel_info.vl_tft ? 8 :
366 (((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */
367 /* use << to mult by: single scan = 1, dual scan = 2 */
368 panel_info.vl_splt) *
369 (panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */
370
wdenk5b1d7132002-11-03 00:07:02 +0000371 lcdp->lcd_lchcr = LCHCR_BO |
372 LCDBIT (LCHCR_AT_BIT, 4) |
wdenk682011f2003-06-03 23:54:09 +0000373 LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) |
wdenk5b1d7132002-11-03 00:07:02 +0000374 panel_info.vl_wbl;
wdenk5b1d7132002-11-03 00:07:02 +0000375
376 lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) |
377 LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) |
378 LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) |
379 panel_info.vl_wbf;
380
381}
382
383/*----------------------------------------------------------------------*/
384
wdenk5b1d7132002-11-03 00:07:02 +0000385#if LCD_BPP == LCD_COLOR8
wdenk8655b6f2004-10-09 23:25:58 +0000386void
wdenk5b1d7132002-11-03 00:07:02 +0000387lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
388{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
wdenk5b1d7132002-11-03 00:07:02 +0000390 volatile cpm8xx_t *cp = &(immr->im_cpm);
391 unsigned short colreg, *cmap_ptr;
392
393 cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2];
394
395 colreg = ((red & 0x0F) << 8) |
396 ((green & 0x0F) << 4) |
397 (blue & 0x0F) ;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#ifdef CONFIG_SYS_INVERT_COLORS
wdenk5b1d7132002-11-03 00:07:02 +0000399 colreg ^= 0x0FFF;
400#endif
401 *cmap_ptr = colreg;
402
403 debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n",
404 regno, &(cp->lcd_cmap[regno * 2]),
405 red, green, blue,
wdenk8bde7f72003-06-27 21:31:46 +0000406 cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]);
wdenk5b1d7132002-11-03 00:07:02 +0000407}
408#endif /* LCD_COLOR8 */
409
410/*----------------------------------------------------------------------*/
411
412#if LCD_BPP == LCD_MONOCHROME
413static
414void lcd_initcolregs (void)
415{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
wdenk5b1d7132002-11-03 00:07:02 +0000417 volatile cpm8xx_t *cp = &(immr->im_cpm);
418 ushort regno;
419
420 for (regno = 0; regno < 16; regno++) {
421 cp->lcd_cmap[regno * 2] = 0;
422 cp->lcd_cmap[(regno * 2) + 1] = regno & 0x0f;
423 }
424}
425#endif
426
427/*----------------------------------------------------------------------*/
428
wdenk8655b6f2004-10-09 23:25:58 +0000429void lcd_enable (void)
wdenk5b1d7132002-11-03 00:07:02 +0000430{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
wdenk5b1d7132002-11-03 00:07:02 +0000432 volatile lcd823_t *lcdp = &immr->im_lcd;
433
434 /* Enable the LCD panel */
wdenk682011f2003-06-03 23:54:09 +0000435#ifndef CONFIG_RBC823
wdenk5b1d7132002-11-03 00:07:02 +0000436 immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */
wdenk682011f2003-06-03 23:54:09 +0000437#endif
wdenk5b1d7132002-11-03 00:07:02 +0000438 lcdp->lcd_lccr |= LCCR_PON;
wdenk608c9142003-01-13 23:54:46 +0000439
440#ifdef CONFIG_V37
441 /* Turn on display backlight */
442 immr->im_cpm.cp_pbpar |= 0x00008000;
443 immr->im_cpm.cp_pbdir |= 0x00008000;
wdenk682011f2003-06-03 23:54:09 +0000444#elif defined(CONFIG_RBC823)
445 /* Turn on display backlight */
446 immr->im_cpm.cp_pbdat |= 0x00004000;
wdenk608c9142003-01-13 23:54:46 +0000447#endif
448
wdenk5b1d7132002-11-03 00:07:02 +0000449#if defined(CONFIG_LWMON)
450 { uchar c = pic_read (0x60);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON)
wdenk7d7ce412004-03-17 01:13:07 +0000452 /* Enable LCD later in sysmon test, only if temperature is OK */
wdenk4532cb62003-04-27 22:52:51 +0000453#else
wdenk8bde7f72003-06-27 21:31:46 +0000454 c |= 0x07; /* Power on CCFL, Enable CCFL, Chip Enable LCD */
wdenk4532cb62003-04-27 22:52:51 +0000455#endif
wdenk5b1d7132002-11-03 00:07:02 +0000456 pic_write (0x60, c);
457 }
wdenk5b1d7132002-11-03 00:07:02 +0000458#endif /* CONFIG_LWMON */
wdenk4a6fd342003-04-12 23:38:12 +0000459
460#if defined(CONFIG_R360MPI)
461 {
462 extern void r360_i2c_lcd_write (uchar data0, uchar data1);
wdenkcb4dbb72003-07-16 16:40:22 +0000463 unsigned long bgi, ctr;
464 char *p;
465
466 if ((p = getenv("lcdbgi")) != NULL) {
467 bgi = simple_strtoul (p, 0, 10) & 0xFFF;
468 } else {
469 bgi = 0xFFF;
470 }
471
472 if ((p = getenv("lcdctr")) != NULL) {
473 ctr = simple_strtoul (p, 0, 10) & 0xFFF;
474 } else {
475 ctr=0x7FF;
476 }
wdenk4a6fd342003-04-12 23:38:12 +0000477
478 r360_i2c_lcd_write(0x10, 0x01);
479 r360_i2c_lcd_write(0x20, 0x01);
wdenkcb4dbb72003-07-16 16:40:22 +0000480 r360_i2c_lcd_write(0x30 | ((bgi>>8) & 0xF), bgi & 0xFF);
481 r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF);
wdenk4a6fd342003-04-12 23:38:12 +0000482 }
483#endif /* CONFIG_R360MPI */
wdenk682011f2003-06-03 23:54:09 +0000484#ifdef CONFIG_RBC823
485 udelay(200000); /* wait 200ms */
486 /* Turn VEE_ON first */
487 immr->im_cpm.cp_pbdat |= 0x00000001;
488 udelay(200000); /* wait 200ms */
489 /* Now turn on LCD_ON */
490 immr->im_cpm.cp_pbdat |= 0x00001000;
491#endif
wdenk8564acf2003-07-14 22:13:32 +0000492#ifdef CONFIG_RRVISION
493 debug ("PC4->Output(1): enable LVDS\n");
494 debug ("PC5->Output(0): disable PAL clock\n");
495 immr->im_ioport.iop_pddir |= 0x1000;
496 immr->im_ioport.iop_pcpar &= ~(0x0C00);
497 immr->im_ioport.iop_pcdir |= 0x0C00 ;
498 immr->im_ioport.iop_pcdat |= 0x0800 ;
499 immr->im_ioport.iop_pcdat &= ~(0x0400);
500 debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n",
501 immr->im_ioport.iop_pdpar,
502 immr->im_ioport.iop_pddir,
503 immr->im_ioport.iop_pddat);
504 debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n",
505 immr->im_ioport.iop_pcpar,
506 immr->im_ioport.iop_pcdir,
507 immr->im_ioport.iop_pcdat);
508#endif
wdenk5b1d7132002-11-03 00:07:02 +0000509}
510
511/*----------------------------------------------------------------------*/
512
wdenk682011f2003-06-03 23:54:09 +0000513#if defined (CONFIG_RBC823)
514void lcd_disable (void)
wdenk5b1d7132002-11-03 00:07:02 +0000515{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200516 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
wdenk5b1d7132002-11-03 00:07:02 +0000517 volatile lcd823_t *lcdp = &immr->im_lcd;
518
519#if defined(CONFIG_LWMON)
520 { uchar c = pic_read (0x60);
wdenk8bde7f72003-06-27 21:31:46 +0000521 c &= ~0x07; /* Power off CCFL, Disable CCFL, Chip Disable LCD */
wdenk5b1d7132002-11-03 00:07:02 +0000522 pic_write (0x60, c);
523 }
524#elif defined(CONFIG_R360MPI)
525 {
wdenk4a6fd342003-04-12 23:38:12 +0000526 extern void r360_i2c_lcd_write (uchar data0, uchar data1);
wdenk5b1d7132002-11-03 00:07:02 +0000527
wdenk4a6fd342003-04-12 23:38:12 +0000528 r360_i2c_lcd_write(0x10, 0x00);
529 r360_i2c_lcd_write(0x20, 0x00);
530 r360_i2c_lcd_write(0x30, 0x00);
531 r360_i2c_lcd_write(0x40, 0x00);
wdenk5b1d7132002-11-03 00:07:02 +0000532 }
533#endif /* CONFIG_LWMON */
534 /* Disable the LCD panel */
535 lcdp->lcd_lccr &= ~LCCR_PON;
wdenk682011f2003-06-03 23:54:09 +0000536#ifdef CONFIG_RBC823
537 /* Turn off display backlight, VEE and LCD_ON */
538 immr->im_cpm.cp_pbdat &= ~0x00005001;
539#else
wdenk5b1d7132002-11-03 00:07:02 +0000540 immr->im_siu_conf.sc_sdcr &= ~(1 << (31 - 25)); /* LAM = 0 */
wdenk682011f2003-06-03 23:54:09 +0000541#endif /* CONFIG_RBC823 */
wdenk5b1d7132002-11-03 00:07:02 +0000542}
wdenk682011f2003-06-03 23:54:09 +0000543#endif /* NOT_USED_SO_FAR || CONFIG_RBC823 */
wdenk5b1d7132002-11-03 00:07:02 +0000544
545
546/************************************************************************/
wdenk5b1d7132002-11-03 00:07:02 +0000547
548#endif /* CONFIG_LCD */