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wdenk3a473b22004-01-03 00:43:19 +00001/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk3a473b22004-01-03 00:43:19 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12/*************************************************************************
13 * (c) 2002 Datentechnik AG - Project: Dino
14 *
15 *
16 * $Id: DB64360.h,v 1.3 2003/04/26 04:58:13 brad Exp $
17 *
18 ************************************************************************/
19
20/*************************************************************************
21 *
22 * History:
23 *
24 * $Log: DB64360.h,v $
25 * Revision 1.3 2003/04/26 04:58:13 brad
26 * Cosmetic changes and compiler warning cleanups
27 *
28 * Revision 1.2 2003/04/23 15:48:15 ingo
29 * mem. map output added
30 *
31 * Revision 1.1 2003/04/17 09:31:42 ias
32 * keymile changes 17_04_2003
33 *
34 * Revision 1.10 2003/03/06 12:25:04 ias
35 * 750 FX CPU HID settings updated
36 *
37 * Revision 1.9 2003/03/03 16:14:36 ias
38 * cleanup compiler warnings of printf fuctions
39 *
40 * Revision 1.8 2003/03/03 15:11:44 ias
41 * Marvell MPSC-UART is working
42 *
43 * Revision 1.7 2003/02/26 12:15:45 ssu
44 * adapted default parameters to new board flash address
45 *
46 * Revision 1.6 2003/02/25 14:55:42 ssu
47 * changed default environment parameters
48 *
49 * Revision 1.5 2003/02/21 17:14:23 ias
50 * added extended SPD handling
51 *
52 * Revision 1.4 2003/01/14 09:16:08 ias
53 * PPCBoot for Marvel Beta 0.9
54 *
55 * Revision 1.3 2002/12/03 13:56:26 ias
56 * Environment in flash support added
57 *
58 * Revision 1.2 2002/11/29 16:53:29 ias
59 * Flash support for STM added
60 *
61 * Revision 1.1 2002/11/29 13:36:31 ias
62 * Revision 0.1 of PPCBOOT (1.1.5) for Marvell DB64360 IBM750FX Board
63 * - working DDRRAM (only 32MByte of 128MB Modul)
64 * - working I2C Driver for SPD EEPROM read
65 * - working DUART 16650 for Serial Console
66 * - working "console"
67 *
68 *
69 *
70 ************************************************************************/
71
72#ifndef __CONFIG_H
73#define __CONFIG_H
74
wdenk3a473b22004-01-03 00:43:19 +000075/* This define must be before the core.h include */
76#define CONFIG_DB64360 1 /* this is an DB64360 board */
77
78#ifndef __ASSEMBLY__
79#include "../board/Marvell/include/core.h"
80#endif
81
82/*-----------------------------------------------------*/
83/* #include "../board/db64360/local.h" */
84#ifndef __LOCAL_H
85#define __LOCAL_H
86
87/* first ethernet */
88#define CONFIG_ETHADDR 64:36:00:00:00:01
89 /* next two ethernet hwaddrs */
wdenke2ffd592004-12-31 09:32:47 +000090#define CONFIG_HAS_ETH1
wdenk3a473b22004-01-03 00:43:19 +000091#define CONFIG_ETH1ADDR 64:36:00:00:00:02
92/* in the atlantis 64360 we have only 2 ETH port on the board,
93if we use PCI it has its own MAC addr */
94
95#define CONFIG_ENV_OVERWRITE
96#endif /* __CONFIG_H */
97
98/*
99 * High Level Configuration Options
100 * (easy to change)
101 */
102
103#define CONFIG_74xx /* we have a 750FX (override local.h) */
104
105#define CONFIG_DB64360 1 /* this is an DB64360 board */
106
Wolfgang Denk2ae18242010-10-06 09:05:45 +0200107#define CONFIG_SYS_TEXT_BASE 0xfff00000
108
wdenk3a473b22004-01-03 00:43:19 +0000109#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
110/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
111 DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
112 so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
113 see sdram_init.c */
114#undef CONFIG_ECC /* enable ECC support */
115#define CONFIG_MV64360_ECC
116
117/* which initialization functions to call for this board */
118#define CONFIG_MISC_INIT_R /* initialize the icache L1 */
wdenkc837dcb2004-01-20 23:12:12 +0000119#define CONFIG_BOARD_EARLY_INIT_F
wdenk3a473b22004-01-03 00:43:19 +0000120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_BOARD_NAME "DB64360"
wdenk3a473b22004-01-03 00:43:19 +0000122#define CONFIG_IDENT_STRING "Marvell DB64360 (1.1)"
123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124/*#define CONFIG_SYS_HUSH_PARSER */
125#undef CONFIG_SYS_HUSH_PARSER
wdenk3a473b22004-01-03 00:43:19 +0000126
wdenk3a473b22004-01-03 00:43:19 +0000127
128/*
129 * The following defines let you select what serial you want to use
130 * for your console driver.
131 *
132 * what to do:
133 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134 * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
wdenk3a473b22004-01-03 00:43:19 +0000135 * to 0 below.
136 *
137 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
138 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
139 */
140
141#define CONFIG_MPSC_PORT 0
142
143/* to change the default ethernet port, use this define (options: 0, 1, 2) */
wdenk3a473b22004-01-03 00:43:19 +0000144#define MV_ETH_DEVS 2
145
146/* #undef CONFIG_ETHER_PORT_MII */
147#if 0
148#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
149#else
150#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
151#endif
152#define CONFIG_ZERO_BOOTDELAY_CHECK
153
154
155#undef CONFIG_BOOTARGS
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100156/*#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
wdenk3a473b22004-01-03 00:43:19 +0000157
158/* ronen - autoboot using tftp */
159#if (CONFIG_BOOTDELAY >= 0)
160#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100161 setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \
162 ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; "
wdenk3a473b22004-01-03 00:43:19 +0000163
164#define CONFIG_BOOTARGS "console=ttyS0,115200"
165
166#endif
167
168/* ronen - the u-boot.bin should be ~0x30000 bytes */
169#define CONFIG_EXTRA_ENV_SETTINGS \
170 "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
171cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
172 "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
173cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
174 "bootargs_root=root=/dev/nfs rw\0" \
175 "bootargs_end=:::DB64360:eth0:none \0"\
176 "ethprime=mv_enet0\0"\
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100177 "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \
178ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
wdenk3a473b22004-01-03 00:43:19 +0000179
180/* --------------------------------------------------------------------------------------------------------------- */
181/* New bootcommands for Marvell DB64360 c 2002 Ingo Assmus */
182
183#define CONFIG_IPADDR 10.2.40.90
184
185#define CONFIG_SERIAL "No. 1"
186#define CONFIG_SERVERIP 10.2.1.126
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000187#define CONFIG_ROOTPATH "/mnt/yellow_dog_mini"
wdenk3a473b22004-01-03 00:43:19 +0000188
189
190#define CONFIG_TESTDRAMDATA y
191#define CONFIG_TESTDRAMADDRESS n
192#define CONFIG_TESETDRAMWALK n
193
194/* --------------------------------------------------------------------------------------------------------------- */
195
196#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
wdenk3a473b22004-01-03 00:43:19 +0000198
199#undef CONFIG_WATCHDOG /* watchdog disabled */
200#undef CONFIG_ALTIVEC /* undef to disable */
201
Jon Loeliger5d2ebe12007-07-09 21:16:53 -0500202/*
203 * BOOTP options
204 */
205#define CONFIG_BOOTP_SUBNETMASK
206#define CONFIG_BOOTP_GATEWAY
207#define CONFIG_BOOTP_HOSTNAME
208#define CONFIG_BOOTP_BOOTPATH
209#define CONFIG_BOOTP_BOOTFILESIZE
210
211
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200212/*
213 * JFFS2 partitions
214 *
215 */
216/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100217#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200218#define CONFIG_JFFS2_DEV "nor1"
219#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
220#define CONFIG_JFFS2_PART_OFFSET 0x00000000
wdenk3a473b22004-01-03 00:43:19 +0000221
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200222/* mtdparts command line support */
223
224/* Use first bank for JFFS2, second bank contains U-Boot.
225 *
226 * Note: fake mtd_id's used, no linux mtd map file.
227 */
228/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100229#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200230#define MTDIDS_DEFAULT "nor1=db64360-1"
231#define MTDPARTS_DEFAULT "mtdparts=db64360-1:-(jffs2)"
232*/
wdenk3a473b22004-01-03 00:43:19 +0000233
wdenk3a473b22004-01-03 00:43:19 +0000234
Jon Loeliger3c3227f2007-07-07 20:40:43 -0500235/*
236 * Command line configuration.
237 */
238#include <config_cmd_default.h>
239
240#define CONFIG_CMD_ASKENV
241#define CONFIG_CMD_I2C
242#define CONFIG_CMD_EEPROM
243#define CONFIG_CMD_CACHE
244#define CONFIG_CMD_JFFS2
245#define CONFIG_CMD_PCI
246#define CONFIG_CMD_NET
247
wdenk3a473b22004-01-03 00:43:19 +0000248
249/*
250 * Miscellaneous configurable options
251 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
253#define CONFIG_SYS_I2C_MULTI_EEPROMS
254#define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed default */
wdenk3a473b22004-01-03 00:43:19 +0000255
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256/* #define CONFIG_SYS_GT_DUAL_CPU also for JTAG even with one cpu */
257#define CONFIG_SYS_LONGHELP /* undef to save memory */
258#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger3c3227f2007-07-07 20:40:43 -0500259#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk3a473b22004-01-03 00:43:19 +0000261#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk3a473b22004-01-03 00:43:19 +0000263#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
265#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
266#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk3a473b22004-01-03 00:43:19 +0000267
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268/*#define CONFIG_SYS_MEMTEST_START 0x00400000 memtest works on */
269/*#define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
270/*#define CONFIG_SYS_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */
wdenk3a473b22004-01-03 00:43:19 +0000271
272/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_DRAM_TEST
wdenk3a473b22004-01-03 00:43:19 +0000274 * DRAM tests
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275 * CONFIG_SYS_DRAM_TEST - enables the following tests.
wdenk3a473b22004-01-03 00:43:19 +0000276 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277 * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
wdenk3a473b22004-01-03 00:43:19 +0000278 * Environment variable 'test_dram_data' must be
279 * set to 'y'.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280 * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
wdenk3a473b22004-01-03 00:43:19 +0000281 * addressable. Environment variable
282 * 'test_dram_address' must be set to 'y'.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283 * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
wdenk3a473b22004-01-03 00:43:19 +0000284 * This test takes about 6 minutes to test 64 MB.
285 * Environment variable 'test_dram_walk' must be
286 * set to 'y'.
287 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_DRAM_TEST
289#if defined(CONFIG_SYS_DRAM_TEST)
290#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
291/* #define CONFIG_SYS_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
292#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
293#define CONFIG_SYS_DRAM_TEST_DATA
294#define CONFIG_SYS_DRAM_TEST_ADDRESS
295#define CONFIG_SYS_DRAM_TEST_WALK
296#endif /* CONFIG_SYS_DRAM_TEST */
wdenk3a473b22004-01-03 00:43:19 +0000297
298#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */
wdenk3a473b22004-01-03 00:43:19 +0000300
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */
wdenk3a473b22004-01-03 00:43:19 +0000302
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
wdenk3a473b22004-01-03 00:43:19 +0000304/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
Wolfgang Denkee80fa72010-06-13 18:38:23 +0200305#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
wdenk3a473b22004-01-03 00:43:19 +0000306
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
308#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */
wdenk3a473b22004-01-03 00:43:19 +0000309
310/*ronen - this is the Tclk (MV64360 core) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_TCLK 133000000
wdenk3a473b22004-01-03 00:43:19 +0000312
313
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenk3a473b22004-01-03 00:43:19 +0000315
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_750FX_HID0 0x8000c084
317#define CONFIG_SYS_750FX_HID1 0x54800000
318#define CONFIG_SYS_750FX_HID2 0x00000000
wdenk3a473b22004-01-03 00:43:19 +0000319
320/*
321 * Low Level Configuration Settings
322 * (address mappings, register initial values, etc.)
323 * You should know what you are doing if you make changes here.
324 */
325
326/*-----------------------------------------------------------------------
327 * Definitions for initial stack pointer and data area
328 */
329
330/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331 * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
wdenk3a473b22004-01-03 00:43:19 +0000332 * To an unused memory region. The stack will remain in cache until RAM
333 * is initialized
334*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_INIT_RAM_LOCK
336#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* unused memory region */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200337#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200338#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
wdenk3a473b22004-01-03 00:43:19 +0000339
340#define RELOCATE_INTERNAL_RAM_ADDR
341#ifdef RELOCATE_INTERNAL_RAM_ADDR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342 #define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf8000000
wdenk3a473b22004-01-03 00:43:19 +0000343#endif
344
345/*-----------------------------------------------------------------------
346 * Start addresses for the final memory configuration
347 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk3a473b22004-01-03 00:43:19 +0000349 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenk3a473b22004-01-03 00:43:19 +0000351/* Dummies for BAT 4-7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */
353#define CONFIG_SYS_SDRAM2_BASE 0x20000000
354#define CONFIG_SYS_SDRAM3_BASE 0x30000000
355#define CONFIG_SYS_SDRAM4_BASE 0x40000000
356#define CONFIG_SYS_FLASH_BASE 0xfff00000
wdenk3a473b22004-01-03 00:43:19 +0000357
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_DFL_BOOTCS_BASE 0xff800000
wdenk3a473b22004-01-03 00:43:19 +0000359#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/
360
361#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
362#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */
363#define PCI0_IO_BASE_BOOTM 0xfd000000
364
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
366#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
367#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
368#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
wdenk3a473b22004-01-03 00:43:19 +0000369
370/* areas to map different things with the GT in physical space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_DRAM_BANKS 4
wdenk3a473b22004-01-03 00:43:19 +0000372
373/* What to put in the bats. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
wdenk3a473b22004-01-03 00:43:19 +0000375
376/* Peripheral Device section */
377
378/*******************************************************/
379/* We have on the db64360 Board : */
380/* GT-Chipset Register Area */
381/* GT-Chipset internal SRAM 256k */
382/* SRAM on external device module */
383/* Real time clock on external device module */
384/* dobble UART on external device module */
385/* Data flash on external device module */
386/* Boot flash on external device module */
387/*******************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
389#define CONFIG_SYS_DB64360_RESET_ADDR 0x14000000 /* After power on Reset the DB64360 is here */
wdenk3a473b22004-01-03 00:43:19 +0000390
391/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
393#define CONFIG_SYS_DEV_BASE 0xfc000000 /* GT Devices CS start here */
wdenk3a473b22004-01-03 00:43:19 +0000394
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE /* DEV_CS0 device modul sram */
396#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */
397#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */
398#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) /* DEV_CS3 device modul large flash */
wdenk3a473b22004-01-03 00:43:19 +0000399
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_DEV0_SIZE _8M /* db64360 sram @ 0xfc00.0000 */
401#define CONFIG_SYS_DEV1_SIZE _8M /* db64360 rtc @ 0xfc80.0000 */
402#define CONFIG_SYS_DEV2_SIZE _16M /* db64360 duart @ 0xfd00.0000 */
403#define CONFIG_SYS_DEV3_SIZE _16M /* db64360 flash @ 0xfe00.0000 */
wdenk3a473b22004-01-03 00:43:19 +0000404/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
405
406/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */
408#define CONFIG_SYS_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */
409#define CONFIG_SYS_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */
410#define CONFIG_SYS_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */
411#define CONFIG_SYS_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */
wdenk3a473b22004-01-03 00:43:19 +0000412
413 /* c 4 a 8 2 4 1 c */
414 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
415 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
416 /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
417 /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
418
419
420/* ronen - update MPP Control MV64360*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#define CONFIG_SYS_MPP_CONTROL_0 0x02222222
422#define CONFIG_SYS_MPP_CONTROL_1 0x11333011
423#define CONFIG_SYS_MPP_CONTROL_2 0x40431111
424#define CONFIG_SYS_MPP_CONTROL_3 0x00000044
wdenk3a473b22004-01-03 00:43:19 +0000425
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426/*# define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */
wdenk3a473b22004-01-03 00:43:19 +0000427
428
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/
wdenk3a473b22004-01-03 00:43:19 +0000430 /* gpp[31] gpp[30] gpp[29] gpp[28] */
431 /* gpp[27] gpp[24]*/
432 /* gpp[19:14] */
433
434/* setup new config_value for MV64360 DDR-RAM !! */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435# define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/
wdenk3a473b22004-01-03 00:43:19 +0000436
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE
438#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */
439#define CONFIG_SYS_INIT_CHAN1
440#define CONFIG_SYS_INIT_CHAN2
wdenk3a473b22004-01-03 00:43:19 +0000441
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#define SRAM_BASE CONFIG_SYS_DEV0_SPACE
wdenk3a473b22004-01-03 00:43:19 +0000443#define SRAM_SIZE 0x00100000 /* 1 MB of sram */
444
445
446/*-----------------------------------------------------------------------
447 * PCI stuff
448 *-----------------------------------------------------------------------
449 */
450
451#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
452#define PCI_HOST_FORCE 1 /* configure as pci host */
453#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
454
455#define CONFIG_PCI /* include pci support */
456#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
457#define CONFIG_PCI_PNP /* do pci plug-and-play */
458#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */
459
460/* PCI MEMORY MAP section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
462#define CONFIG_SYS_PCI0_MEM_SIZE _128M
463#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
464#define CONFIG_SYS_PCI1_MEM_SIZE _128M
wdenk3a473b22004-01-03 00:43:19 +0000465
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200466#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
467#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
wdenk3a473b22004-01-03 00:43:19 +0000468
469/* PCI I/O MAP section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
471#define CONFIG_SYS_PCI0_IO_SIZE _16M
472#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
473#define CONFIG_SYS_PCI1_IO_SIZE _16M
wdenk3a473b22004-01-03 00:43:19 +0000474
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
476#define CONFIG_SYS_PCI0_IO_SPACE_PCI (CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
477#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
478#define CONFIG_SYS_PCI1_IO_SPACE_PCI (CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
wdenk3a473b22004-01-03 00:43:19 +0000479
480#if defined (CONFIG_750CX)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200481#define CONFIG_SYS_PCI_IDSEL 0x0
wdenk3a473b22004-01-03 00:43:19 +0000482#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200483#define CONFIG_SYS_PCI_IDSEL 0x30
wdenk3a473b22004-01-03 00:43:19 +0000484#endif
485/*----------------------------------------------------------------------
486 * Initial BAT mappings
487 */
488
489/* NOTES:
490 * 1) GUARDED and WRITE_THRU not allowed in IBATS
491 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
492 */
493
494/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200495#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
496#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
497#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
498#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
wdenk3a473b22004-01-03 00:43:19 +0000499
500/* init ram */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200501#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
502#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
503#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
504#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
wdenk3a473b22004-01-03 00:43:19 +0000505
506/* PCI0, PCI1 in one BAT */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200507#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
508#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
509#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
510#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk3a473b22004-01-03 00:43:19 +0000511
512/* GT regs, bootrom, all the devices, PCI I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200513#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
514#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
515#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
516#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenk3a473b22004-01-03 00:43:19 +0000517
518/* I2C addresses for the two DIMM SPD chips */
519#define DIMM0_I2C_ADDR 0x56
520#define DIMM1_I2C_ADDR 0x54
521
522/*
523 * For booting Linux, the board info and command line data
524 * have to be in the first 8 MB of memory, since this is
525 * the maximum mapped by the Linux kernel during initialization.
526 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200527#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
wdenk3a473b22004-01-03 00:43:19 +0000528
529/*-----------------------------------------------------------------------
530 * FLASH organization
531 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200532#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
533#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
wdenk3a473b22004-01-03 00:43:19 +0000534
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200535#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */
536#define CONFIG_SYS_EXTRA_FLASH_WIDTH 4 /* 32 bit */
537#define CONFIG_SYS_BOOT_FLASH_WIDTH 1 /* 8 bit */
wdenk3a473b22004-01-03 00:43:19 +0000538
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200539#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
540#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
541#define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */
542#define CONFIG_SYS_FLASH_CFI 1
wdenk3a473b22004-01-03 00:43:19 +0000543
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200544#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200545#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
546#define CONFIG_ENV_SECT_SIZE 0x10000
547#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200548/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
wdenk3a473b22004-01-03 00:43:19 +0000549
550/*-----------------------------------------------------------------------
551 * Cache Configuration
552 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200553#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
Jon Loeliger3c3227f2007-07-07 20:40:43 -0500554#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200555#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenk3a473b22004-01-03 00:43:19 +0000556#endif
557
558/*-----------------------------------------------------------------------
559 * L2CR setup -- make sure this is right for your board!
560 * look in include/mpc74xx.h for the defines used here
561 */
562
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200563#define CONFIG_SYS_L2
wdenk3a473b22004-01-03 00:43:19 +0000564
565
566#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
567#define L2_INIT 0
568#else
569
570#define L2_INIT 0
571/*
572#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
573 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
574*/
575#endif
576
577#define L2_ENABLE (L2_INIT | L2CR_L2E)
578
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200579#define CONFIG_SYS_BOARD_ASM_INIT 1
wdenk3a473b22004-01-03 00:43:19 +0000580
581#endif /* __CONFIG_H */