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wdenkbf9e3b32004-02-12 00:47:09 +00001/*
2 * Configuation settings for the Motorola MC5272C3 board.
3 *
4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenkbf9e3b32004-02-12 00:47:09 +00007 */
wdenk4e5ca3e2003-12-08 01:34:36 +00008
wdenkbf9e3b32004-02-12 00:47:09 +00009/*
10 * board/config.h - configuration options, board specific
11 */
wdenk4e5ca3e2003-12-08 01:34:36 +000012
wdenkbf9e3b32004-02-12 00:47:09 +000013#ifndef _M5272C3_H
14#define _M5272C3_H
15
16/*
17 * High Level Configuration Options
18 * (easy to change)
19 */
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050020#define CONFIG_MCF52x2 /* define processor family */
21#define CONFIG_M5272 /* define processor type */
wdenk4e5ca3e2003-12-08 01:34:36 +000022
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050023#define CONFIG_MCFTMR
wdenk4e5ca3e2003-12-08 01:34:36 +000024
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050025#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020026#define CONFIG_SYS_UART_PORT (0)
TsiChung Liew79e07992008-08-15 16:50:07 +000027#define CONFIG_BAUDRATE 115200
wdenk4e5ca3e2003-12-08 01:34:36 +000028
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050029#undef CONFIG_WATCHDOG
wdenkbf9e3b32004-02-12 00:47:09 +000030#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
31
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050032#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
wdenkbf9e3b32004-02-12 00:47:09 +000033
34/* Configuration for environment
35 * Environment is embedded in u-boot in the second sector of the flash
36 */
37#ifndef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020038#define CONFIG_ENV_OFFSET 0x4000
39#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020040#define CONFIG_ENV_IS_IN_FLASH 1
wdenkbf9e3b32004-02-12 00:47:09 +000041#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020042#define CONFIG_ENV_ADDR 0xffe04000
43#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020044#define CONFIG_ENV_IS_IN_FLASH 1
wdenkbf9e3b32004-02-12 00:47:09 +000045#endif
46
Jon Loeliger8353e132007-07-08 14:14:17 -050047/*
Jon Loeliger659e2f62007-07-10 09:10:49 -050048 * BOOTP options
49 */
50#define CONFIG_BOOTP_BOOTFILESIZE
51#define CONFIG_BOOTP_BOOTPATH
52#define CONFIG_BOOTP_GATEWAY
53#define CONFIG_BOOTP_HOSTNAME
54
Jon Loeliger659e2f62007-07-10 09:10:49 -050055/*
Jon Loeliger8353e132007-07-08 14:14:17 -050056 * Command line configuration.
57 */
58#include <config_cmd_default.h>
59
TsiChung Liewdd9f0542010-03-11 22:12:53 -060060#define CONFIG_CMD_CACHE
Jon Loeliger8353e132007-07-08 14:14:17 -050061#define CONFIG_CMD_MII
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050062#define CONFIG_CMD_NET
63#define CONFIG_CMD_PING
64#define CONFIG_CMD_MISC
65#define CONFIG_CMD_ELF
66#define CONFIG_CMD_FLASH
67#define CONFIG_CMD_MEMORY
Jon Loeliger8353e132007-07-08 14:14:17 -050068
69#undef CONFIG_CMD_LOADS
70#undef CONFIG_CMD_LOADB
71
wdenkbf9e3b32004-02-12 00:47:09 +000072#define CONFIG_BOOTDELAY 5
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050073#define CONFIG_MCFFEC
74#ifdef CONFIG_MCFFEC
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050075# define CONFIG_MII 1
TsiChung Liewd53cf6a2008-08-19 00:37:13 +060076# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077# define CONFIG_SYS_DISCOVER_PHY
78# define CONFIG_SYS_RX_ETH_BUFFER 8
79# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050080
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081# define CONFIG_SYS_FEC0_PINMUX 0
82# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
Wolfgang Denk53677ef2008-05-20 16:00:29 +020083# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
85# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050086# define FECDUPLEX FULL
87# define FECSPEED _100BASET
88# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
90# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050091# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050093#endif
94
95#ifdef CONFIG_MCFFEC
96# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
97# define CONFIG_IPADDR 192.162.1.2
98# define CONFIG_NETMASK 255.255.255.0
99# define CONFIG_SERVERIP 192.162.1.1
100# define CONFIG_GATEWAYIP 192.162.1.1
101# define CONFIG_OVERWRITE_ETHADDR_ONCE
102#endif /* CONFIG_MCFFEC */
103
104#define CONFIG_HOSTNAME M5272C3
105#define CONFIG_EXTRA_ENV_SETTINGS \
106 "netdev=eth0\0" \
107 "loadaddr=10000\0" \
108 "u-boot=u-boot.bin\0" \
109 "load=tftp ${loadaddr) ${u-boot}\0" \
110 "upd=run load; run prog\0" \
111 "prog=prot off ffe00000 ffe3ffff;" \
112 "era ffe00000 ffe3ffff;" \
113 "cp.b ${loadaddr} ffe00000 ${filesize};"\
114 "save\0" \
115 ""
wdenkbf9e3b32004-02-12 00:47:09 +0000116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_PROMPT "-> "
118#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkbf9e3b32004-02-12 00:47:09 +0000119
Jon Loeliger8353e132007-07-08 14:14:17 -0500120#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkbf9e3b32004-02-12 00:47:09 +0000122#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkbf9e3b32004-02-12 00:47:09 +0000124#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
127#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
128#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
129#define CONFIG_SYS_LOAD_ADDR 0x20000
130#define CONFIG_SYS_MEMTEST_START 0x400
131#define CONFIG_SYS_MEMTEST_END 0x380000
132#define CONFIG_SYS_HZ 1000
133#define CONFIG_SYS_CLK 66000000
wdenkbf9e3b32004-02-12 00:47:09 +0000134
135/*
136 * Low Level Configuration Settings
137 * (address mappings, register initial values, etc.)
138 * You should know what you are doing if you make changes here.
139 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
141#define CONFIG_SYS_SCR 0x0003
142#define CONFIG_SYS_SPR 0xffff
wdenkbf9e3b32004-02-12 00:47:09 +0000143
wdenkbf9e3b32004-02-12 00:47:09 +0000144/*-----------------------------------------------------------------------
145 * Definitions for initial stack pointer and data area (in DPRAM)
146 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200148#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200149#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkbf9e3b32004-02-12 00:47:09 +0000151
152/*-----------------------------------------------------------------------
153 * Start addresses for the final memory configuration
154 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkbf9e3b32004-02-12 00:47:09 +0000156 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_SDRAM_BASE 0x00000000
158#define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
159#define CONFIG_SYS_FLASH_BASE 0xffe00000
wdenkbf9e3b32004-02-12 00:47:09 +0000160
161#ifdef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_MONITOR_BASE 0x20000
wdenkbf9e3b32004-02-12 00:47:09 +0000163#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
wdenkbf9e3b32004-02-12 00:47:09 +0000165#endif
166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_MONITOR_LEN 0x20000
168#define CONFIG_SYS_MALLOC_LEN (256 << 10)
169#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
wdenkbf9e3b32004-02-12 00:47:09 +0000170
171/*
172 * For booting Linux, the board info and command line data
173 * have to be in the first 8 MB of memory, since this is
174 * the maximum mapped by the Linux kernel during initialization ??
175 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
wdenkbf9e3b32004-02-12 00:47:09 +0000177
TsiChung Liewb2028162008-10-21 14:19:26 +0000178/*
wdenkbf9e3b32004-02-12 00:47:09 +0000179 * FLASH organization
180 */
TsiChung Liewb2028162008-10-21 14:19:26 +0000181#define CONFIG_SYS_FLASH_CFI
182#ifdef CONFIG_SYS_FLASH_CFI
183# define CONFIG_FLASH_CFI_DRIVER 1
184# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
185# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
186# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
187# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
188# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
189#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000190
191/*-----------------------------------------------------------------------
192 * Cache Configuration
193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_CACHELINE_SIZE 16
wdenkbf9e3b32004-02-12 00:47:09 +0000195
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600196#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200197 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600198#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200199 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600200#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
201#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
202 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
203 CF_ACR_EN | CF_ACR_SM_ALL)
204#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
205 CF_CACR_DISD | CF_CACR_INVI | \
206 CF_CACR_CEIB | CF_CACR_DCM | \
207 CF_CACR_EUSP)
208
wdenkbf9e3b32004-02-12 00:47:09 +0000209/*-----------------------------------------------------------------------
210 * Memory bank definitions
211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
213#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
214#define CONFIG_SYS_BR1_PRELIM 0
215#define CONFIG_SYS_OR1_PRELIM 0
216#define CONFIG_SYS_BR2_PRELIM 0x30000001
217#define CONFIG_SYS_OR2_PRELIM 0xFFF80000
218#define CONFIG_SYS_BR3_PRELIM 0
219#define CONFIG_SYS_OR3_PRELIM 0
220#define CONFIG_SYS_BR4_PRELIM 0
221#define CONFIG_SYS_OR4_PRELIM 0
222#define CONFIG_SYS_BR5_PRELIM 0
223#define CONFIG_SYS_OR5_PRELIM 0
224#define CONFIG_SYS_BR6_PRELIM 0
225#define CONFIG_SYS_OR6_PRELIM 0
226#define CONFIG_SYS_BR7_PRELIM 0x00000701
227#define CONFIG_SYS_OR7_PRELIM 0xFFC0007C
wdenkbf9e3b32004-02-12 00:47:09 +0000228
229/*-----------------------------------------------------------------------
230 * Port configuration
231 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_PACNT 0x00000000
233#define CONFIG_SYS_PADDR 0x0000
234#define CONFIG_SYS_PADAT 0x0000
235#define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */
236#define CONFIG_SYS_PBDDR 0x0000
237#define CONFIG_SYS_PBDAT 0x0000
238#define CONFIG_SYS_PDCNT 0x00000000
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500239#endif /* _M5272C3_H */