blob: bb3351812e7ecbe64c7142b5f921fa07b6977b04 [file] [log] [blame]
Stefan Roese5e4b3362005-08-22 17:51:53 +02001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese5e4b3362005-08-22 17:51:53 +02006 */
7
8/*************************************************************************
9 * (c) 2005 esd gmbh Hannover
10 *
11 *
12 * from IceCube.h file
13 * by Reinhard Arlt reinhard.arlt@esd-electronics.com
14 *
15 *************************************************************************/
16
17#ifndef __CONFIG_H
18#define __CONFIG_H
19
20/*
21 * High Level Configuration Options
22 * (easy to change)
23 */
24
25#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */
26#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
27#define CONFIG_ICECUBE 1 /* ... on IceCube board */
28#define CONFIG_PF5200 1 /* ... on PF5200 board */
29#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
30
Wolfgang Denk2ae18242010-10-06 09:05:45 +020031#ifndef CONFIG_SYS_TEXT_BASE
32#define CONFIG_SYS_TEXT_BASE 0xFFF00000
33#endif
34
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020035#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
Stefan Roese5e4b3362005-08-22 17:51:53 +020036
Becky Bruce31d82672008-05-08 19:02:12 -050037#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Stefan Roese5e4b3362005-08-22 17:51:53 +020038/*
39 * Serial console configuration
40 */
41#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
42#if 0 /* test-only */
43#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
44#else
45#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
46#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Stefan Roese5e4b3362005-08-22 17:51:53 +020048
Stefan Roese5e4b3362005-08-22 17:51:53 +020049/*
50 * PCI Mapping:
51 * 0x40000000 - 0x4fffffff - PCI Memory
52 * 0x50000000 - 0x50ffffff - PCI IO Space
53 */
54#define CONFIG_PCI 1
55#define CONFIG_PCI_PNP 1
56#define CONFIG_PCI_SCAN_SHOW 1
TsiChung Liewf33fca22008-03-30 01:19:06 -050057#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
Stefan Roese5e4b3362005-08-22 17:51:53 +020058
59#define CONFIG_PCI_MEM_BUS 0x40000000
60#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
61#define CONFIG_PCI_MEM_SIZE 0x10000000
62
63#define CONFIG_PCI_IO_BUS 0x50000000
64#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
65#define CONFIG_PCI_IO_SIZE 0x01000000
66
Marian Balakowicz63ff0042005-10-28 22:30:33 +020067#define CONFIG_MII 1
Stefan Roese5e4b3362005-08-22 17:51:53 +020068#if 0 /* test-only !!! */
Stefan Roese5e4b3362005-08-22 17:51:53 +020069#define CONFIG_EEPRO100 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
Stefan Roese5e4b3362005-08-22 17:51:53 +020071#define CONFIG_NS8382X 1
72#endif
Stefan Roese5e4b3362005-08-22 17:51:53 +020073
74/* Partitions */
75#define CONFIG_MAC_PARTITION
76#define CONFIG_DOS_PARTITION
77
78/* USB */
79#if 0
80#define CONFIG_USB_OHCI
Stefan Roese5e4b3362005-08-22 17:51:53 +020081#define CONFIG_USB_STORAGE
Stefan Roese5e4b3362005-08-22 17:51:53 +020082#endif
83
Stefan Roese5e4b3362005-08-22 17:51:53 +020084
Jon Loeligerd794cfe2007-07-04 22:31:15 -050085/*
Jon Loeliger079a1362007-07-10 10:12:10 -050086 * BOOTP options
87 */
88#define CONFIG_BOOTP_BOOTFILESIZE
89#define CONFIG_BOOTP_BOOTPATH
90#define CONFIG_BOOTP_GATEWAY
91#define CONFIG_BOOTP_HOSTNAME
92
93
94/*
Jon Loeligerd794cfe2007-07-04 22:31:15 -050095 * Command line configuration.
96 */
97#include <config_cmd_default.h>
98
99#define CONFIG_CMD_BSP
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500100#define CONFIG_CMD_EEPROM
101#define CONFIG_CMD_ELF
102#define CONFIG_CMD_FAT
103#define CONFIG_CMD_I2C
104#define CONFIG_CMD_IDE
105
Jon Loeliger079a1362007-07-10 10:12:10 -0500106#define CONFIG_CMD_PCI
Jon Loeliger079a1362007-07-10 10:12:10 -0500107
Stefan Roese5e4b3362005-08-22 17:51:53 +0200108
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200109#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110# define CONFIG_SYS_LOWBOOT 1
111# define CONFIG_SYS_LOWBOOT16 1
Stefan Roese5e4b3362005-08-22 17:51:53 +0200112#endif
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200113#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114# define CONFIG_SYS_LOWBOOT 1
115# define CONFIG_SYS_LOWBOOT08 1
Stefan Roese5e4b3362005-08-22 17:51:53 +0200116#endif
117
118/*
119 * Autobooting
120 */
121#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
122
123#define CONFIG_PREBOOT "echo;" \
124 "echo Welcome to ParaFinder pf5200;" \
125 "echo"
126
127#undef CONFIG_BOOTARGS
128
129#define CONFIG_EXTRA_ENV_SETTINGS \
130 "netdev=eth0\0" \
131 "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
132 "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100133 "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
134 "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
135 "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
Stefan Roese5e4b3362005-08-22 17:51:53 +0200136 "loadaddr=01000000\0" \
137 "serverip=192.168.2.99\0" \
138 "gatewayip=10.0.0.79\0" \
139 "user=mu\0" \
140 "target=pf5200.esd\0" \
141 "script=pf5200.bat\0" \
142 "image=/tftpboot/vxWorks_pf5200\0" \
143 "ipaddr=10.0.13.196\0" \
144 "netmask=255.255.0.0\0" \
145 ""
146
147#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
148
Stefan Roese5e4b3362005-08-22 17:51:53 +0200149/*
150 * IPB Bus clocking configuration.
151 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200153/*
154 * I2C configuration
155 */
156#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */
160#define CONFIG_SYS_I2C_SLAVE 0x7F
Stefan Roese5e4b3362005-08-22 17:51:53 +0200161
162/*
163 * EEPROM configuration
164 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
166#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
167#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
168#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
169#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
Stefan Roese5e4b3362005-08-22 17:51:53 +0200170/*
171 * Flash configuration
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_FLASH_BASE 0xFE000000
174#define CONFIG_SYS_FLASH_SIZE 0x02000000
175#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
176#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
177#define CONFIG_SYS_MAX_FLASH_SECT 512
Stefan Roese5e4b3362005-08-22 17:51:53 +0200178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
180#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200181
182/*
183 * Environment settings
184 */
185#if 1 /* test-only */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200186#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200187#define CONFIG_ENV_SIZE 0x10000
188#define CONFIG_ENV_SECT_SIZE 0x10000
Stefan Roese5e4b3362005-08-22 17:51:53 +0200189#define CONFIG_ENV_OVERWRITE 1
190#else
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200191#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200192#define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
193#define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200194 /* total size of a CAT24WC32 is 8192 bytes */
195#define CONFIG_ENV_OVERWRITE 1
196#endif
197
198/*
199 * Memory map
200 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_MBAR 0xF0000000
202#define CONFIG_SYS_SDRAM_BASE 0x00000000
203#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
Stefan Roese5e4b3362005-08-22 17:51:53 +0200204
205/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200207#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200208
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200209#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roese5e4b3362005-08-22 17:51:53 +0200211
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200212#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
214# define CONFIG_SYS_RAMBOOT 1
Stefan Roese5e4b3362005-08-22 17:51:53 +0200215#endif
216
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
218#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
219#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200220
221/*
222 * Ethernet configuration
223 */
224#define CONFIG_MPC5xxx_FEC 1
Ben Warren86321fc2009-02-05 23:58:25 -0800225#define CONFIG_MPC5xxx_FEC_MII100
Stefan Roese5e4b3362005-08-22 17:51:53 +0200226/*
Ben Warren86321fc2009-02-05 23:58:25 -0800227 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
Stefan Roese5e4b3362005-08-22 17:51:53 +0200228 */
Ben Warren86321fc2009-02-05 23:58:25 -0800229/* #define CONFIG_MPC5xxx_FEC_MII10 */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200230#define CONFIG_PHY_ADDR 0x00
231#define CONFIG_UDP_CHECKSUM 1
232
233/*
234 * GPIO configuration
235 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444
Stefan Roese5e4b3362005-08-22 17:51:53 +0200237
238/*
239 * Miscellaneous configurable options
240 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_LONGHELP /* undef to save memory */
242#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500243#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200245#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200247#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
249#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
250#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200251
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
253#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200254
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200256
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200260
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500262#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500264#endif
265
Stefan Roese5e4b3362005-08-22 17:51:53 +0200266/*
267 * Various low-level settings
268 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
270#define CONFIG_SYS_HID0_FINAL HID0_ICE
Stefan Roese5e4b3362005-08-22 17:51:53 +0200271
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
273#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
274#define CONFIG_SYS_BOOTCS_CFG 0x0004DD00
Stefan Roese5e4b3362005-08-22 17:51:53 +0200275
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
277#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Stefan Roese5e4b3362005-08-22 17:51:53 +0200278
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_CS1_START 0xfd000000
280#define CONFIG_SYS_CS1_SIZE 0x00010000
281#define CONFIG_SYS_CS1_CFG 0x10101410
Stefan Roese5e4b3362005-08-22 17:51:53 +0200282
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_CS_BURST 0x00000000
284#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
Stefan Roese5e4b3362005-08-22 17:51:53 +0200285
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_RESET_ADDRESS 0xff000000
Stefan Roese5e4b3362005-08-22 17:51:53 +0200287
288/*-----------------------------------------------------------------------
289 * USB stuff
290 *-----------------------------------------------------------------------
291 */
292#define CONFIG_USB_CLOCK 0x0001BBBB
293#define CONFIG_USB_CONFIG 0x00001000
294
295/*-----------------------------------------------------------------------
296 * IDE/ATA stuff Supports IDE harddisk
297 *-----------------------------------------------------------------------
298 */
299
300#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
301
302#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
303#undef CONFIG_IDE_LED /* LED for ide not supported */
304
305#define CONFIG_IDE_RESET /* reset for ide supported */
306#define CONFIG_IDE_PREINIT
307
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
309#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200310
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Stefan Roese5e4b3362005-08-22 17:51:53 +0200312
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
Stefan Roese5e4b3362005-08-22 17:51:53 +0200314
315/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
Stefan Roese5e4b3362005-08-22 17:51:53 +0200317
318/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
Stefan Roese5e4b3362005-08-22 17:51:53 +0200320
321/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
Stefan Roese5e4b3362005-08-22 17:51:53 +0200323
324/* Interval between registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_ATA_STRIDE 4
Stefan Roese5e4b3362005-08-22 17:51:53 +0200326
327/*-----------------------------------------------------------------------
328 * CPLD stuff
329 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
331#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200332
333/* CPLD program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */
335#define CONFIG_SYS_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */
336#define CONFIG_SYS_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */
337#define CONFIG_SYS_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200338
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define JTAG_GPIO_ADDR_TMS (CONFIG_SYS_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */
340#define JTAG_GPIO_ADDR_TCK (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */
341#define JTAG_GPIO_ADDR_TDI (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */
342#define JTAG_GPIO_ADDR_TDO (CONFIG_SYS_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */
Stefan Roese5e4b3362005-08-22 17:51:53 +0200343
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define JTAG_GPIO_ADDR_CFG (CONFIG_SYS_MBAR + 0xB00)
Stefan Roese5e4b3362005-08-22 17:51:53 +0200345#define JTAG_GPIO_CFG_SET 0x00000000
346#define JTAG_GPIO_CFG_RESET 0x00F00000
347
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define JTAG_GPIO_ADDR_EN_TMS (CONFIG_SYS_MBAR + 0xB04)
Stefan Roese5e4b3362005-08-22 17:51:53 +0200349#define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */
350#define JTAG_GPIO_TMS_EN_RESET 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define JTAG_GPIO_ADDR_DDR_TMS (CONFIG_SYS_MBAR + 0xB0C)
Stefan Roese5e4b3362005-08-22 17:51:53 +0200352#define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */
353#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
354
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define JTAG_GPIO_ADDR_EN_TCK (CONFIG_SYS_MBAR + 0xC00)
Stefan Roese5e4b3362005-08-22 17:51:53 +0200356#define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */
357#define JTAG_GPIO_TCK_EN_RESET 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define JTAG_GPIO_ADDR_DDR_TCK (CONFIG_SYS_MBAR + 0xC08)
Stefan Roese5e4b3362005-08-22 17:51:53 +0200359#define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */
360#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
361
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define JTAG_GPIO_ADDR_EN_TDI (CONFIG_SYS_MBAR + 0xC00)
Stefan Roese5e4b3362005-08-22 17:51:53 +0200363#define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */
364#define JTAG_GPIO_TDI_EN_RESET 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define JTAG_GPIO_ADDR_DDR_TDI (CONFIG_SYS_MBAR + 0xC08)
Stefan Roese5e4b3362005-08-22 17:51:53 +0200366#define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */
367#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
368
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define JTAG_GPIO_ADDR_EN_TDO (CONFIG_SYS_MBAR + 0xB04)
Stefan Roese5e4b3362005-08-22 17:51:53 +0200370#define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */
371#define JTAG_GPIO_TDO_EN_RESET 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define JTAG_GPIO_ADDR_DDR_TDO (CONFIG_SYS_MBAR + 0xB0C)
Stefan Roese5e4b3362005-08-22 17:51:53 +0200373#define JTAG_GPIO_TDO_DDR_SET 0x00000000
374#define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */
375
376#endif /* __CONFIG_H */