blob: e7186e83990a59bd5e86f279bc84afb3c0c5cbf5 [file] [log] [blame]
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +01001/*
2 * Configuation settings for the Delta board.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __CONFIG_H
24#define __CONFIG_H
25
26/*
27 * High Level Configuration Options
28 * (easy to change)
29 */
30#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
31#define CONFIG_DELTA 1 /* Delta board */
32
33/* #define CONFIG_LCD 1 */
34#ifdef CONFIG_LCD
35#define CONFIG_SHARP_LM8V31
36#endif
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +010037#define BOARD_LATE_INIT 1
38
39#undef CONFIG_SKIP_RELOCATE_UBOOT
40#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
41
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020042/* we will never enable dcache, because we have to setup MMU first */
43#define CONFIG_SYS_NO_DCACHE
44
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +010045/*
46 * Size of malloc() pool
47 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
49#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +010050
51/*
52 * Hardware drivers
53 */
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +010054#undef TURN_ON_ETHERNET
55#ifdef TURN_ON_ETHERNET
56# define CONFIG_DRIVER_SMC91111 1
57# define CONFIG_SMC91111_BASE 0x14000300
58# define CONFIG_SMC91111_EXT_PHY
59# define CONFIG_SMC_USE_32_BIT
60# undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */
61#endif
62
Markus Klotzbuecherba70d6a2006-03-24 12:23:27 +010063#define CONFIG_HARD_I2C 1 /* required for DA9030 access */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
65#define CONFIG_SYS_I2C_SLAVE 1 /* I2C controllers address */
Markus Klotzbuecherba70d6a2006-03-24 12:23:27 +010066#define DA9030_I2C_ADDR 0x49 /* I2C address of DA9030 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_DA9030_EXTON_DELAY 100000 /* wait x us after DA9030 reset via EXTON */
68#define CONFIG_SYS_I2C_INIT_BOARD 1
Markus Klotzbuecherba70d6a2006-03-24 12:23:27 +010069/* #define CONFIG_HW_WATCHDOG 1 /\* Required for hitting the DA9030 WD *\/ */
70
Markus Klotzbuecher71ae4112006-04-25 10:03:01 +020071#define DELTA_CHECK_KEYBD 1 /* check for keys pressed during boot */
72#define CONFIG_PREBOOT "\0"
73
74#ifdef DELTA_CHECK_KEYBD
75# define KEYBD_DATALEN 4 /* we have four keys */
76# define KEYBD_KP_DKIN0 0x1 /* vol+ */
77# define KEYBD_KP_DKIN1 0x2 /* vol- */
78# define KEYBD_KP_DKIN2 0x3 /* multi */
79# define KEYBD_KP_DKIN5 0x4 /* SWKEY_GN */
80#endif /* DELTA_CHECK_KEYBD */
81
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +010082/*
83 * select serial console configuration
84 */
Jean-Christophe PLAGNIOL-VILLARD379be582009-05-16 22:48:46 +020085#define CONFIG_PXA_SERIAL
Markus Klotzbuecher552fc622006-03-20 20:19:37 +010086#define CONFIG_FFUART 1
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +010087
88/* allow to overwrite serial and ethaddr */
89#define CONFIG_ENV_OVERWRITE
90
91#define CONFIG_BAUDRATE 115200
92
Jon Loeligerab999ba2007-07-04 22:32:03 -050093
94/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -050095 * BOOTP options
96 */
97#define CONFIG_BOOTP_BOOTFILESIZE
98#define CONFIG_BOOTP_BOOTPATH
99#define CONFIG_BOOTP_GATEWAY
100#define CONFIG_BOOTP_HOSTNAME
101
102
103/*
Jon Loeligerab999ba2007-07-04 22:32:03 -0500104 * Command line configuration.
105 */
106#include <config_cmd_default.h>
107
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100108#ifdef TURN_ON_ETHERNET
Jon Loeligerab999ba2007-07-04 22:32:03 -0500109
110#define CONFIG_CMD_PING
111
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100112#else
Jon Loeligerab999ba2007-07-04 22:32:03 -0500113
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500114#define CONFIG_CMD_SAVEENV
Jon Loeligerab999ba2007-07-04 22:32:03 -0500115#define CONFIG_CMD_NAND
116#define CONFIG_CMD_I2C
117
118#undef CONFIG_CMD_NET
119#undef CONFIG_CMD_FLASH
120#undef CONFIG_CMD_IMLS
121
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100122#endif
123
Markus Klotzbuecher24e37642006-05-23 10:33:11 +0200124/* USB */
Markus Klotzbuecher7b59b3c2006-11-27 11:44:58 +0100125#define CONFIG_USB_OHCI_NEW 1
Markus Klotzbuecher3e326ec2006-05-22 16:33:54 +0200126#define CONFIG_USB_STORAGE 1
127#define CONFIG_DOS_PARTITION 1
128
Jean-Christophe PLAGNIOL-VILLARDe9d0d522007-10-19 10:55:24 +0200129#include <asm/arch/pxa-regs.h> /* for OHCI_REGS_BASE */
130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
132#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
133#define CONFIG_SYS_USB_OHCI_REGS_BASE OHCI_REGS_BASE
134#define CONFIG_SYS_USB_OHCI_SLOT_NAME "delta"
135#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
Markus Klotzbuecher3e326ec2006-05-22 16:33:54 +0200136
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100137#define CONFIG_BOOTDELAY -1
138#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
139#define CONFIG_NETMASK 255.255.0.0
140#define CONFIG_IPADDR 192.168.0.21
141#define CONFIG_SERVERIP 192.168.0.250
142#define CONFIG_BOOTCOMMAND "bootm 80000"
143#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
144#define CONFIG_CMDLINE_TAG
145#define CONFIG_TIMESTAMP
146
Jon Loeligerab999ba2007-07-04 22:32:03 -0500147#if defined(CONFIG_CMD_KGDB)
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100148#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
149#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
150#endif
151
152/*
153 * Miscellaneous configurable options
154 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_HUSH_PARSER 1
156#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_LONGHELP /* undef to save memory */
159#ifdef CONFIG_SYS_HUSH_PARSER
160#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100161#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100163#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
165#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
166#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
167#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
168#define CONFIG_SYS_DEVICE_NULLDEV 1
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_MEMTEST_START 0x80400000 /* memtest works on */
171#define CONFIG_SYS_MEMTEST_END 0x80800000 /* 4 ... 8 MB in DRAM */
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100174
Micha Kalfon94a33122009-02-11 19:50:11 +0200175#define CONFIG_SYS_HZ 1000
Markus Klotzbuecher40b0baf2006-03-24 14:35:25 +0100176
Markus Klotzbuecherc855ef62006-03-27 16:01:03 +0200177/* Monahans Core Frequency */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
179#define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */
Markus Klotzbuecher40b0baf2006-03-24 14:35:25 +0100180
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100181
182 /* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100184
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100185#ifdef CONFIG_MMC
186#define CONFIG_PXA_MMC
187#define CONFIG_CMD_MMC
188#define CONFIG_SYS_MMC_BASE 0xF0000000
189#endif
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100190
191/*
192 * Stack sizes
193 *
194 * The stack sizes are set up in start.S using the settings below
195 */
196#define CONFIG_STACKSIZE (128*1024) /* regular stack */
197#ifdef CONFIG_USE_IRQ
198#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
199#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
200#endif
201
202/*
203 * Physical Memory Map
204 */
205#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
Markus Klotzbuechereeaab722006-03-29 17:59:20 +0200206#define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */
Markus Klotzbücher599f5222006-02-22 17:48:43 +0100207#define PHYS_SDRAM_1_SIZE 0x1000000 /* 64 MB */
Markus Klotzbuechereeaab722006-03-29 17:59:20 +0200208#define PHYS_SDRAM_2 0x81000000 /* SDRAM Bank #2 */
Markus Klotzbücher599f5222006-02-22 17:48:43 +0100209#define PHYS_SDRAM_2_SIZE 0x1000000 /* 64 MB */
Markus Klotzbuechereeaab722006-03-29 17:59:20 +0200210#define PHYS_SDRAM_3 0x82000000 /* SDRAM Bank #3 */
Markus Klotzbücher599f5222006-02-22 17:48:43 +0100211#define PHYS_SDRAM_3_SIZE 0x1000000 /* 64 MB */
Markus Klotzbuechereeaab722006-03-29 17:59:20 +0200212#define PHYS_SDRAM_4 0x83000000 /* SDRAM Bank #4 */
Markus Klotzbücher599f5222006-02-22 17:48:43 +0100213#define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_DRAM_BASE 0x80000000 /* at CS0 */
216#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB Ram */
Markus Klotzbücherff3c2a92006-02-22 14:05:44 +0100217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#undef CONFIG_SYS_SKIP_DRAM_SCRUB
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100219
Markus Klotzbücher69493282006-02-28 18:05:25 +0100220/*
221 * NAND Flash
222 */
Jean-Christophe PLAGNIOL-VILLARDcc4a0ce2008-08-13 01:40:43 +0200223#undef CONFIG_NAND_LEGACY
Marian Balakowicz6db39702006-04-08 19:08:06 +0200224
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */
226#undef CONFIG_SYS_NAND1_BASE
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100227
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
229#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Markus Klotzbücher69493282006-02-28 18:05:25 +0100230
Wolfgang Denk951a9542006-03-06 23:18:48 +0100231/* nand timeout values */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_NAND_PROG_ERASE_TO 3000
233#define CONFIG_SYS_NAND_OTHER_TO 100
234#define CONFIG_SYS_NAND_SENDCMD_RETRY 3
Markus Klotzbücher43638c62006-03-06 15:04:25 +0100235#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
236
237/* NAND Timing Parameters (in ns) */
Markus Klotzbuecher552fc622006-03-20 20:19:37 +0100238#define NAND_TIMING_tCH 10
239#define NAND_TIMING_tCS 0
Markus Klotzbücher43638c62006-03-06 15:04:25 +0100240#define NAND_TIMING_tWH 20
Markus Klotzbuecher552fc622006-03-20 20:19:37 +0100241#define NAND_TIMING_tWP 40
Markus Klotzbücher43638c62006-03-06 15:04:25 +0100242
Markus Klotzbuecher552fc622006-03-20 20:19:37 +0100243#define NAND_TIMING_tRH 20
244#define NAND_TIMING_tRP 40
Markus Klotzbücher43638c62006-03-06 15:04:25 +0100245
Markus Klotzbuecher552fc622006-03-20 20:19:37 +0100246#define NAND_TIMING_tR 11123
Markus Klotzbücher43638c62006-03-06 15:04:25 +0100247#define NAND_TIMING_tWHR 100
248#define NAND_TIMING_tAR 10
249
250/* NAND debugging */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_DFC_DEBUG1 /* usefull */
252#undef CONFIG_SYS_DFC_DEBUG2 /* noisy */
253#undef CONFIG_SYS_DFC_DEBUG3 /* extremly noisy */
Markus Klotzbücherf9e02912006-03-06 13:45:42 +0100254
255#define CONFIG_MTD_DEBUG
256#define CONFIG_MTD_DEBUG_VERBOSE 1
Markus Klotzbücherbf7cac02006-03-04 18:35:51 +0100257
Markus Klotzbuecher552fc622006-03-20 20:19:37 +0100258#define ADDR_COLUMN 1
259#define ADDR_PAGE 2
260#define ADDR_COLUMN_PAGE 3
Markus Klotzbücher69493282006-02-28 18:05:25 +0100261
262#define NAND_ChipID_UNKNOWN 0x00
Markus Klotzbuecher552fc622006-03-20 20:19:37 +0100263#define NAND_MAX_FLOORS 1
Markus Klotzbücher69493282006-02-28 18:05:25 +0100264
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_NO_FLASH 1
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100266
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200267#define CONFIG_ENV_IS_IN_NAND 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200268#define CONFIG_ENV_OFFSET 0x40000
269#define CONFIG_ENV_OFFSET_REDUND 0x44000
270#define CONFIG_ENV_SIZE 0x4000
Markus Klotzbücher4f7a0e32006-02-20 16:37:37 +0100271
272#endif /* __CONFIG_H */