blob: 013c7cfc59ce856c2c714501ada84f6edf64efaa [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Bo Shenf7fa2f32012-07-05 17:21:46 +00002/*
3 * Copyright (C) 2012 Atmel Corporation
4 *
5 * Configuation settings for the AT91SAM9X5EK board.
Bo Shenf7fa2f32012-07-05 17:21:46 +00006 */
7
8#ifndef __CONFIG_H__
9#define __CONFIG_H__
10
Bo Shenf7fa2f32012-07-05 17:21:46 +000011/* ARM asynchronous clock */
12#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
13#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
Bo Shenf7fa2f32012-07-05 17:21:46 +000014
Bo Shenf7fa2f32012-07-05 17:21:46 +000015/* general purpose I/O */
Bo Shenf7fa2f32012-07-05 17:21:46 +000016
Bo Shenf7fa2f32012-07-05 17:21:46 +000017/*
Tom Rini8850c5d2017-05-12 22:33:27 -040018 * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
Richard Genoudb030e732012-11-29 23:18:34 +000019 * NB: in this case, USB 1.1 devices won't be recognized.
20 */
21
Bo Shenf7fa2f32012-07-05 17:21:46 +000022/* SDRAM */
Bo Shenf7fa2f32012-07-05 17:21:46 +000023#define CONFIG_SYS_SDRAM_BASE 0x20000000
24#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
25
26#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou Yang74631b62017-04-18 14:51:54 +080027 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Bo Shenf7fa2f32012-07-05 17:21:46 +000028
29/* DataFlash */
Bo Shenf7fa2f32012-07-05 17:21:46 +000030
Bo Shenf7fa2f32012-07-05 17:21:46 +000031/* NAND flash */
32#ifdef CONFIG_CMD_NAND
Bo Shenf7fa2f32012-07-05 17:21:46 +000033#define CONFIG_SYS_MAX_NAND_DEVICE 1
34#define CONFIG_SYS_NAND_BASE 0x40000000
35#define CONFIG_SYS_NAND_DBW_8 1
36/* our ALE is AD21 */
37#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
38/* our CLE is AD22 */
39#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
40#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
41#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
Tom Rini8f1a80e2017-07-28 21:31:42 -040042#endif
43
Richard Genoudb030e732012-11-29 23:18:34 +000044/* USB */
45#ifdef CONFIG_CMD_USB
Tom Rini8850c5d2017-05-12 22:33:27 -040046#ifndef CONFIG_USB_EHCI_HCD
Bo Shendcd2f1a2013-10-21 16:14:00 +080047#define CONFIG_USB_ATMEL
48#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
Richard Genoudb030e732012-11-29 23:18:34 +000049#define CONFIG_USB_OHCI_NEW
50#define CONFIG_SYS_USB_OHCI_CPU_INIT
51#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
52#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5"
53#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
54#endif
Richard Genoudb030e732012-11-29 23:18:34 +000055#endif
56
Bo Shend85e8912015-03-27 14:23:35 +080057/* SPL */
Bo Shend85e8912015-03-27 14:23:35 +080058#define CONFIG_SPL_MAX_SIZE 0x6000
59#define CONFIG_SPL_STACK 0x308000
60
61#define CONFIG_SPL_BSS_START_ADDR 0x20000000
62#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
63#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
64#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
65
Bo Shend85e8912015-03-27 14:23:35 +080066#define CONFIG_SYS_MONITOR_LEN (512 << 10)
67
68#define CONFIG_SYS_MASTER_CLOCK 132096000
69#define CONFIG_SYS_AT91_PLLA 0x20c73f03
70#define CONFIG_SYS_MCKR 0x1301
71#define CONFIG_SYS_MCKR_CSS 0x1302
72
Wenyou Yang55415432017-09-14 11:07:44 +080073#ifdef CONFIG_SD_BOOT
Bo Shend85e8912015-03-27 14:23:35 +080074#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Wenyou Yang55415432017-09-14 11:07:44 +080075#endif
Bo Shend85e8912015-03-27 14:23:35 +080076
Bo Shenf7fa2f32012-07-05 17:21:46 +000077#endif