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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +01002/*
3 * Copyright (C) 2016, Imagination Technologies Ltd.
4 *
5 * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
6 *
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +01007 * Imagination Technologies Ltd. MIPSfpga
8 */
9
10#ifndef __XILFPGA_CONFIG_H
11#define __XILFPGA_CONFIG_H
12
13/* BootROM + MIG is pretty smart. DDR and Cache initialized */
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +010014
15/*--------------------------------------------
16 * CPU configuration
17 */
18/* CPU Timer rate */
19#define CONFIG_SYS_MIPS_TIMER_FREQ 50000000
20
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +010021/*----------------------------------------------------------------------
22 * Memory Layout
23 */
24
25/* SDRAM Configuration (for final code, data, stack, heap) */
26#define CONFIG_SYS_SDRAM_BASE 0x80000000
27#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */
28#define CONFIG_SYS_INIT_SP_ADDR \
29 (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000)
30
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +010031/*----------------------------------------------------------------------
32 * Commands
33 */
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +010034
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +010035/*------------------------------------------------------------
36 * Console Configuration
37 */
38#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +010039
40/* -------------------------------------------------
41 * Environment
42 */
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +010043
44/* ---------------------------------------------------------------------
45 * Board boot configuration
46 */
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +010047
48#endif /* __XILFPGA_CONFIG_H */