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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +09002/*
3 * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
4 * Copyright (C) 2012 Renesas Solutions Corp.
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +09005 */
6
7#ifndef __KZM9G_H
8#define __KZM9G_H
9
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090010#define CONFIG_SH73A0
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090011
12#include <asm/arch/rmobile.h>
13
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090014/* MEMORY */
15#define KZM_SDRAM_BASE (0x40000000)
16#define PHYS_SDRAM KZM_SDRAM_BASE
17#define PHYS_SDRAM_SIZE (512 * 1024 * 1024)
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090018
19/* NOR Flash */
20#define KZM_FLASH_BASE (0x00000000)
21#define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE)
22#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090023#define CONFIG_SYS_MAX_FLASH_SECT (512)
24
25/* prompt */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090026#define CONFIG_SYS_PBSIZE 256
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090027#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
28
29/* SCIF */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090030#define CONFIG_CONS_SCIF4
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090031
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090032#undef CONFIG_SYS_LOADS_BAUD_CHANGE
33
34#define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */
35#define CONFIG_SYS_INIT_RAM_SIZE (0x10000)
36#define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4)
37#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
38 CONFIG_SYS_INIT_RAM_SIZE - \
39 GENERATED_GBL_DATA_SIZE)
Tetsuyuki Kobayashi9415cf92012-07-05 01:43:44 +000040#define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024)
41#define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT)
42#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT)
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090043
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090044#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
45
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090046#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000
47
48/* FLASH */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090049#undef CONFIG_SYS_FLASH_QUIET_TEST
50#define CONFIG_SYS_FLASH_EMPTY_INFO
51#define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090052
53/* Timeout for Flash erase operations (in ms) */
54#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
55/* Timeout for Flash write operations (in ms) */
56#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
57/* Timeout for Flash set sector lock bit operations (in ms) */
58#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
59/* Timeout for Flash clear lock bit operations (in ms) */
60#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
61
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090062#undef CONFIG_SYS_DIRECT_FLASH_TFTP
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090063
64/* GPIO / PFC */
65#define CONFIG_SH_GPIO_PFC
66
67/* Clock */
Nobuhiro Iwamatsueae6c8a2012-08-03 13:56:52 +090068#define CONFIG_GLOBAL_TIMER
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090069#define CONFIG_SYS_CPU_CLK (1196000000)
Tom Rini2f8a6db2021-12-14 13:36:40 -050070#define CONFIG_SH_SCIF_CLK_FREQ get_board_sys_clk()
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090071#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090072
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090073#endif /* __KZM9G_H */