wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001, 2002, 2003 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * Keith Outwater, keith_outwater@mvis.com` |
| 5 | * Steven Scholz, steven.scholz@imc-berlin.de |
| 6 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | /* |
| 11 | * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim) |
wdenk | 7f70e85 | 2003-05-20 14:25:27 +0000 | [diff] [blame] | 12 | * DS1307 and DS1338 Real Time Clock (RTC). |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 13 | * |
| 14 | * based on ds1337.c |
| 15 | */ |
| 16 | |
| 17 | #include <common.h> |
| 18 | #include <command.h> |
| 19 | #include <rtc.h> |
| 20 | #include <i2c.h> |
| 21 | |
Michal Simek | 871c18d | 2008-07-14 19:45:37 +0200 | [diff] [blame] | 22 | #if defined(CONFIG_CMD_DATE) |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 23 | |
| 24 | /*---------------------------------------------------------------------*/ |
| 25 | #undef DEBUG_RTC |
| 26 | |
| 27 | #ifdef DEBUG_RTC |
| 28 | #define DEBUGR(fmt,args...) printf(fmt ,##args) |
| 29 | #else |
| 30 | #define DEBUGR(fmt,args...) |
| 31 | #endif |
| 32 | /*---------------------------------------------------------------------*/ |
| 33 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 34 | #ifndef CONFIG_SYS_I2C_RTC_ADDR |
| 35 | # define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 36 | #endif |
| 37 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 38 | #if defined(CONFIG_RTC_DS1307) && (CONFIG_SYS_I2C_SPEED > 100000) |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 39 | # error The DS1307 is specified only up to 100kHz! |
| 40 | #endif |
| 41 | |
| 42 | /* |
| 43 | * RTC register addresses |
| 44 | */ |
| 45 | #define RTC_SEC_REG_ADDR 0x00 |
| 46 | #define RTC_MIN_REG_ADDR 0x01 |
| 47 | #define RTC_HR_REG_ADDR 0x02 |
| 48 | #define RTC_DAY_REG_ADDR 0x03 |
| 49 | #define RTC_DATE_REG_ADDR 0x04 |
| 50 | #define RTC_MON_REG_ADDR 0x05 |
| 51 | #define RTC_YR_REG_ADDR 0x06 |
| 52 | #define RTC_CTL_REG_ADDR 0x07 |
| 53 | |
| 54 | #define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */ |
| 55 | |
| 56 | #define RTC_CTL_BIT_RS0 0x01 /* Rate select 0 */ |
| 57 | #define RTC_CTL_BIT_RS1 0x02 /* Rate select 1 */ |
| 58 | #define RTC_CTL_BIT_SQWE 0x10 /* Square Wave Enable */ |
| 59 | #define RTC_CTL_BIT_OUT 0x80 /* Output Control */ |
| 60 | |
| 61 | static uchar rtc_read (uchar reg); |
| 62 | static void rtc_write (uchar reg, uchar val); |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 63 | |
| 64 | /* |
| 65 | * Get the current time from the RTC |
| 66 | */ |
Yuri Tikhonov | b73a19e | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 67 | int rtc_get (struct rtc_time *tmp) |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 68 | { |
Yuri Tikhonov | b73a19e | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 69 | int rel = 0; |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 70 | uchar sec, min, hour, mday, wday, mon, year; |
| 71 | |
| 72 | sec = rtc_read (RTC_SEC_REG_ADDR); |
| 73 | min = rtc_read (RTC_MIN_REG_ADDR); |
| 74 | hour = rtc_read (RTC_HR_REG_ADDR); |
| 75 | wday = rtc_read (RTC_DAY_REG_ADDR); |
| 76 | mday = rtc_read (RTC_DATE_REG_ADDR); |
| 77 | mon = rtc_read (RTC_MON_REG_ADDR); |
| 78 | year = rtc_read (RTC_YR_REG_ADDR); |
| 79 | |
| 80 | DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " |
| 81 | "hr: %02x min: %02x sec: %02x\n", |
| 82 | year, mon, mday, wday, hour, min, sec); |
| 83 | |
| 84 | if (sec & RTC_SEC_BIT_CH) { |
| 85 | printf ("### Warning: RTC oscillator has stopped\n"); |
| 86 | /* clear the CH flag */ |
| 87 | rtc_write (RTC_SEC_REG_ADDR, |
| 88 | rtc_read (RTC_SEC_REG_ADDR) & ~RTC_SEC_BIT_CH); |
Yuri Tikhonov | b73a19e | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 89 | rel = -1; |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 90 | } |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 91 | |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 92 | tmp->tm_sec = bcd2bin (sec & 0x7F); |
| 93 | tmp->tm_min = bcd2bin (min & 0x7F); |
| 94 | tmp->tm_hour = bcd2bin (hour & 0x3F); |
| 95 | tmp->tm_mday = bcd2bin (mday & 0x3F); |
| 96 | tmp->tm_mon = bcd2bin (mon & 0x1F); |
| 97 | tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000); |
| 98 | tmp->tm_wday = bcd2bin ((wday - 1) & 0x07); |
| 99 | tmp->tm_yday = 0; |
| 100 | tmp->tm_isdst= 0; |
| 101 | |
| 102 | DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
| 103 | tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, |
| 104 | tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
Yuri Tikhonov | b73a19e | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 105 | |
| 106 | return rel; |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 107 | } |
| 108 | |
| 109 | |
| 110 | /* |
| 111 | * Set the RTC |
| 112 | */ |
Jean-Christophe PLAGNIOL-VILLARD | d1e2319 | 2008-09-01 23:06:23 +0200 | [diff] [blame] | 113 | int rtc_set (struct rtc_time *tmp) |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 114 | { |
| 115 | DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
| 116 | tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, |
| 117 | tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
| 118 | |
| 119 | if (tmp->tm_year < 1970 || tmp->tm_year > 2069) |
| 120 | printf("WARNING: year should be between 1970 and 2069!\n"); |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 121 | |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 122 | rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); |
| 123 | rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon)); |
| 124 | rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1)); |
| 125 | rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); |
| 126 | rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour)); |
| 127 | rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); |
| 128 | rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); |
Jean-Christophe PLAGNIOL-VILLARD | d1e2319 | 2008-09-01 23:06:23 +0200 | [diff] [blame] | 129 | |
| 130 | return 0; |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 131 | } |
| 132 | |
| 133 | |
| 134 | /* |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 135 | * Reset the RTC. We setting the date back to 1970-01-01. |
| 136 | * We also enable the oscillator output on the SQW/OUT pin and program |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 137 | * it for 32,768 Hz output. Note that according to the datasheet, turning |
| 138 | * on the square wave output increases the current drain on the backup |
| 139 | * battery to something between 480nA and 800nA. |
| 140 | */ |
| 141 | void rtc_reset (void) |
| 142 | { |
| 143 | struct rtc_time tmp; |
| 144 | |
| 145 | rtc_write (RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */ |
| 146 | rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS0); |
| 147 | |
| 148 | tmp.tm_year = 1970; |
| 149 | tmp.tm_mon = 1; |
| 150 | tmp.tm_mday= 1; |
| 151 | tmp.tm_hour = 0; |
| 152 | tmp.tm_min = 0; |
| 153 | tmp.tm_sec = 0; |
| 154 | |
| 155 | rtc_set(&tmp); |
| 156 | |
| 157 | printf ( "RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n", |
| 158 | tmp.tm_year, tmp.tm_mon, tmp.tm_mday, |
| 159 | tmp.tm_hour, tmp.tm_min, tmp.tm_sec); |
| 160 | |
| 161 | return; |
| 162 | } |
| 163 | |
| 164 | |
| 165 | /* |
| 166 | * Helper functions |
| 167 | */ |
| 168 | |
| 169 | static |
| 170 | uchar rtc_read (uchar reg) |
| 171 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 172 | return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 173 | } |
| 174 | |
| 175 | |
| 176 | static void rtc_write (uchar reg, uchar val) |
| 177 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 178 | i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 179 | } |
Jon Loeliger | 068b60a | 2007-07-10 10:27:39 -0500 | [diff] [blame] | 180 | #endif |