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Magnus Lilja8449f282009-07-01 01:07:55 +02001/*
2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
3 *
4 * (C) Copyright 2004
5 * Texas Instruments.
6 * Richard Woodruff <r-woodruff2@ti.com>
7 * Kshitij Gupta <kshitij@ti.com>
8 *
9 * Configuration settings for the Freescale i.MX31 PDK board.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
Magnus Lilja38a8b3e2010-01-17 17:46:11 +010033#include <asm/arch/mx31-regs.h>
34
Magnus Lilja8449f282009-07-01 01:07:55 +020035/* High Level Configuration Options */
36#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
37#define CONFIG_MX31 1 /* in a mx31 */
38#define CONFIG_MX31_HCLK_FREQ 26000000
39#define CONFIG_MX31_CLK32 32768
40
41#define CONFIG_DISPLAY_CPUINFO
42#define CONFIG_DISPLAY_BOARDINFO
43
44#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
45#define CONFIG_SETUP_MEMORY_TAGS 1
46#define CONFIG_INITRD_TAG 1
47
Magnus Liljad08e5ca2009-07-04 10:31:24 +020048#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
Magnus Lilja8449f282009-07-01 01:07:55 +020049#define CONFIG_SKIP_LOWLEVEL_INIT
Magnus Liljad08e5ca2009-07-04 10:31:24 +020050#define CONFIG_SKIP_RELOCATE_UBOOT
51#endif
Magnus Lilja8449f282009-07-01 01:07:55 +020052
53/*
54 * Size of malloc() pool
55 */
Magnus Lilja38a8b3e2010-01-17 17:46:11 +010056#define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
Magnus Lilja8449f282009-07-01 01:07:55 +020057/* Bytes reserved for initial data */
58#define CONFIG_SYS_GBL_DATA_SIZE 128
59
60/*
61 * Hardware drivers
62 */
63
64#define CONFIG_MXC_UART 1
65#define CONFIG_SYS_MX31_UART1 1
66
67#define CONFIG_HARD_SPI 1
68#define CONFIG_MXC_SPI 1
69#define CONFIG_DEFAULT_SPI_BUS 1
70#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH)
71
72#define CONFIG_RTC_MC13783 1
73
74/* MC13783 connected to CSPI2 and SS2 */
75#define CONFIG_MC13783_SPI_BUS 1
76#define CONFIG_MC13783_SPI_CS 2
77
78/* allow to overwrite serial and ethaddr */
79#define CONFIG_ENV_OVERWRITE
80#define CONFIG_CONS_INDEX 1
81#define CONFIG_BAUDRATE 115200
82#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
83
84/***********************************************************
85 * Command definition
86 ***********************************************************/
87
88#include <config_cmd_default.h>
89
90#define CONFIG_CMD_MII
91#define CONFIG_CMD_PING
92#define CONFIG_CMD_SPI
93#define CONFIG_CMD_DATE
Magnus Lilja38a8b3e2010-01-17 17:46:11 +010094#define CONFIG_CMD_NAND
Magnus Lilja8449f282009-07-01 01:07:55 +020095
96/*
97 * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
98 * that CFG_NO_FLASH is undefined).
99 */
100#undef CONFIG_CMD_IMLS
101
102#define CONFIG_BOOTDELAY 3
103
104#define CONFIG_EXTRA_ENV_SETTINGS \
105 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
106 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
107 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
108 "bootcmd=run bootcmd_net\0" \
109 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
Magnus Lilja38a8b3e2010-01-17 17:46:11 +0100110 "tftpboot 0x81000000 uImage-mx31; bootm\0" \
111 "prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; " \
112 "nand erase 0x0 0x40000; " \
113 "nand write 0x81000000 0x0 0x40000\0"
Magnus Lilja8449f282009-07-01 01:07:55 +0200114
Ben Warren736fead2009-07-20 22:01:11 -0700115#define CONFIG_NET_MULTI
116#define CONFIG_SMC911X 1
117#define CONFIG_SMC911X_BASE 0xB6000000
118#define CONFIG_SMC911X_32_BIT 1
Magnus Lilja8449f282009-07-01 01:07:55 +0200119
120/*
121 * Miscellaneous configurable options
122 */
123#define CONFIG_SYS_LONGHELP /* undef to save memory */
124#define CONFIG_SYS_PROMPT "uboot> "
125#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
126/* Print Buffer Size */
127#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
128 sizeof(CONFIG_SYS_PROMPT)+16)
129/* max number of command args */
130#define CONFIG_SYS_MAXARGS 16
131/* Boot Argument Buffer Size */
132#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
133
134/* memtest works on */
135#define CONFIG_SYS_MEMTEST_START 0x80000000
136#define CONFIG_SYS_MEMTEST_END 0x10000
137
138/* default load address */
139#define CONFIG_SYS_LOAD_ADDR 0x81000000
140
141#define CONFIG_SYS_HZ 1000
142
143#define CONFIG_CMDLINE_EDITING 1
144
145/*-----------------------------------------------------------------------
146 * Stack sizes
147 *
148 * The stack sizes are set up in start.S using the settings below
149 */
150#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
151
152/*-----------------------------------------------------------------------
153 * Physical Memory Map
154 */
155#define CONFIG_NR_DRAM_BANKS 1
156#define PHYS_SDRAM_1 CSD0_BASE
157#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
158
159/*-----------------------------------------------------------------------
160 * FLASH and environment organization
161 */
162/* No NOR flash present */
163#define CONFIG_SYS_NO_FLASH 1
164
Magnus Lilja38a8b3e2010-01-17 17:46:11 +0100165#define CONFIG_ENV_IS_IN_NAND 1
166#define CONFIG_ENV_OFFSET 0x40000
167#define CONFIG_ENV_OFFSET_REDUND 0x60000
168#define CONFIG_ENV_SIZE (128 * 1024)
Magnus Lilja8449f282009-07-01 01:07:55 +0200169
Magnus Lilja38a8b3e2010-01-17 17:46:11 +0100170/*
171 * NAND driver
172 */
173#define CONFIG_NAND_MXC
174#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
175#define CONFIG_SYS_MAX_NAND_DEVICE 1
176#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
177#define CONFIG_MXC_NAND_HWECC
178#define CONFIG_SYS_NAND_LARGEPAGE
Magnus Lilja8449f282009-07-01 01:07:55 +0200179
Magnus Liljad08e5ca2009-07-04 10:31:24 +0200180/* NAND configuration for the NAND_SPL */
181
182/* Start copying real U-boot from the second page */
183#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
184#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000
185/* Load U-Boot to this address */
186#define CONFIG_SYS_NAND_U_BOOT_DST 0x87f00000
187#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
188
189#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
190#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
191#define CONFIG_SYS_NAND_PAGE_COUNT 64
192#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
193#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
194
195
196/* Configuration of lowlevel_init.S (clocks and SDRAM) */
197#define CCM_CCMR_SETUP 0x074B0BF5
198#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
199 PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \
200 PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \
201 PDR0_MCU_PODF(0))
202#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
203 PLL_MFN(12))
204
205#define ESDMISC_MDDR_SETUP 0x00000004
206#define ESDMISC_MDDR_RESET_DL 0x0000000c
207#define ESDCFG0_MDDR_SETUP 0x006ac73a
208
209#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
210#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
211 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
212#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
213#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
214#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
215#define ESDCTL_RW ESDCTL_SETTINGS
216
Magnus Lilja8449f282009-07-01 01:07:55 +0200217#endif /* __CONFIG_H */