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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Lucile Quirion9ee16892015-06-30 17:17:47 -04002/*
3 * Copyright (C) 2015, Savoir-faire Linux Inc.
4 *
5 * Derived from MX51EVK code by
6 * Guennadi Liakhovetski <lg@denx.de>
7 * Freescale Semiconductor, Inc.
8 *
9 * Configuration settings for the TS4800 Board
Lucile Quirion9ee16892015-06-30 17:17:47 -040010 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/* High Level Configuration Options */
Lucile Quirion9ee16892015-06-30 17:17:47 -040016
Bin Menga1875592016-02-05 19:30:11 -080017#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage bootloader */
Lucile Quirion9ee16892015-06-30 17:17:47 -040018
19#define CONFIG_HW_WATCHDOG
20
Tom Rini94ba26f2017-01-25 20:42:35 -050021#define CONFIG_MACH_TYPE MACH_TYPE_TS48XX
22
Lucile Quirion9ee16892015-06-30 17:17:47 -040023/* text base address used when linking */
Lucile Quirion9ee16892015-06-30 17:17:47 -040024
25#include <asm/arch/imx-regs.h>
26
27/* enable passing of ATAGs */
28#define CONFIG_CMDLINE_TAG
29#define CONFIG_SETUP_MEMORY_TAGS
30#define CONFIG_INITRD_TAG
31#define CONFIG_REVISION_TAG
32
Lucile Quirion9ee16892015-06-30 17:17:47 -040033/*
34 * Size of malloc() pool
35 */
36#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
37
38/*
39 * Hardware drivers
40 */
41
Lucile Quirion9ee16892015-06-30 17:17:47 -040042#define CONFIG_MXC_UART_BASE UART1_BASE
Lucile Quirion9ee16892015-06-30 17:17:47 -040043
44/*
Lucile Quirion9ee16892015-06-30 17:17:47 -040045 * MMC Configs
46 * */
Lucile Quirion9ee16892015-06-30 17:17:47 -040047#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
48
Damien Riegelf3488bb2015-06-30 17:17:48 -040049/*
50 * Eth Configs
51 */
Damien Riegelf3488bb2015-06-30 17:17:48 -040052
53#define CONFIG_FEC_MXC
54#define IMX_FEC_BASE FEC_BASE_ADDR
55#define CONFIG_ETHPRIME "FEC"
56#define CONFIG_FEC_MXC_PHYADDR 0
57
Lucile Quirion9ee16892015-06-30 17:17:47 -040058/***********************************************************
59 * Command definition
60 ***********************************************************/
61
Lucile Quirion9ee16892015-06-30 17:17:47 -040062/* Environment variables */
63
Lucile Quirion9ee16892015-06-30 17:17:47 -040064
65#define CONFIG_LOADADDR 0x91000000 /* loadaddr env var */
66
67#define CONFIG_EXTRA_ENV_SETTINGS \
68 "script=boot.scr\0" \
Damien Riegele4537942016-04-21 17:34:02 -040069 "image=zImage\0" \
70 "fdt_file=imx51-ts4800.dtb\0" \
71 "fdt_addr=0x90fe0000\0" \
Lucile Quirion9ee16892015-06-30 17:17:47 -040072 "mmcdev=0\0" \
Damien Riegele4537942016-04-21 17:34:02 -040073 "mmcpart=2\0" \
74 "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
75 "mmcargs=setenv bootargs root=${mmcroot}\0" \
Lucile Quirion9ee16892015-06-30 17:17:47 -040076 "addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \
77 "loadbootscript=" \
78 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
79 "bootscript=echo Running bootscript from mmc ...; " \
80 "source\0" \
81 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \
Damien Riegele4537942016-04-21 17:34:02 -040082 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
Lucile Quirion9ee16892015-06-30 17:17:47 -040083 "mmcboot=echo Booting from mmc ...; " \
84 "run mmcargs addtty; " \
Damien Riegele4537942016-04-21 17:34:02 -040085 "if run loadfdt; then " \
86 "bootz ${loadaddr} - ${fdt_addr}; " \
87 "else " \
88 "echo ERR: cannot load FDT; " \
89 "fi; "
90
Lucile Quirion9ee16892015-06-30 17:17:47 -040091
92#define CONFIG_BOOTCOMMAND \
93 "mmc dev ${mmcdev}; if mmc rescan; then " \
94 "if run loadbootscript; then " \
95 "run bootscript; " \
96 "else " \
97 "if run loadimage; then " \
98 "run mmcboot; " \
99 "fi; " \
100 "fi; " \
101 "fi; "
102
103/*
104 * Miscellaneous configurable options
105 */
Lucile Quirion9ee16892015-06-30 17:17:47 -0400106
107#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
108
Lucile Quirion9ee16892015-06-30 17:17:47 -0400109/*-----------------------------------------------------------------------
110 * Physical Memory Map
111 */
Lucile Quirion9ee16892015-06-30 17:17:47 -0400112#define PHYS_SDRAM_1 CSD0_BASE_ADDR
113#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
114
115#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
116#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
117#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
118
Lucile Quirion9ee16892015-06-30 17:17:47 -0400119#define CONFIG_SYS_INIT_SP_OFFSET \
120 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
121#define CONFIG_SYS_INIT_SP_ADDR \
122 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
123
124/* Low level init */
125#define CONFIG_SYS_DDR_CLKSEL 0
126#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
127#define CONFIG_SYS_MAIN_PWR_ON
128
129/*-----------------------------------------------------------------------
130 * Environment organization
131 */
132
Lucile Quirion9ee16892015-06-30 17:17:47 -0400133#endif