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Wolfgang Denkad5bb452007-03-06 18:08:43 +01001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denkad5bb452007-03-06 18:08:43 +01006 */
7
8#include <common.h>
9
10/*
11 * CPU test
12 * Shift instructions: srawi
13 *
14 * The test contains a pre-built table of instructions, operands and
15 * expected results. For each table entry, the test will cyclically use
16 * different sets of operand registers and result registers.
17 */
18
Wolfgang Denkad5bb452007-03-06 18:08:43 +010019#include <post.h>
20#include "cpu_asm.h"
21
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020022#if CONFIG_POST & CONFIG_SYS_POST_CPU
Wolfgang Denkad5bb452007-03-06 18:08:43 +010023
24extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
25extern ulong cpu_post_makecr (long v);
26
27static struct cpu_post_srawi_s
28{
29 ulong cmd;
30 ulong op1;
31 uchar op2;
32 ulong res;
33} cpu_post_srawi_table[] =
34{
35 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +020036 OP_SRAWI,
Wolfgang Denkad5bb452007-03-06 18:08:43 +010037 0x8000,
38 3,
39 0x1000
40 },
41 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +020042 OP_SRAWI,
Wolfgang Denkad5bb452007-03-06 18:08:43 +010043 0x80000000,
44 3,
45 0xf0000000
46 },
47};
Mike Frysingerd2397812011-05-10 07:28:35 +000048static unsigned int cpu_post_srawi_size = ARRAY_SIZE(cpu_post_srawi_table);
Wolfgang Denkad5bb452007-03-06 18:08:43 +010049
50int cpu_post_test_srawi (void)
51{
52 int ret = 0;
53 unsigned int i, reg;
54 int flag = disable_interrupts();
55
56 for (i = 0; i < cpu_post_srawi_size && ret == 0; i++)
57 {
58 struct cpu_post_srawi_s *test = cpu_post_srawi_table + i;
59
60 for (reg = 0; reg < 32 && ret == 0; reg++)
61 {
62 unsigned int reg0 = (reg + 0) % 32;
63 unsigned int reg1 = (reg + 1) % 32;
64 unsigned int stk = reg < 16 ? 31 : 15;
Wolfgang Denk53677ef2008-05-20 16:00:29 +020065 unsigned long code[] =
Wolfgang Denkad5bb452007-03-06 18:08:43 +010066 {
67 ASM_STW(stk, 1, -4),
68 ASM_ADDI(stk, 1, -16),
69 ASM_STW(3, stk, 8),
70 ASM_STW(reg0, stk, 4),
71 ASM_STW(reg1, stk, 0),
72 ASM_LWZ(reg0, stk, 8),
73 ASM_11S(test->cmd, reg1, reg0, test->op2),
74 ASM_STW(reg1, stk, 8),
75 ASM_LWZ(reg1, stk, 0),
76 ASM_LWZ(reg0, stk, 4),
77 ASM_LWZ(3, stk, 8),
78 ASM_ADDI(1, stk, 16),
79 ASM_LWZ(stk, 1, -4),
80 ASM_BLR,
81 };
Wolfgang Denk53677ef2008-05-20 16:00:29 +020082 unsigned long codecr[] =
Wolfgang Denkad5bb452007-03-06 18:08:43 +010083 {
84 ASM_STW(stk, 1, -4),
85 ASM_ADDI(stk, 1, -16),
86 ASM_STW(3, stk, 8),
87 ASM_STW(reg0, stk, 4),
88 ASM_STW(reg1, stk, 0),
89 ASM_LWZ(reg0, stk, 8),
90 ASM_11S(test->cmd, reg1, reg0, test->op2) | BIT_C,
91 ASM_STW(reg1, stk, 8),
92 ASM_LWZ(reg1, stk, 0),
93 ASM_LWZ(reg0, stk, 4),
94 ASM_LWZ(3, stk, 8),
95 ASM_ADDI(1, stk, 16),
96 ASM_LWZ(stk, 1, -4),
97 ASM_BLR,
98 };
99 ulong res;
100 ulong cr;
101
102 if (ret == 0)
103 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200104 cr = 0;
105 cpu_post_exec_21 (code, & cr, & res, test->op1);
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100106
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200107 ret = res == test->res && cr == 0 ? 0 : -1;
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100108
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200109 if (ret != 0)
110 {
Wolfgang Denk93e14592013-10-04 17:43:24 +0200111 post_log ("Error at srawi test %d !\n", i);
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200112 }
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100113 }
114
115 if (ret == 0)
116 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200117 cpu_post_exec_21 (codecr, & cr, & res, test->op1);
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100118
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200119 ret = res == test->res &&
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100120 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
121
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200122 if (ret != 0)
123 {
Wolfgang Denk93e14592013-10-04 17:43:24 +0200124 post_log ("Error at srawi test %d !\n", i);
125 }
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100126 }
127 }
128 }
129
130 if (flag)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200131 enable_interrupts();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100132
133 return ret;
134}
135
136#endif