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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk5d3207d2002-08-21 22:08:56 +00002/*
Wolfgang Denk5b5eb9c2008-03-26 15:38:47 +01003 * (C) Copyright 2001-2008
Biwen Li3bebb4f2020-05-01 20:03:56 +08004 * Copyright 2020 NXP
wdenk5d3207d2002-08-21 22:08:56 +00005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Keith Outwater, keith_outwater@mvis.com`
wdenk5d3207d2002-08-21 22:08:56 +00007 */
8
9/*
10 * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
11 * DS1337 Real Time Clock (RTC).
12 */
13
14#include <common.h>
15#include <command.h>
Biwen Li3bebb4f2020-05-01 20:03:56 +080016#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060017#include <log.h>
wdenk5d3207d2002-08-21 22:08:56 +000018#include <rtc.h>
19#include <i2c.h>
20
wdenk5d3207d2002-08-21 22:08:56 +000021/*
22 * RTC register addresses
23 */
Kenth Eriksson8fde2f32012-07-12 19:59:44 +000024#if defined CONFIG_RTC_DS1337
wdenk5d3207d2002-08-21 22:08:56 +000025#define RTC_SEC_REG_ADDR 0x0
26#define RTC_MIN_REG_ADDR 0x1
27#define RTC_HR_REG_ADDR 0x2
28#define RTC_DAY_REG_ADDR 0x3
29#define RTC_DATE_REG_ADDR 0x4
30#define RTC_MON_REG_ADDR 0x5
31#define RTC_YR_REG_ADDR 0x6
32#define RTC_CTL_REG_ADDR 0x0e
33#define RTC_STAT_REG_ADDR 0x0f
Werner Pfisterb0078c82009-09-21 14:49:55 +020034#define RTC_TC_REG_ADDR 0x10
Kenth Eriksson8fde2f32012-07-12 19:59:44 +000035#elif defined CONFIG_RTC_DS1388
36#define RTC_SEC_REG_ADDR 0x1
37#define RTC_MIN_REG_ADDR 0x2
38#define RTC_HR_REG_ADDR 0x3
39#define RTC_DAY_REG_ADDR 0x4
40#define RTC_DATE_REG_ADDR 0x5
41#define RTC_MON_REG_ADDR 0x6
42#define RTC_YR_REG_ADDR 0x7
43#define RTC_CTL_REG_ADDR 0x0c
44#define RTC_STAT_REG_ADDR 0x0b
45#define RTC_TC_REG_ADDR 0x0a
46#endif
wdenk5d3207d2002-08-21 22:08:56 +000047
48/*
49 * RTC control register bits
50 */
Wolfgang Denk5b5eb9c2008-03-26 15:38:47 +010051#define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */
52#define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */
53#define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */
54#define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */
55#define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */
56#define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */
wdenk5d3207d2002-08-21 22:08:56 +000057
58/*
59 * RTC status register bits
60 */
Wolfgang Denk5b5eb9c2008-03-26 15:38:47 +010061#define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */
62#define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */
63#define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */
wdenk5d3207d2002-08-21 22:08:56 +000064
65
Biwen Li3bebb4f2020-05-01 20:03:56 +080066#if !CONFIG_IS_ENABLED(DM_RTC)
wdenk5d3207d2002-08-21 22:08:56 +000067static uchar rtc_read (uchar reg);
68static void rtc_write (uchar reg, uchar val);
wdenk5d3207d2002-08-21 22:08:56 +000069
70/*
71 * Get the current time from the RTC
72 */
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +030073int rtc_get (struct rtc_time *tmp)
wdenk5d3207d2002-08-21 22:08:56 +000074{
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +030075 int rel = 0;
wdenk5d3207d2002-08-21 22:08:56 +000076 uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
77
78 control = rtc_read (RTC_CTL_REG_ADDR);
79 status = rtc_read (RTC_STAT_REG_ADDR);
80 sec = rtc_read (RTC_SEC_REG_ADDR);
81 min = rtc_read (RTC_MIN_REG_ADDR);
82 hour = rtc_read (RTC_HR_REG_ADDR);
83 wday = rtc_read (RTC_DAY_REG_ADDR);
84 mday = rtc_read (RTC_DATE_REG_ADDR);
85 mon_cent = rtc_read (RTC_MON_REG_ADDR);
86 year = rtc_read (RTC_YR_REG_ADDR);
87
Kenth Eriksson8fde2f32012-07-12 19:59:44 +000088 /* No century bit, assume year 2000 */
89#ifdef CONFIG_RTC_DS1388
90 mon_cent |= 0x80;
91#endif
92
Wolfgang Denk88b25332011-10-29 09:39:11 +000093 debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
wdenk5d3207d2002-08-21 22:08:56 +000094 "hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
95 year, mon_cent, mday, wday, hour, min, sec, control, status);
96
97 if (status & RTC_STAT_BIT_OSF) {
98 printf ("### Warning: RTC oscillator has stopped\n");
99 /* clear the OSF flag */
100 rtc_write (RTC_STAT_REG_ADDR,
101 rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +0300102 rel = -1;
wdenk5d3207d2002-08-21 22:08:56 +0000103 }
104
105 tmp->tm_sec = bcd2bin (sec & 0x7F);
106 tmp->tm_min = bcd2bin (min & 0x7F);
107 tmp->tm_hour = bcd2bin (hour & 0x3F);
108 tmp->tm_mday = bcd2bin (mday & 0x3F);
109 tmp->tm_mon = bcd2bin (mon_cent & 0x1F);
110 tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
111 tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
112 tmp->tm_yday = 0;
113 tmp->tm_isdst= 0;
114
Wolfgang Denk88b25332011-10-29 09:39:11 +0000115 debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
wdenk5d3207d2002-08-21 22:08:56 +0000116 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
117 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +0300118
119 return rel;
wdenk5d3207d2002-08-21 22:08:56 +0000120}
121
122
123/*
124 * Set the RTC
125 */
Jean-Christophe PLAGNIOL-VILLARDd1e23192008-09-01 23:06:23 +0200126int rtc_set (struct rtc_time *tmp)
wdenk5d3207d2002-08-21 22:08:56 +0000127{
128 uchar century;
129
Wolfgang Denk88b25332011-10-29 09:39:11 +0000130 debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
wdenk5d3207d2002-08-21 22:08:56 +0000131 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
132 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
133
134 rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
135
136 century = (tmp->tm_year >= 2000) ? 0x80 : 0;
137 rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century);
138
139 rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
140 rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
141 rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
142 rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
143 rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
Jean-Christophe PLAGNIOL-VILLARDd1e23192008-09-01 23:06:23 +0200144
145 return 0;
wdenk5d3207d2002-08-21 22:08:56 +0000146}
147
148
149/*
150 * Reset the RTC. We also enable the oscillator output on the
151 * SQW/INTB* pin and program it for 32,768 Hz output. Note that
152 * according to the datasheet, turning on the square wave output
153 * increases the current drain on the backup battery from about
Chris Packham2bd3cab2017-05-30 12:03:33 +1200154 * 600 nA to 2uA. Define CONFIG_RTC_DS1337_NOOSC if you wish to turn
Joakim Tjernlundda8808d2008-03-26 13:02:13 +0100155 * off the OSC output.
wdenk5d3207d2002-08-21 22:08:56 +0000156 */
Kenth Eriksson8fde2f32012-07-12 19:59:44 +0000157
Chris Packham2bd3cab2017-05-30 12:03:33 +1200158#ifdef CONFIG_RTC_DS1337_NOOSC
Joakim Tjernlundda8808d2008-03-26 13:02:13 +0100159 #define RTC_DS1337_RESET_VAL \
Wolfgang Denk5b5eb9c2008-03-26 15:38:47 +0100160 (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
Joakim Tjernlundda8808d2008-03-26 13:02:13 +0100161#else
162 #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
163#endif
wdenk5d3207d2002-08-21 22:08:56 +0000164void rtc_reset (void)
165{
Chris Packham2bd3cab2017-05-30 12:03:33 +1200166#ifdef CONFIG_RTC_DS1337
Joakim Tjernlundda8808d2008-03-26 13:02:13 +0100167 rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
Chris Packham2bd3cab2017-05-30 12:03:33 +1200168#elif defined CONFIG_RTC_DS1388
Kenth Eriksson8fde2f32012-07-12 19:59:44 +0000169 rtc_write(RTC_CTL_REG_ADDR, 0x0); /* hw default */
170#endif
Chris Packham2bd3cab2017-05-30 12:03:33 +1200171#ifdef CONFIG_RTC_DS1339_TCR_VAL
172 rtc_write (RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL);
Werner Pfisterb0078c82009-09-21 14:49:55 +0200173#endif
Chris Packham2bd3cab2017-05-30 12:03:33 +1200174#ifdef CONFIG_RTC_DS1388_TCR_VAL
175 rtc_write(RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL);
Kenth Eriksson8fde2f32012-07-12 19:59:44 +0000176#endif
wdenk5d3207d2002-08-21 22:08:56 +0000177}
178
179
180/*
181 * Helper functions
182 */
183
184static
185uchar rtc_read (uchar reg)
186{
Tom Rini65cc0e22022-11-16 13:10:41 -0500187 return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
wdenk5d3207d2002-08-21 22:08:56 +0000188}
189
190
191static void rtc_write (uchar reg, uchar val)
192{
Tom Rini65cc0e22022-11-16 13:10:41 -0500193 i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
wdenk5d3207d2002-08-21 22:08:56 +0000194}
Biwen Li3bebb4f2020-05-01 20:03:56 +0800195#else
196static uchar rtc_read(struct udevice *dev, uchar reg)
197{
198 return dm_i2c_reg_read(dev, reg);
199}
200
201static void rtc_write(struct udevice *dev, uchar reg, uchar val)
202{
203 dm_i2c_reg_write(dev, reg, val);
204}
205
206static int ds1337_rtc_get(struct udevice *dev, struct rtc_time *tmp)
207{
208 int rel = 0;
209 uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
210
211 control = rtc_read(dev, RTC_CTL_REG_ADDR);
212 status = rtc_read(dev, RTC_STAT_REG_ADDR);
213 sec = rtc_read(dev, RTC_SEC_REG_ADDR);
214 min = rtc_read(dev, RTC_MIN_REG_ADDR);
215 hour = rtc_read(dev, RTC_HR_REG_ADDR);
216 wday = rtc_read(dev, RTC_DAY_REG_ADDR);
217 mday = rtc_read(dev, RTC_DATE_REG_ADDR);
218 mon_cent = rtc_read(dev, RTC_MON_REG_ADDR);
219 year = rtc_read(dev, RTC_YR_REG_ADDR);
220
221 /* No century bit, assume year 2000 */
222#ifdef CONFIG_RTC_DS1388
223 mon_cent |= 0x80;
224#endif
225
226 debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x\n",
227 year, mon_cent, mday, wday);
228 debug("hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
229 hour, min, sec, control, status);
230
231 if (status & RTC_STAT_BIT_OSF) {
232 printf("### Warning: RTC oscillator has stopped\n");
233 /* clear the OSF flag */
234 rtc_write(dev, RTC_STAT_REG_ADDR,
235 rtc_read(dev, RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
236 rel = -1;
237 }
238
239 tmp->tm_sec = bcd2bin(sec & 0x7F);
240 tmp->tm_min = bcd2bin(min & 0x7F);
241 tmp->tm_hour = bcd2bin(hour & 0x3F);
242 tmp->tm_mday = bcd2bin(mday & 0x3F);
243 tmp->tm_mon = bcd2bin(mon_cent & 0x1F);
244 tmp->tm_year = bcd2bin(year) + ((mon_cent & 0x80) ? 2000 : 1900);
245 tmp->tm_wday = bcd2bin((wday - 1) & 0x07);
246 tmp->tm_yday = 0;
247 tmp->tm_isdst = 0;
248
249 debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
250 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
251 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
252
253 return rel;
254}
255
256static int ds1337_rtc_set(struct udevice *dev, const struct rtc_time *tmp)
257{
258 uchar century;
259
260 debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
261 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
262 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
263
264 rtc_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100));
265
266 century = (tmp->tm_year >= 2000) ? 0x80 : 0;
267 rtc_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon) | century);
268
269 rtc_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday + 1));
270 rtc_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday));
271 rtc_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour));
272 rtc_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min));
273 rtc_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec));
274
275 return 0;
276}
277
278#ifdef CONFIG_RTC_DS1337_NOOSC
279 #define RTC_DS1337_RESET_VAL \
280 (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
281#else
282 #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
283#endif
284static int ds1337_rtc_reset(struct udevice *dev)
285{
286#ifdef CONFIG_RTC_DS1337
287 rtc_write(dev, RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
288#elif defined CONFIG_RTC_DS1388
289 rtc_write(dev, RTC_CTL_REG_ADDR, 0x0); /* hw default */
290#endif
291#ifdef CONFIG_RTC_DS1339_TCR_VAL
292 rtc_write(dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL);
293#endif
294#ifdef CONFIG_RTC_DS1388_TCR_VAL
295 rtc_write(dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL);
296#endif
297 return 0;
298}
299
300static const struct rtc_ops ds1337_rtc_ops = {
301 .get = ds1337_rtc_get,
302 .set = ds1337_rtc_set,
303 .reset = ds1337_rtc_reset,
304};
305
306static const struct udevice_id ds1337_rtc_ids[] = {
307 { .compatible = "ds1337" },
308 { .compatible = "ds1338" },
Clemens Gruber6f84e802021-11-05 14:46:50 +0100309 { .compatible = "ds1339" },
Biwen Li3bebb4f2020-05-01 20:03:56 +0800310 { }
311};
312
313U_BOOT_DRIVER(rtc_ds1337) = {
314 .name = "rtc-ds1337",
315 .id = UCLASS_RTC,
316 .of_match = ds1337_rtc_ids,
317 .ops = &ds1337_rtc_ops,
318};
319#endif