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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stephen Warrene04bfda2014-03-25 11:39:33 -06002/*
3 * (C) Copyright 2014
4 * NVIDIA Corporation <www.nvidia.com>
Stephen Warrene04bfda2014-03-25 11:39:33 -06005 */
6
7#include <common.h>
Simon Glasse3f44f52017-07-25 08:30:12 -06008#include <dm.h>
Thierry Reding6e2fca92014-12-09 22:25:21 -07009#include <power/as3722.h>
Simon Glasse3f44f52017-07-25 08:30:12 -060010#include <power/pmic.h>
Thierry Reding6e2fca92014-12-09 22:25:21 -070011
Stephen Warren93485322014-04-22 14:37:55 -060012#include <asm/arch/gpio.h>
Stephen Warrene04bfda2014-03-25 11:39:33 -060013#include <asm/arch/pinmux.h>
Thierry Reding6e2fca92014-12-09 22:25:21 -070014
Stephen Warrene04bfda2014-03-25 11:39:33 -060015#include "pinmux-config-jetson-tk1.h"
16
17/*
18 * Routine: pinmux_init
19 * Description: Do individual peripheral pinmux configs
20 */
21void pinmux_init(void)
22{
Stephen Warrenc1fe92f2015-02-18 13:27:04 -070023 pinmux_clear_tristate_input_clamping();
Stephen Warren4ff213b2014-04-22 14:37:56 -060024
Stephen Warren93485322014-04-22 14:37:55 -060025 gpio_config_table(jetson_tk1_gpio_inits,
26 ARRAY_SIZE(jetson_tk1_gpio_inits));
27
Stephen Warrene04bfda2014-03-25 11:39:33 -060028 pinmux_config_pingrp_table(jetson_tk1_pingrps,
29 ARRAY_SIZE(jetson_tk1_pingrps));
30
31 pinmux_config_drvgrp_table(jetson_tk1_drvgrps,
32 ARRAY_SIZE(jetson_tk1_drvgrps));
Stephen Warrenbbca7102016-04-21 16:03:37 -060033
34 pinmux_config_mipipadctrlgrp_table(jetson_tk1_mipipadctrlgrps,
35 ARRAY_SIZE(jetson_tk1_mipipadctrlgrps));
Stephen Warrene04bfda2014-03-25 11:39:33 -060036}
Thierry Reding6e2fca92014-12-09 22:25:21 -070037
38#ifdef CONFIG_PCI_TEGRA
Simon Glasse3f44f52017-07-25 08:30:12 -060039/* TODO: Convert to driver model */
40static int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
Thierry Reding6e2fca92014-12-09 22:25:21 -070041{
Thierry Reding6e2fca92014-12-09 22:25:21 -070042 int err;
43
Simon Glasse3f44f52017-07-25 08:30:12 -060044 if (sd > 6)
45 return -EINVAL;
46
47 err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
Thierry Reding6e2fca92014-12-09 22:25:21 -070048 if (err) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +090049 pr_err("failed to update SD control register: %d", err);
Thierry Reding6e2fca92014-12-09 22:25:21 -070050 return err;
51 }
52
Simon Glasse3f44f52017-07-25 08:30:12 -060053 return 0;
54}
55
56int tegra_pcie_board_init(void)
57{
58 struct udevice *dev;
59 int ret;
60
61 ret = uclass_get_device_by_driver(UCLASS_PMIC,
62 DM_GET_DRIVER(pmic_as3722), &dev);
63 if (ret) {
64 debug("%s: Failed to find PMIC\n", __func__);
65 return ret;
Thierry Reding6e2fca92014-12-09 22:25:21 -070066 }
67
Simon Glasse3f44f52017-07-25 08:30:12 -060068 ret = as3722_sd_enable(dev, 4);
69 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +090070 pr_err("failed to enable SD4: %d\n", ret);
Simon Glasse3f44f52017-07-25 08:30:12 -060071 return ret;
72 }
73
74 ret = as3722_sd_set_voltage(dev, 4, 0x24);
75 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +090076 pr_err("failed to set SD4 voltage: %d\n", ret);
Simon Glasse3f44f52017-07-25 08:30:12 -060077 return ret;
Thierry Reding6e2fca92014-12-09 22:25:21 -070078 }
79
Thierry Reding6e2fca92014-12-09 22:25:21 -070080 return 0;
81}
Thierry Reding6e2fca92014-12-09 22:25:21 -070082#endif /* PCI */