Blame - configs/chromebook_minnie_defconfig - platform/external/u-boot

blob: c1e36fa8601d36c6d708265f0c2717382e0ef4e4 [file] [log] [blame]

Simon Glass	c420ef6	2016-11-13 14:24:54 -0700	[diff] [blame]	1	CONFIG_ARM=y
				2	CONFIG_ARCH_ROCKCHIP=y
				3	CONFIG_SYS_MALLOC_F_LEN=0x2000
Simon Glass	c420ef6	2016-11-13 14:24:54 -0700	[diff] [blame]	4	CONFIG_ROCKCHIP_RK3288=y
Tom Rini	8728c97	2017-03-13 13:48:42 -0400	[diff] [blame]	5	# CONFIG_SPL_MMC_SUPPORT is not set
Simon Glass	c420ef6	2016-11-13 14:24:54 -0700	[diff] [blame]	6	CONFIG_TARGET_CHROMEBOOK_MINNIE=y
				7	CONFIG_SPL_SPI_FLASH_SUPPORT=y
				8	CONFIG_SPL_SPI_SUPPORT=y
				9	CONFIG_SPL_STACK_R_ADDR=0x80000
				10	CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie"
Tom Rini	fb82fe3	2017-06-19 09:47:40 -0400	[diff] [blame]	11	CONFIG_DEBUG_UART=y
Tom Rini	48f6232	2017-08-25 17:50:27 -0400	[diff] [blame]	12	# CONFIG_ANDROID_BOOT_IMAGE is not set
Simon Glass	c420ef6	2016-11-13 14:24:54 -0700	[diff] [blame]	13	CONFIG_SILENT_CONSOLE=y
				14	# CONFIG_DISPLAY_CPUINFO is not set
				15	CONFIG_SPL_STACK_R=y
				16	CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Tom Rini	48f6232	2017-08-25 17:50:27 -0400	[diff] [blame]	17	CONFIG_FASTBOOT_FLASH=y
				18	CONFIG_FASTBOOT_FLASH_MMC_DEV=0
Simon Glass	c420ef6	2016-11-13 14:24:54 -0700	[diff] [blame]	19	# CONFIG_CMD_IMLS is not set
Tom Rini	8866312	2017-08-14 19:58:53 -0400	[diff] [blame]	20	CONFIG_CMD_GPIO=y
Patrick Delaunay	b331cd6	2017-01-27 11:00:42 +0100	[diff] [blame]	21	CONFIG_CMD_GPT=y
Tom Rini	8866312	2017-08-14 19:58:53 -0400	[diff] [blame]	22	CONFIG_CMD_I2C=y
Simon Glass	c420ef6	2016-11-13 14:24:54 -0700	[diff] [blame]	23	CONFIG_CMD_MMC=y
				24	CONFIG_CMD_SF=y
Simon Glass	719d36e	2017-08-04 16:34:46 -0600	[diff] [blame]	25	CONFIG_CMD_SF_TEST=y
Tom Rini	8866312	2017-08-14 19:58:53 -0400	[diff] [blame]	26	CONFIG_CMD_SPI=y
Simon Glass	c420ef6	2016-11-13 14:24:54 -0700	[diff] [blame]	27	# CONFIG_CMD_SETEXPR is not set
Simon Glass	c420ef6	2016-11-13 14:24:54 -0700	[diff] [blame]	28	CONFIG_CMD_CACHE=y
				29	CONFIG_CMD_TIME=y
				30	CONFIG_CMD_PMIC=y
				31	CONFIG_CMD_REGULATOR=y
Patrick Delaunay	b0cf733	2017-01-27 11:00:37 +0100	[diff] [blame]	32	# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunay	1acc008	2017-01-27 11:00:38 +0100	[diff] [blame]	33	# CONFIG_SPL_ISO_PARTITION is not set
Patrick Delaunay	bd42a94	2017-01-27 11:00:41 +0100	[diff] [blame]	34	# CONFIG_SPL_EFI_PARTITION is not set
Patrick Delaunay	b331cd6	2017-01-27 11:00:42 +0100	[diff] [blame]	35	CONFIG_SPL_PARTITION_UUIDS=y
Simon Glass	c420ef6	2016-11-13 14:24:54 -0700	[diff] [blame]	36	CONFIG_SPL_OF_CONTROL=y
				37	CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Masahiro Yamada	1878095	2016-12-07 22:10:25 +0900	[diff] [blame]	38	CONFIG_SPL_OF_PLATDATA=y
Simon Glass	c420ef6	2016-11-13 14:24:54 -0700	[diff] [blame]	39	CONFIG_REGMAP=y
				40	CONFIG_SPL_REGMAP=y
				41	CONFIG_SYSCON=y
				42	CONFIG_SPL_SYSCON=y
				43	# CONFIG_SPL_SIMPLE_BUS is not set
				44	CONFIG_CLK=y
				45	CONFIG_SPL_CLK=y
				46	CONFIG_ROCKCHIP_GPIO=y
				47	CONFIG_I2C_CROS_EC_TUNNEL=y
				48	CONFIG_SYS_I2C_ROCKCHIP=y
				49	CONFIG_I2C_MUX=y
				50	CONFIG_DM_KEYBOARD=y
				51	CONFIG_CROS_EC_KEYB=y
				52	CONFIG_CROS_EC=y
				53	CONFIG_CROS_EC_SPI=y
				54	CONFIG_PWRSEQ=y
Masahiro Yamada	55ed3b4	2017-01-10 13:32:04 +0900	[diff] [blame]	55	CONFIG_MMC_DW=y
Masahiro Yamada	fed4408	2017-01-10 13:32:03 +0900	[diff] [blame]	56	CONFIG_MMC_DW_ROCKCHIP=y
Simon Glass	c420ef6	2016-11-13 14:24:54 -0700	[diff] [blame]	57	CONFIG_PINCTRL=y
				58	CONFIG_SPL_PINCTRL=y
				59	# CONFIG_SPL_PINCTRL_FULL is not set
Philipp Tomsich	51c7f34	2017-04-19 16:46:37 +0200	[diff] [blame]	60	CONFIG_PINCTRL_ROCKCHIP_RK3288=y
Simon Glass	c420ef6	2016-11-13 14:24:54 -0700	[diff] [blame]	61	CONFIG_DM_PMIC=y
				62	# CONFIG_SPL_PMIC_CHILDREN is not set
Jacob Chen	453c5a9	2017-05-02 14:54:52 +0800	[diff] [blame]	63	CONFIG_PMIC_RK8XX=y
Simon Glass	c420ef6	2016-11-13 14:24:54 -0700	[diff] [blame]	64	CONFIG_DM_REGULATOR_FIXED=y
Jacob Chen	453c5a9	2017-05-02 14:54:52 +0800	[diff] [blame]	65	CONFIG_REGULATOR_RK8XX=y
Simon Glass	c420ef6	2016-11-13 14:24:54 -0700	[diff] [blame]	66	CONFIG_PWM_ROCKCHIP=y
				67	CONFIG_RAM=y
				68	CONFIG_SPL_RAM=y
Simon Glass	c420ef6	2016-11-13 14:24:54 -0700	[diff] [blame]	69	CONFIG_DEBUG_UART_BASE=0xff690000
				70	CONFIG_DEBUG_UART_CLOCK=24000000
				71	CONFIG_DEBUG_UART_SHIFT=2
				72	CONFIG_SYS_NS16550=y
				73	CONFIG_ROCKCHIP_SERIAL=y
				74	CONFIG_ROCKCHIP_SPI=y
				75	CONFIG_SYSRESET=y
Tom Rini	ecad705	2017-08-25 17:50:26 -0400	[diff] [blame]	76	CONFIG_USB=y
				77	CONFIG_USB_GADGET=y
				78	CONFIG_USB_GADGET_DWC2_OTG=y
				79	CONFIG_USB_GADGET_DOWNLOAD=y
				80	CONFIG_G_DNL_MANUFACTURER="Rockchip"
				81	CONFIG_G_DNL_VENDOR_NUM=0x2207
				82	CONFIG_G_DNL_PRODUCT_NUM=0x320a
Simon Glass	c420ef6	2016-11-13 14:24:54 -0700	[diff] [blame]	83	CONFIG_DM_VIDEO=y
				84	CONFIG_DISPLAY=y
				85	CONFIG_VIDEO_ROCKCHIP=y
eric.gao@rock-chips.com	b98f0a3	2017-04-17 22:24:23 +0800	[diff] [blame]	86	CONFIG_DISPLAY_ROCKCHIP_EDP=y
Tom Rini	fb82fe3	2017-06-19 09:47:40 -0400	[diff] [blame]	87	CONFIG_DISPLAY_ROCKCHIP_HDMI=y
Simon Glass	c420ef6	2016-11-13 14:24:54 -0700	[diff] [blame]	88	CONFIG_CONSOLE_SCROLL_LINES=10
				89	CONFIG_USE_TINY_PRINTF=y
				90	CONFIG_CMD_DHRYSTONE=y
				91	CONFIG_ERRNO_STR=y
Simon Glass	c420ef6	2016-11-13 14:24:54 -0700	[diff] [blame]	92	# CONFIG_SPL_OF_LIBFDT is not set