| YouMin Chen | 39edfaa | 2019-11-15 11:04:43 +0800 | [diff] [blame^] | 1 | { |
| 2 | { |
| 3 | { |
| 4 | .rank = 0x1, |
| 5 | .col = 0xC, |
| 6 | .bk = 0x3, |
| 7 | .bw = 0x1, |
| 8 | .dbw = 0x0, |
| 9 | .row_3_4 = 0x0, |
| 10 | .cs0_row = 0x10, |
| 11 | .cs1_row = 0x10, |
| 12 | .cs0_high16bit_row = 0x10, |
| 13 | .cs1_high16bit_row = 0x10, |
| 14 | .ddrconfig = 0, |
| 15 | }, |
| 16 | { |
| 17 | {0x290a060a}, |
| 18 | {0x08020303}, |
| 19 | {0x00000002}, |
| 20 | {0x00001111}, |
| 21 | {0x0000000c}, |
| 22 | {0x0000021a}, |
| 23 | 0x000000ff |
| 24 | } |
| 25 | }, |
| 26 | { |
| 27 | .ddr_freq = 333, |
| 28 | .dramtype = LPDDR3, |
| 29 | .num_channels = 1, |
| 30 | .stride = 0, |
| 31 | .odt = 0, |
| 32 | }, |
| 33 | { |
| 34 | { |
| 35 | {0x00000000, 0x43041008}, /* MSTR */ |
| 36 | {0x00000064, 0x00140023}, /* RFSHTMG */ |
| 37 | {0x000000d0, 0x00220002}, /* INIT0 */ |
| 38 | {0x000000d4, 0x00010000}, /* INIT1 */ |
| 39 | {0x000000d8, 0x00000703}, /* INIT2 */ |
| 40 | {0x000000dc, 0x00830004}, /* INIT3 */ |
| 41 | {0x000000e0, 0x00010000}, /* INIT4 */ |
| 42 | {0x000000e4, 0x00070003}, /* INIT5 */ |
| 43 | {0x000000f4, 0x000f012f}, /* RANKCTL */ |
| 44 | {0x00000100, 0x06090b07}, /* DRAMTMG0 */ |
| 45 | {0x00000104, 0x0002020b}, /* DRAMTMG1 */ |
| 46 | {0x00000108, 0x02030506}, /* DRAMTMG2 */ |
| 47 | {0x0000010c, 0x00505000}, /* DRAMTMG3 */ |
| 48 | {0x00000110, 0x03020204}, /* DRAMTMG4 */ |
| 49 | {0x00000114, 0x01010303}, /* DRAMTMG5 */ |
| 50 | {0x00000118, 0x02020003}, /* DRAMTMG6 */ |
| 51 | {0x00000120, 0x00000303}, /* DRAMTMG8 */ |
| 52 | {0x00000138, 0x00000025}, /* DRAMTMG14 */ |
| 53 | {0x00000180, 0x003c000f}, /* ZQCTL0 */ |
| 54 | {0x00000184, 0x00900000}, /* ZQCTL1 */ |
| 55 | {0x00000190, 0x07020000}, /* DFITMG0 */ |
| 56 | {0x00000198, 0x07000101}, /* DFILPCFG0 */ |
| 57 | {0x000001a0, 0xc0400003}, /* DFIUPD0 */ |
| 58 | {0x00000240, 0x0900090c}, /* ODTCFG */ |
| 59 | {0x00000244, 0x00000101}, /* ODTMAP */ |
| 60 | {0x00000250, 0x00001f00}, /* SCHED */ |
| 61 | {0x00000490, 0x00000001}, /* PCTRL_0 */ |
| 62 | {0xffffffff, 0xffffffff} |
| 63 | } |
| 64 | }, |
| 65 | { |
| 66 | { |
| 67 | {0x00000004, 0x0000000b}, /* PHYREG01 */ |
| 68 | {0x00000028, 0x00000006}, /* PHYREG0A */ |
| 69 | {0x0000002c, 0x00000000}, /* PHYREG0B */ |
| 70 | {0x00000030, 0x00000003}, /* PHYREG0C */ |
| 71 | {0xffffffff, 0xffffffff} |
| 72 | } |
| 73 | } |
| 74 | }, |