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Mike Frysingerfdce83c2008-11-04 00:04:03 -05001/*
2 * Blackfin cache control code
3 *
4 * Copyright 2003-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
Mike Frysinger9171fc82008-03-30 15:46:13 -04008 * Licensed under the GPL-2 or later.
9 */
10
11#include <asm/linkage.h>
12#include <config.h>
13#include <asm/blackfin.h>
14
15.text
Mike Frysingerfdce83c2008-11-04 00:04:03 -050016/* Since all L1 caches work the same way, we use the same method for flushing
17 * them. Only the actual flush instruction differs. We write this in asm as
18 * GCC can be hard to coax into writing nice hardware loops.
19 *
20 * Also, we assume the following register setup:
21 * R0 = start address
22 * R1 = end address
23 */
24.macro do_flush flushins:req optflushins optnopins label
25
26 R2 = -L1_CACHE_BYTES;
27
28 /* start = (start & -L1_CACHE_BYTES) */
29 R0 = R0 & R2;
30
31 /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */
32 R1 += -1;
33 R1 = R1 & R2;
34 R1 += L1_CACHE_BYTES;
35
36 /* count = (end - start) >> L1_CACHE_SHIFT */
37 R2 = R1 - R0;
38 R2 >>= L1_CACHE_SHIFT;
39 P1 = R2;
40
41.ifnb \label
42\label :
43.endif
44 P0 = R0;
45 LSETUP (1f, 2f) LC1 = P1;
Mike Frysinger9171fc82008-03-30 15:46:13 -0400461:
Mike Frysingerfdce83c2008-11-04 00:04:03 -050047.ifnb \optflushins
48 \optflushins [P0];
49.endif
50#if ANOMALY_05000443
51.ifb \optnopins
522:
53.endif
54 \flushins [P0++];
55.ifnb \optnopins
562: \optnopins;
57.endif
58#else
592: \flushins [P0++];
60#endif
61
Mike Frysinger9171fc82008-03-30 15:46:13 -040062 RTS;
Mike Frysingerfdce83c2008-11-04 00:04:03 -050063.endm
64
65/* Invalidate all instruction cache lines assocoiated with this memory area */
66ENTRY(_blackfin_icache_flush_range)
67 do_flush IFLUSH, , nop
Mike Frysinger9171fc82008-03-30 15:46:13 -040068ENDPROC(_blackfin_icache_flush_range)
69
Mike Frysingerfdce83c2008-11-04 00:04:03 -050070/* Flush all cache lines assocoiated with this area of memory. */
71ENTRY(_blackfin_icache_dcache_flush_range)
72 do_flush FLUSH, IFLUSH
73ENDPROC(_blackfin_icache_dcache_flush_range)
Mike Frysinger9171fc82008-03-30 15:46:13 -040074
Mike Frysingerfdce83c2008-11-04 00:04:03 -050075/* Throw away all D-cached data in specified region without any obligation to
76 * write them back. Since the Blackfin ISA does not have an "invalidate"
77 * instruction, we use flush/invalidate. Perhaps as a speed optimization we
78 * could bang on the DTEST MMRs ...
79 */
Mike Frysinger05b75e42008-10-06 03:35:44 -040080ENTRY(_blackfin_dcache_flush_invalidate_range)
Mike Frysingerfdce83c2008-11-04 00:04:03 -050081 do_flush FLUSHINV
Mike Frysinger05b75e42008-10-06 03:35:44 -040082ENDPROC(_blackfin_dcache_flush_invalidate_range)
Mike Frysingerfdce83c2008-11-04 00:04:03 -050083
84/* Flush all data cache lines assocoiated with this memory area */
85ENTRY(_blackfin_dcache_flush_range)
86 do_flush FLUSH, , , .Ldfr
87ENDPROC(_blackfin_dcache_flush_range)