| Patrick Delaunay | 6cccc8d | 2022-07-05 16:55:57 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) |
| 2 | /* |
| 3 | * Copyright (C) STMicroelectronics 2022 - All Rights Reserved |
| 4 | */ |
| 5 | |
| 6 | / { |
| 7 | aliases { |
| 8 | gpio0 = &gpioa; |
| 9 | gpio1 = &gpiob; |
| 10 | gpio2 = &gpioc; |
| 11 | gpio3 = &gpiod; |
| 12 | gpio4 = &gpioe; |
| 13 | gpio5 = &gpiof; |
| 14 | gpio6 = &gpiog; |
| 15 | gpio7 = &gpioh; |
| 16 | gpio8 = &gpioi; |
| 17 | gpio9 = &gpioj; |
| 18 | gpio10 = &gpiok; |
| 19 | gpio25 = &gpioz; |
| 20 | pinctrl0 = &pinctrl; |
| 21 | pinctrl1 = &pinctrl_z; |
| 22 | }; |
| 23 | |
| 24 | binman: binman { |
| 25 | multiple-images; |
| 26 | }; |
| 27 | |
| 28 | soc { |
| 29 | u-boot,dm-pre-reloc; |
| 30 | |
| 31 | ddr: ddr@5a003000 { |
| 32 | u-boot,dm-pre-reloc; |
| 33 | |
| 34 | compatible = "st,stm32mp1-ddr"; |
| 35 | |
| 36 | reg = <0x5a003000 0x550 |
| 37 | 0x5a004000 0x234>; |
| 38 | |
| 39 | status = "okay"; |
| 40 | }; |
| 41 | }; |
| 42 | |
| 43 | /* need PSCI for sysreset during board_f */ |
| 44 | psci { |
| 45 | u-boot,dm-pre-proper; |
| 46 | }; |
| 47 | }; |
| 48 | |
| 49 | &bsec { |
| 50 | u-boot,dm-pre-reloc; |
| 51 | }; |
| 52 | |
| 53 | &gpioa { |
| 54 | u-boot,dm-pre-reloc; |
| 55 | }; |
| 56 | |
| 57 | &gpiob { |
| 58 | u-boot,dm-pre-reloc; |
| 59 | }; |
| 60 | |
| 61 | &gpioc { |
| 62 | u-boot,dm-pre-reloc; |
| 63 | }; |
| 64 | |
| 65 | &gpiod { |
| 66 | u-boot,dm-pre-reloc; |
| 67 | }; |
| 68 | |
| 69 | &gpioe { |
| 70 | u-boot,dm-pre-reloc; |
| 71 | }; |
| 72 | |
| 73 | &gpiof { |
| 74 | u-boot,dm-pre-reloc; |
| 75 | }; |
| 76 | |
| 77 | &gpiog { |
| 78 | u-boot,dm-pre-reloc; |
| 79 | }; |
| 80 | |
| 81 | &gpioh { |
| 82 | u-boot,dm-pre-reloc; |
| 83 | }; |
| 84 | |
| 85 | &gpioi { |
| 86 | u-boot,dm-pre-reloc; |
| 87 | }; |
| 88 | |
| 89 | &gpioj { |
| 90 | u-boot,dm-pre-reloc; |
| 91 | }; |
| 92 | |
| 93 | &gpiok { |
| 94 | u-boot,dm-pre-reloc; |
| 95 | }; |
| 96 | |
| 97 | &gpioz { |
| 98 | u-boot,dm-pre-reloc; |
| 99 | }; |
| 100 | |
| 101 | &optee { |
| 102 | u-boot,dm-pre-proper; |
| 103 | }; |
| 104 | |
| 105 | &iwdg2 { |
| 106 | u-boot,dm-pre-reloc; |
| 107 | }; |
| 108 | |
| 109 | /* pre-reloc probe = reserve video frame buffer in video_reserve() */ |
| 110 | <dc { |
| 111 | u-boot,dm-pre-proper; |
| 112 | }; |
| 113 | |
| 114 | /* temp = waiting kernel update */ |
| 115 | &m4_rproc { |
| 116 | resets = <&scmi_reset RST_SCMI_MCU>, |
| 117 | <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; |
| 118 | reset-names = "mcu_rst", "hold_boot"; |
| 119 | }; |
| 120 | |
| 121 | &pinctrl { |
| 122 | u-boot,dm-pre-reloc; |
| 123 | }; |
| 124 | |
| 125 | &pinctrl_z { |
| 126 | u-boot,dm-pre-reloc; |
| 127 | }; |
| 128 | |
| 129 | &rcc { |
| 130 | u-boot,dm-pre-reloc; |
| 131 | }; |
| 132 | |
| 133 | &scmi { |
| 134 | u-boot,dm-pre-proper; |
| 135 | }; |
| 136 | |
| 137 | &usart1 { |
| 138 | resets = <&rcc USART1_R>; |
| 139 | }; |
| 140 | |
| 141 | &usart2 { |
| 142 | resets = <&rcc USART2_R>; |
| 143 | }; |
| 144 | |
| 145 | &usart3 { |
| 146 | resets = <&rcc USART3_R>; |
| 147 | }; |
| 148 | |
| 149 | &uart4 { |
| 150 | resets = <&rcc UART4_R>; |
| 151 | }; |
| 152 | |
| 153 | &uart5 { |
| 154 | resets = <&rcc UART5_R>; |
| 155 | }; |
| 156 | |
| 157 | &usart6 { |
| 158 | resets = <&rcc USART6_R>; |
| 159 | }; |
| 160 | |
| 161 | &uart7 { |
| 162 | resets = <&rcc UART7_R>; |
| 163 | }; |
| 164 | |
| 165 | &uart8{ |
| 166 | resets = <&rcc UART8_R>; |
| 167 | }; |