Manivannan Sadhasivam | eba6589 | 2018-06-14 23:38:32 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
Amit Singh Tomar | b1a6bb3 | 2020-04-19 19:28:25 +0530 | [diff] [blame] | 3 | * Actions Semi Owl SoCs platform support. |
Manivannan Sadhasivam | eba6589 | 2018-06-14 23:38:32 +0530 | [diff] [blame] | 4 | * |
| 5 | * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |
| 6 | */ |
| 7 | |
Simon Glass | 9a3b4ce | 2019-12-28 10:45:01 -0700 | [diff] [blame] | 8 | #include <cpu_func.h> |
Simon Glass | 691d719 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 9 | #include <init.h> |
Simon Glass | 90526e9 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 10 | #include <asm/cache.h> |
Simon Glass | 401d1c4 | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 11 | #include <asm/global_data.h> |
Manivannan Sadhasivam | eba6589 | 2018-06-14 23:38:32 +0530 | [diff] [blame] | 12 | #include <linux/arm-smccc.h> |
| 13 | #include <linux/psci.h> |
| 14 | #include <common.h> |
| 15 | #include <asm/io.h> |
| 16 | #include <asm/mach-types.h> |
| 17 | #include <asm/psci.h> |
| 18 | |
Amit Singh Tomar | 3ca564e | 2020-05-09 13:45:07 +0530 | [diff] [blame] | 19 | #define DMM_INTERLEAVE_PER_CH_CFG 0xe0290028 |
| 20 | |
Manivannan Sadhasivam | eba6589 | 2018-06-14 23:38:32 +0530 | [diff] [blame] | 21 | DECLARE_GLOBAL_DATA_PTR; |
| 22 | |
Amit Singh Tomar | 3ca564e | 2020-05-09 13:45:07 +0530 | [diff] [blame] | 23 | unsigned int owl_get_ddrcap(void) |
| 24 | { |
| 25 | unsigned int val, cap; |
| 26 | |
| 27 | /* ddr capacity register initialized by ddr driver |
| 28 | * in early bootloader |
| 29 | */ |
| 30 | #if defined(CONFIG_MACH_S700) |
| 31 | val = (readl(DMM_INTERLEAVE_PER_CH_CFG) >> 8) & 0x7; |
| 32 | cap = (val + 1) * 256; |
| 33 | #elif defined(CONFIG_MACH_S900) |
| 34 | val = (readl(DMM_INTERLEAVE_PER_CH_CFG) >> 8) & 0xf; |
| 35 | cap = 64 * (1 << val); |
| 36 | #endif |
| 37 | |
| 38 | return cap; |
| 39 | } |
| 40 | |
Manivannan Sadhasivam | eba6589 | 2018-06-14 23:38:32 +0530 | [diff] [blame] | 41 | /* |
| 42 | * dram_init - sets uboots idea of sdram size |
| 43 | */ |
| 44 | int dram_init(void) |
| 45 | { |
Amit Singh Tomar | 3ca564e | 2020-05-09 13:45:07 +0530 | [diff] [blame] | 46 | gd->ram_size = owl_get_ddrcap() * 1024 * 1024; |
Manivannan Sadhasivam | eba6589 | 2018-06-14 23:38:32 +0530 | [diff] [blame] | 47 | return 0; |
| 48 | } |
| 49 | |
| 50 | /* This is called after dram_init() so use get_ram_size result */ |
| 51 | int dram_init_banksize(void) |
| 52 | { |
Tom Rini | aa6e94d | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 53 | gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; |
Manivannan Sadhasivam | eba6589 | 2018-06-14 23:38:32 +0530 | [diff] [blame] | 54 | gd->bd->bi_dram[0].size = gd->ram_size; |
| 55 | |
| 56 | return 0; |
| 57 | } |
| 58 | |
| 59 | static void show_psci_version(void) |
| 60 | { |
| 61 | struct arm_smccc_res res; |
| 62 | |
| 63 | arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res); |
| 64 | |
| 65 | printf("PSCI: v%ld.%ld\n", |
Amit Singh Tomar | b1a6bb3 | 2020-04-19 19:28:25 +0530 | [diff] [blame] | 66 | PSCI_VERSION_MAJOR(res.a0), |
Manivannan Sadhasivam | eba6589 | 2018-06-14 23:38:32 +0530 | [diff] [blame] | 67 | PSCI_VERSION_MINOR(res.a0)); |
| 68 | } |
| 69 | |
| 70 | int board_init(void) |
| 71 | { |
| 72 | show_psci_version(); |
| 73 | |
| 74 | return 0; |
| 75 | } |
| 76 | |
Harald Seiler | 35b65dd | 2020-12-15 16:47:52 +0100 | [diff] [blame] | 77 | void reset_cpu(void) |
Manivannan Sadhasivam | eba6589 | 2018-06-14 23:38:32 +0530 | [diff] [blame] | 78 | { |
| 79 | psci_system_reset(); |
| 80 | } |