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Timur Tabi2ad6b512006-10-31 18:44:42 -06001/*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
Timur Tabi7a78f142007-01-31 15:54:29 -060024 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
Timur Tabi2ad6b512006-10-31 18:44:42 -060025
26 Memory map:
27
28 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
29 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
30 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
31 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
32 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
33 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
Timur Tabi7a78f142007-01-31 15:54:29 -060034 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
Timur Tabi2ad6b512006-10-31 18:44:42 -060035 0xF001_0000-0xF001_FFFF Local bus expansion slot
Timur Tabi7a78f142007-01-31 15:54:29 -060036 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
37 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
38 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
Timur Tabi2ad6b512006-10-31 18:44:42 -060039
40 I2C address list:
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010041 Align. Board
42 Bus Addr Part No. Description Length Location
Timur Tabi2ad6b512006-10-31 18:44:42 -060043 ----------------------------------------------------------------
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010044 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
Timur Tabi2ad6b512006-10-31 18:44:42 -060045
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010046 I2C1 0x20 PCF8574 I2C Expander 0 U8
47 I2C1 0x21 PCF8574 I2C Expander 0 U10
48 I2C1 0x38 PCF8574A I2C Expander 0 U8
49 I2C1 0x39 PCF8574A I2C Expander 0 U10
50 I2C1 0x51 (DDR) DDR EEPROM 1 U1
51 I2C1 0x68 DS1339 RTC 1 U68
Timur Tabi2ad6b512006-10-31 18:44:42 -060052
53 Note that a given board has *either* a pair of 8574s or a pair of 8574As.
54*/
55
56#ifndef __CONFIG_H
57#define __CONFIG_H
58
Timur Tabi7a78f142007-01-31 15:54:29 -060059#if (TEXT_BASE == 0xFE000000)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_LOWBOOT
Timur Tabi7a78f142007-01-31 15:54:29 -060061#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -060062
63/*
64 * High Level Configuration Options
65 */
66#define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */
67#define CONFIG_MPC8349 /* MPC8349 specific */
68
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
Timur Tabi2ad6b512006-10-31 18:44:42 -060070
Timur Tabi89c77842008-02-08 13:15:55 -060071#define CONFIG_MISC_INIT_F
72#define CONFIG_MISC_INIT_R
Timur Tabi7a78f142007-01-31 15:54:29 -060073
Timur Tabi89c77842008-02-08 13:15:55 -060074/*
75 * On-board devices
76 */
Timur Tabi7a78f142007-01-31 15:54:29 -060077
78#ifdef CONFIG_MPC8349ITX
Timur Tabi2ad6b512006-10-31 18:44:42 -060079#define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */
Timur Tabi89c77842008-02-08 13:15:55 -060080#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +020081#define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */
Timur Tabi7a78f142007-01-31 15:54:29 -060082#endif
83
84#define CONFIG_PCI
Timur Tabi2ad6b512006-10-31 18:44:42 -060085#define CONFIG_RTC_DS1337
Timur Tabi7a78f142007-01-31 15:54:29 -060086#define CONFIG_HARD_I2C
87#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
88
89/*
90 * Device configurations
91 */
Timur Tabi2ad6b512006-10-31 18:44:42 -060092
93/* I2C */
Timur Tabi2ad6b512006-10-31 18:44:42 -060094#ifdef CONFIG_HARD_I2C
95
Timur Tabibe5e6182006-11-03 19:15:00 -060096#define CONFIG_FSL_I2C
Timur Tabi2ad6b512006-10-31 18:44:42 -060097#define CONFIG_I2C_MULTI_BUS
98#define CONFIG_I2C_CMD_TREE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_I2C_OFFSET 0x3000
100#define CONFIG_SYS_I2C2_OFFSET 0x3100
101#define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
Valeriy Glushkovb7be63a2009-02-04 18:27:49 +0200102#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
105#define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
106#define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
107#define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
108#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
109#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
Timur Tabibe5e6182006-11-03 19:15:00 -0600110#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
113#define CONFIG_SYS_I2C_SLAVE 0x7F
Timur Tabi2ad6b512006-10-31 18:44:42 -0600114
115/* Don't probe these addresses: */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_I2C_NOPROBES {{1, CONFIG_SYS_I2C_8574_ADDR1}, \
117 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
118 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
119 {1, CONFIG_SYS_I2C_8574A_ADDR2}}
Timur Tabi2ad6b512006-10-31 18:44:42 -0600120/* Bit definitions for the 8574[A] I2C expander */
121#define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
122#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
123#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
124#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
125#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
126
127#undef CONFIG_SOFT_I2C
128
129#endif
130
Timur Tabi7a78f142007-01-31 15:54:29 -0600131/* Compact Flash */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600132#ifdef CONFIG_COMPACT_FLASH
133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_IDE_MAXBUS 1
135#define CONFIG_SYS_IDE_MAXDEVICE 1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
138#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
139#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
140#define CONFIG_SYS_ATA_REG_OFFSET 0
141#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
142#define CONFIG_SYS_ATA_STRIDE 2
Timur Tabi2ad6b512006-10-31 18:44:42 -0600143
144#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */
145
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +0200146#endif
147
148/*
149 * SATA
150 */
151#ifdef CONFIG_SATA_SIL3114
152
153#define CONFIG_SYS_SATA_MAX_DEVICE 4
154#define CONFIG_LIBATA
155#define CONFIG_LBA48
Timur Tabi2ad6b512006-10-31 18:44:42 -0600156
Timur Tabi7a78f142007-01-31 15:54:29 -0600157#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -0600158
Timur Tabi7a78f142007-01-31 15:54:29 -0600159/*
160 * DDR Setup
161 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
163#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
164#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
165#define CONFIG_SYS_83XX_DDR_USES_CS0
166#define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
167#define CONFIG_SYS_MEMTEST_END 0x2000
Timur Tabi7a78f142007-01-31 15:54:29 -0600168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
Joe D'Abbraccio507e2d72008-03-24 13:00:59 -0400170 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
Timur Tabif64702b2007-04-30 13:59:50 -0500171
Valeriy Glushkovb7be63a2009-02-04 18:27:49 +0200172#define CONFIG_VERY_BIG_RAM
173#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
174
Timur Tabi7a78f142007-01-31 15:54:29 -0600175#ifdef CONFIG_HARD_I2C
176#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
177#endif
178
179#ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */
181 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
Timur Tabi7a78f142007-01-31 15:54:29 -0600182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183 #define CONFIG_SYS_DDR_TIMING_1 0x26242321
184 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
Timur Tabi7a78f142007-01-31 15:54:29 -0600185#endif
186
187/*
188 *Flash on the Local Bus
189 */
190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200192#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
194#define CONFIG_SYS_FLASH_EMPTY_INFO
195#define CONFIG_SYS_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */
196#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
197#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
198#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Timur Tabi7a78f142007-01-31 15:54:29 -0600199
200/* The ITX has two flash chips, but the ITX-GP has only one. To support both
201boards, we say we have two, but don't display a message if we find only one. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_FLASH_QUIET_TEST
203#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
204#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
205#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
206#define CONFIG_SYS_FLASH_SIZE_SHIFT 4 /* log2 of the above value */
207#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Timur Tabi7a78f142007-01-31 15:54:29 -0600208
Timur Tabi89c77842008-02-08 13:15:55 -0600209/* Vitesse 7385 */
210
211#ifdef CONFIG_VSC7385_ENET
212
213#define CONFIG_TSEC2
214
215/* The flash address and size of the VSC7385 firmware image */
216#define CONFIG_VSC7385_IMAGE 0xFEFFE000
217#define CONFIG_VSC7385_IMAGE_SIZE 8192
218
219#endif
220
Timur Tabi7a78f142007-01-31 15:54:29 -0600221/*
222 * BRx, ORx, LBLAWBARx, and LBLAWARx
223 */
224
225/* Flash */
226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
228#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
Anton Vorontsovf9023af2008-05-29 18:14:56 +0400229 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
Timur Tabi7a78f142007-01-31 15:54:29 -0600230 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
232#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
Timur Tabi7a78f142007-01-31 15:54:29 -0600233
234/* Vitesse 7385 */
235
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_VSC7385_BASE 0xF8000000
Timur Tabi7a78f142007-01-31 15:54:29 -0600237
Timur Tabi89c77842008-02-08 13:15:55 -0600238#ifdef CONFIG_VSC7385_ENET
239
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
241#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
Timur Tabi7a78f142007-01-31 15:54:29 -0600242 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
243 OR_GPCM_EHTR | OR_GPCM_EAD)
244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
246#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
Timur Tabi7a78f142007-01-31 15:54:29 -0600247
248#endif
249
250/* LED */
251
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_LED_BASE 0xF9000000
253#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE | BR_PS_8 | BR_V)
254#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
Timur Tabi7a78f142007-01-31 15:54:29 -0600255 OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \
256 OR_GPCM_EHTR | OR_GPCM_EAD)
257
258/* Compact Flash */
259
260#ifdef CONFIG_COMPACT_FLASH
261
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_CF_BASE 0xF0000000
Timur Tabi7a78f142007-01-31 15:54:29 -0600263
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V)
265#define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
Timur Tabi7a78f142007-01-31 15:54:29 -0600266
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE
268#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
Timur Tabi7a78f142007-01-31 15:54:29 -0600269
270#endif
271
272/*
273 * U-Boot memory configuration
274 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
278#define CONFIG_SYS_RAMBOOT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600279#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#undef CONFIG_SYS_RAMBOOT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600281#endif
282
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_INIT_RAM_LOCK
284#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
285#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
Timur Tabi2ad6b512006-10-31 18:44:42 -0600286
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
288#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
289#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Timur Tabi2ad6b512006-10-31 18:44:42 -0600290
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
292#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
293#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600294
295/*
296 * Local Bus LCRR and LBCR regs
297 * LCRR: DLL bypass, Clock divider is 4
298 * External Local Bus rate is
299 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
300 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
302#define CONFIG_SYS_LBC_LBCR 0x00000000
Timur Tabi2ad6b512006-10-31 18:44:42 -0600303
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
305#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/
Timur Tabi2ad6b512006-10-31 18:44:42 -0600306
307/*
Timur Tabi2ad6b512006-10-31 18:44:42 -0600308 * Serial Port
309 */
310#define CONFIG_CONS_INDEX 1
311#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_NS16550
313#define CONFIG_SYS_NS16550_SERIAL
314#define CONFIG_SYS_NS16550_REG_SIZE 1
315#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600316
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_BAUDRATE_TABLE \
Timur Tabi7a78f142007-01-31 15:54:29 -0600318 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
319
Nikita V. Youshchenko8a364f02007-05-23 12:45:25 +0400320#define CONFIG_CONSOLE ttyS0
Timur Tabi7a78f142007-01-31 15:54:29 -0600321#define CONFIG_BAUDRATE 115200
Timur Tabi2ad6b512006-10-31 18:44:42 -0600322
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
324#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600325
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600326/* pass open firmware flat tree */
Kim Phillips35cc4e42007-08-15 22:30:39 -0500327#define CONFIG_OF_LIBFDT 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600328#define CONFIG_OF_BOARD_SETUP 1
329#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600330
Timur Tabi7a78f142007-01-31 15:54:29 -0600331/*
332 * PCI
333 */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600334#ifdef CONFIG_PCI
335
336#define CONFIG_MPC83XX_PCI2
337
338/*
339 * General PCI
340 * Addresses are mapped 1-1.
341 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
343#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
344#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
345#define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
346#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
347#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
348#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
349#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
350#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600351
352#ifdef CONFIG_MPC83XX_PCI2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
354#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
355#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
356#define CONFIG_SYS_PCI2_MMIO_BASE (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
357#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
358#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
359#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
360#define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
361#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600362#endif
363
364#define _IO_BASE 0x00000000 /* points to PCI I/O space */
365
366#define CONFIG_NET_MULTI
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100367#define CONFIG_PCI_PNP /* do pci plug-and-play */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600368
369#ifdef CONFIG_RTL8139
370/* This macro is used by RTL8139 but not defined in PPC architecture */
371#define KSEG1ADDR(x) (x)
372#endif
373
374#ifndef CONFIG_PCI_PNP
375 #define PCI_ENET0_IOADDR 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
Timur Tabi2ad6b512006-10-31 18:44:42 -0600377 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
378#endif
379
380#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
381
382#endif
383
Timur Tabi7a78f142007-01-31 15:54:29 -0600384#define PCI_66M
385#ifdef PCI_66M
386#define CONFIG_83XX_CLKIN 66666666 /* in Hz */
387#else
388#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
389#endif
390
Timur Tabi2ad6b512006-10-31 18:44:42 -0600391/* TSEC */
392
393#ifdef CONFIG_TSEC_ENET
394
Timur Tabi2ad6b512006-10-31 18:44:42 -0600395#define CONFIG_NET_MULTI
Timur Tabi2ad6b512006-10-31 18:44:42 -0600396#define CONFIG_MII
Jon Loeliger659e2f62007-07-10 09:10:49 -0500397#define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600398
Kim Phillips255a35772007-05-16 16:52:19 -0500399#define CONFIG_TSEC1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600400
Kim Phillips255a35772007-05-16 16:52:19 -0500401#ifdef CONFIG_TSEC1
Andy Fleming10327dc2007-08-16 16:35:02 -0500402#define CONFIG_HAS_ETH0
Kim Phillips255a35772007-05-16 16:52:19 -0500403#define CONFIG_TSEC1_NAME "TSEC0"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100405#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600406#define TSEC1_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500407#define TSEC1_FLAGS TSEC_GIGABIT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600408#endif
409
Kim Phillips255a35772007-05-16 16:52:19 -0500410#ifdef CONFIG_TSEC2
Timur Tabi7a78f142007-01-31 15:54:29 -0600411#define CONFIG_HAS_ETH1
Kim Phillips255a35772007-05-16 16:52:19 -0500412#define CONFIG_TSEC2_NAME "TSEC1"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Timur Tabi89c77842008-02-08 13:15:55 -0600414
Timur Tabi2ad6b512006-10-31 18:44:42 -0600415#define TSEC2_PHY_ADDR 4
416#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500417#define TSEC2_FLAGS TSEC_GIGABIT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600418#endif
419
420#define CONFIG_ETHPRIME "Freescale TSEC"
421
422#endif
423
Timur Tabi2ad6b512006-10-31 18:44:42 -0600424/*
425 * Environment
426 */
Timur Tabi7a78f142007-01-31 15:54:29 -0600427#define CONFIG_ENV_OVERWRITE
428
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200430 #define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200432 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
433 #define CONFIG_ENV_SIZE 0x2000
Timur Tabi2ad6b512006-10-31 18:44:42 -0600434#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200436 #undef CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200437 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200439 #define CONFIG_ENV_SIZE 0x2000
Timur Tabi2ad6b512006-10-31 18:44:42 -0600440#endif
441
442#define CONFIG_LOADS_ECHO /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600444
Jon Loeliger8ea54992007-07-04 22:30:06 -0500445/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500446 * BOOTP options
447 */
448#define CONFIG_BOOTP_BOOTFILESIZE
449#define CONFIG_BOOTP_BOOTPATH
450#define CONFIG_BOOTP_GATEWAY
451#define CONFIG_BOOTP_HOSTNAME
452
453
454/*
Jon Loeliger8ea54992007-07-04 22:30:06 -0500455 * Command line configuration.
456 */
457#include <config_cmd_default.h>
458
459#define CONFIG_CMD_CACHE
460#define CONFIG_CMD_DATE
461#define CONFIG_CMD_IRQ
462#define CONFIG_CMD_NET
463#define CONFIG_CMD_PING
Valeriy Glushkovb7be63a2009-02-04 18:27:49 +0200464#define CONFIG_CMD_DHCP
Jon Loeliger8ea54992007-07-04 22:30:06 -0500465#define CONFIG_CMD_SDRAM
Timur Tabi2ad6b512006-10-31 18:44:42 -0600466
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +0200467#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114)
468 #define CONFIG_DOS_PARTITION
469 #define CONFIG_CMD_FAT
470#endif
471
Timur Tabi2ad6b512006-10-31 18:44:42 -0600472#ifdef CONFIG_COMPACT_FLASH
Jon Loeliger8ea54992007-07-04 22:30:06 -0500473 #define CONFIG_CMD_IDE
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +0200474#endif
475
476#ifdef CONFIG_SATA_SIL3114
477 #define CONFIG_CMD_SATA
478 #define CONFIG_CMD_EXT2
Timur Tabi2ad6b512006-10-31 18:44:42 -0600479#endif
480
481#ifdef CONFIG_PCI
Jon Loeliger8ea54992007-07-04 22:30:06 -0500482 #define CONFIG_CMD_PCI
Timur Tabi2ad6b512006-10-31 18:44:42 -0600483#endif
484
485#ifdef CONFIG_HARD_I2C
Jon Loeliger8ea54992007-07-04 22:30:06 -0500486 #define CONFIG_CMD_I2C
Timur Tabi2ad6b512006-10-31 18:44:42 -0600487#endif
488
Timur Tabi2ad6b512006-10-31 18:44:42 -0600489/* Watchdog */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600490#undef CONFIG_WATCHDOG /* watchdog disabled */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600491
492/*
493 * Miscellaneous configurable options
494 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200495#define CONFIG_SYS_LONGHELP /* undef to save memory */
Timur Tabi7a78f142007-01-31 15:54:29 -0600496#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200497#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
498#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Timur Tabi7a78f142007-01-31 15:54:29 -0600499
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200500#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kim Phillipsb2115752008-04-24 14:07:38 -0500501#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
Timur Tabi7a78f142007-01-31 15:54:29 -0600502
503#ifdef CONFIG_MPC8349ITX
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200504#define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */
Timur Tabi7a78f142007-01-31 15:54:29 -0600505#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200506#define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */
Timur Tabi7a78f142007-01-31 15:54:29 -0600507#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -0600508
Jon Loeliger8ea54992007-07-04 22:30:06 -0500509#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200510 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600511#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200512 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600513#endif
514
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200515#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
516#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
517#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
518#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600519
520/*
521 * For booting Linux, the board info and command line data
522 * have to be in the first 8 MB of memory, since this is
523 * the maximum mapped by the Linux kernel during initialization.
524 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200525#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Timur Tabi2ad6b512006-10-31 18:44:42 -0600526
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200527#define CONFIG_SYS_HRCW_LOW (\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600528 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
529 HRCWL_DDR_TO_SCB_CLK_1X1 |\
530 HRCWL_CSB_TO_CLKIN_4X1 |\
531 HRCWL_VCO_1X2 |\
532 HRCWL_CORE_TO_CSB_2X1)
533
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200534#ifdef CONFIG_SYS_LOWBOOT
535#define CONFIG_SYS_HRCW_HIGH (\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600536 HRCWH_PCI_HOST |\
Timur Tabi7a78f142007-01-31 15:54:29 -0600537 HRCWH_32_BIT_PCI |\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600538 HRCWH_PCI1_ARBITER_ENABLE |\
Timur Tabi7a78f142007-01-31 15:54:29 -0600539 HRCWH_PCI2_ARBITER_ENABLE |\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600540 HRCWH_CORE_ENABLE |\
541 HRCWH_FROM_0X00000100 |\
542 HRCWH_BOOTSEQ_DISABLE |\
543 HRCWH_SW_WATCHDOG_DISABLE |\
544 HRCWH_ROM_LOC_LOCAL_16BIT |\
545 HRCWH_TSEC1M_IN_GMII |\
546 HRCWH_TSEC2M_IN_GMII )
547#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200548#define CONFIG_SYS_HRCW_HIGH (\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600549 HRCWH_PCI_HOST |\
550 HRCWH_32_BIT_PCI |\
551 HRCWH_PCI1_ARBITER_ENABLE |\
Timur Tabi7a78f142007-01-31 15:54:29 -0600552 HRCWH_PCI2_ARBITER_ENABLE |\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600553 HRCWH_CORE_ENABLE |\
554 HRCWH_FROM_0XFFF00100 |\
555 HRCWH_BOOTSEQ_DISABLE |\
556 HRCWH_SW_WATCHDOG_DISABLE |\
557 HRCWH_ROM_LOC_LOCAL_16BIT |\
558 HRCWH_TSEC1M_IN_GMII |\
559 HRCWH_TSEC2M_IN_GMII )
560#endif
561
Timur Tabi7a78f142007-01-31 15:54:29 -0600562/*
563 * System performance
564 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200565#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
566#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
567#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
568#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
569#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
570#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600571
Timur Tabi7a78f142007-01-31 15:54:29 -0600572/*
573 * System IO Config
574 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200575#define CONFIG_SYS_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */
576#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600577
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200578#define CONFIG_SYS_HID0_INIT 0x000000000
579#define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600580
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200581#define CONFIG_SYS_HID2 HID2_HBE
Becky Bruce31d82672008-05-08 19:02:12 -0500582#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600583
Timur Tabi7a78f142007-01-31 15:54:29 -0600584/* DDR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200585#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
586#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600587
Timur Tabi7a78f142007-01-31 15:54:29 -0600588/* PCI */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600589#ifdef CONFIG_PCI
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200590#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
591#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
592#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
593#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600594#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200595#define CONFIG_SYS_IBAT1L 0
596#define CONFIG_SYS_IBAT1U 0
597#define CONFIG_SYS_IBAT2L 0
598#define CONFIG_SYS_IBAT2U 0
Timur Tabi2ad6b512006-10-31 18:44:42 -0600599#endif
600
601#ifdef CONFIG_MPC83XX_PCI2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200602#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
603#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
604#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
605#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600606#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200607#define CONFIG_SYS_IBAT3L 0
608#define CONFIG_SYS_IBAT3U 0
609#define CONFIG_SYS_IBAT4L 0
610#define CONFIG_SYS_IBAT4U 0
Timur Tabi2ad6b512006-10-31 18:44:42 -0600611#endif
612
613/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200614#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
615#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600616
617/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
Scott Woodc1230982009-03-31 17:49:36 -0500618#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
619 BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200620#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600621
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200622#define CONFIG_SYS_IBAT7L 0
623#define CONFIG_SYS_IBAT7U 0
Timur Tabi2ad6b512006-10-31 18:44:42 -0600624
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200625#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
626#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
627#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
628#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
629#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
630#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
631#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
632#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
633#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
634#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
635#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
636#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
637#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
638#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
639#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
640#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Timur Tabi2ad6b512006-10-31 18:44:42 -0600641
642/*
643 * Internal Definitions
644 *
645 * Boot Flags
646 */
647#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
648#define BOOTFLAG_WARM 0x02 /* Software reboot */
649
Jon Loeliger8ea54992007-07-04 22:30:06 -0500650#if defined(CONFIG_CMD_KGDB)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600651#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
652#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
653#endif
654
655
656/*
657 * Environment Configuration
658 */
659#define CONFIG_ENV_OVERWRITE
660
Timur Tabi89c77842008-02-08 13:15:55 -0600661#ifdef CONFIG_HAS_ETH0
Timur Tabi2ad6b512006-10-31 18:44:42 -0600662#define CONFIG_ETHADDR 00:E0:0C:00:8C:01
663#endif
664
Timur Tabi89c77842008-02-08 13:15:55 -0600665#ifdef CONFIG_HAS_ETH1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600666#define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02
667#endif
668
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600669#define CONFIG_IPADDR 192.168.1.253
670#define CONFIG_SERVERIP 192.168.1.1
671#define CONFIG_GATEWAYIP 192.168.1.1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600672#define CONFIG_NETMASK 255.255.252.0
Timur Tabi98883332006-10-31 19:14:41 -0600673#define CONFIG_NETDEV eth0
Timur Tabi2ad6b512006-10-31 18:44:42 -0600674
Timur Tabi7a78f142007-01-31 15:54:29 -0600675#ifdef CONFIG_MPC8349ITX
Timur Tabi2ad6b512006-10-31 18:44:42 -0600676#define CONFIG_HOSTNAME mpc8349emitx
Timur Tabi7a78f142007-01-31 15:54:29 -0600677#else
678#define CONFIG_HOSTNAME mpc8349emitxgp
679#endif
680
681/* Default path and filenames */
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600682#define CONFIG_ROOTPATH /nfsroot/rootfs
683#define CONFIG_BOOTFILE uImage
Timur Tabi7a78f142007-01-31 15:54:29 -0600684#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600685
Timur Tabi7a78f142007-01-31 15:54:29 -0600686#ifdef CONFIG_MPC8349ITX
687#define CONFIG_FDTFILE mpc8349emitx.dtb
Timur Tabi2ad6b512006-10-31 18:44:42 -0600688#else
Timur Tabi7a78f142007-01-31 15:54:29 -0600689#define CONFIG_FDTFILE mpc8349emitxgp.dtb
Timur Tabi2ad6b512006-10-31 18:44:42 -0600690#endif
691
Timur Tabi7a78f142007-01-31 15:54:29 -0600692#define CONFIG_BOOTDELAY 0
693
Timur Tabi2ad6b512006-10-31 18:44:42 -0600694#define XMK_STR(x) #x
695#define MK_STR(x) XMK_STR(x)
696
Timur Tabi98883332006-10-31 19:14:41 -0600697#define CONFIG_BOOTARGS \
698 "root=/dev/nfs rw" \
699 " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200700 " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \
Timur Tabi98883332006-10-31 19:14:41 -0600701 MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \
702 MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \
Nikita V. Youshchenko8a364f02007-05-23 12:45:25 +0400703 " console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE)
Timur Tabi98883332006-10-31 19:14:41 -0600704
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100705#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200706 "console=" MK_STR(CONFIG_CONSOLE) "\0" \
707 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
708 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
709 "tftpflash=tftpboot $loadaddr $uboot; " \
710 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
711 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
712 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
713 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
714 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100715 "fdtaddr=400000\0" \
Timur Tabi7a78f142007-01-31 15:54:29 -0600716 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600717
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100718#define CONFIG_NFSBOOTCOMMAND \
Timur Tabi7a78f142007-01-31 15:54:29 -0600719 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
720 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
721 " console=$console,$baudrate $othbootargs; " \
722 "tftp $loadaddr $bootfile;" \
723 "tftp $fdtaddr $fdtfile;" \
724 "bootm $loadaddr - $fdtaddr"
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600725
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100726#define CONFIG_RAMBOOTCOMMAND \
Timur Tabi7a78f142007-01-31 15:54:29 -0600727 "setenv bootargs root=/dev/ram rw" \
728 " console=$console,$baudrate $othbootargs; " \
729 "tftp $ramdiskaddr $ramdiskfile;" \
730 "tftp $loadaddr $bootfile;" \
731 "tftp $fdtaddr $fdtfile;" \
732 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600733
734#undef MK_STR
735#undef XMK_STR
736
737#endif