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wdenk42d1f032003-10-15 23:53:47 +00001/*
wdenk97d80fc2004-06-09 00:34:46 +00002 * Freescale Three Speed Ethernet Controller driver
wdenk42d1f032003-10-15 23:53:47 +00003 *
4 * This software may be used and distributed according to the
5 * terms of the GNU Public License, Version 2, incorporated
6 * herein by reference.
7 *
Andy Fleming81f481c2007-04-23 02:24:28 -05008 * Copyright 2004, 2007 Freescale Semiconductor, Inc.
wdenk42d1f032003-10-15 23:53:47 +00009 * (C) Copyright 2003, Motorola, Inc.
wdenk42d1f032003-10-15 23:53:47 +000010 * author Andy Fleming
11 *
12 */
13
14#include <config.h>
wdenk42d1f032003-10-15 23:53:47 +000015#include <common.h>
16#include <malloc.h>
17#include <net.h>
18#include <command.h>
19
20#if defined(CONFIG_TSEC_ENET)
21#include "tsec.h"
Marian Balakowicz63ff0042005-10-28 22:30:33 +020022#include "miiphy.h"
wdenk42d1f032003-10-15 23:53:47 +000023
Wolfgang Denkd87080b2006-03-31 18:32:53 +020024DECLARE_GLOBAL_DATA_PTR;
25
Marian Balakowicz63ff0042005-10-28 22:30:33 +020026#define TX_BUF_CNT 2
wdenk42d1f032003-10-15 23:53:47 +000027
Jon Loeliger89875e92006-10-10 17:03:43 -050028static uint rxIdx; /* index of the current RX buffer */
29static uint txIdx; /* index of the current TX buffer */
wdenk42d1f032003-10-15 23:53:47 +000030
31typedef volatile struct rtxbd {
32 txbd8_t txbd[TX_BUF_CNT];
33 rxbd8_t rxbd[PKTBUFSRX];
Jon Loeliger89875e92006-10-10 17:03:43 -050034} RTXBD;
wdenk42d1f032003-10-15 23:53:47 +000035
wdenk97d80fc2004-06-09 00:34:46 +000036struct tsec_info_struct {
37 unsigned int phyaddr;
Jon Loeligerd9b94f22005-07-25 14:05:07 -050038 u32 flags;
wdenk97d80fc2004-06-09 00:34:46 +000039 unsigned int phyregidx;
40};
41
wdenk97d80fc2004-06-09 00:34:46 +000042/* The tsec_info structure contains 3 values which the
43 * driver uses to determine how to operate a given ethernet
Andy Fleming09f3e092006-09-13 10:34:18 -050044 * device. The information needed is:
wdenk97d80fc2004-06-09 00:34:46 +000045 * phyaddr - The address of the PHY which is attached to
wdenk9d46ea42005-03-14 23:56:42 +000046 * the given device.
wdenk97d80fc2004-06-09 00:34:46 +000047 *
Jon Loeligerd9b94f22005-07-25 14:05:07 -050048 * flags - This variable indicates whether the device
49 * supports gigabit speed ethernet, and whether it should be
50 * in reduced mode.
wdenk97d80fc2004-06-09 00:34:46 +000051 *
52 * phyregidx - This variable specifies which ethernet device
wdenk9d46ea42005-03-14 23:56:42 +000053 * controls the MII Management registers which are connected
Andy Fleming09f3e092006-09-13 10:34:18 -050054 * to the PHY. For now, only TSEC1 (index 0) has
wdenk9d46ea42005-03-14 23:56:42 +000055 * access to the PHYs, so all of the entries have "0".
wdenk97d80fc2004-06-09 00:34:46 +000056 *
57 * The values specified in the table are taken from the board's
58 * config file in include/configs/. When implementing a new
59 * board with ethernet capability, it is necessary to define:
Andy Fleming09f3e092006-09-13 10:34:18 -050060 * TSECn_PHY_ADDR
61 * TSECn_PHYIDX
wdenk97d80fc2004-06-09 00:34:46 +000062 *
Andy Fleming09f3e092006-09-13 10:34:18 -050063 * for n = 1,2,3, etc. And for FEC:
wdenk97d80fc2004-06-09 00:34:46 +000064 * FEC_PHY_ADDR
65 * FEC_PHYIDX
66 */
67static struct tsec_info_struct tsec_info[] = {
Andy Fleming3a790132007-08-15 20:03:25 -050068#ifdef CONFIG_TSEC1
69 {TSEC1_PHY_ADDR, TSEC1_FLAGS, TSEC1_PHYIDX},
Zach Sadeckied810642007-07-31 12:27:25 -050070#else
Jon Loeliger89875e92006-10-10 17:03:43 -050071 {0, 0, 0},
wdenk97d80fc2004-06-09 00:34:46 +000072#endif
Andy Fleming3a790132007-08-15 20:03:25 -050073#ifdef CONFIG_TSEC2
74 {TSEC2_PHY_ADDR, TSEC2_FLAGS, TSEC2_PHYIDX},
Zach Sadeckied810642007-07-31 12:27:25 -050075#else
Jon Loeliger89875e92006-10-10 17:03:43 -050076 {0, 0, 0},
wdenk97d80fc2004-06-09 00:34:46 +000077#endif
78#ifdef CONFIG_MPC85XX_FEC
Andy Fleming3a790132007-08-15 20:03:25 -050079 {FEC_PHY_ADDR, FEC_FLAGS, FEC_PHYIDX},
wdenk9d46ea42005-03-14 23:56:42 +000080#else
Andy Fleming3a790132007-08-15 20:03:25 -050081#ifdef CONFIG_TSEC3
82 {TSEC3_PHY_ADDR, TSEC3_FLAGS, TSEC3_PHYIDX},
Jon Loeligerdebb7352006-04-26 17:58:56 -050083#else
Jon Loeliger89875e92006-10-10 17:03:43 -050084 {0, 0, 0},
Jon Loeligerdebb7352006-04-26 17:58:56 -050085#endif
Andy Fleming3a790132007-08-15 20:03:25 -050086#ifdef CONFIG_TSEC4
87 {TSEC4_PHY_ADDR, TSEC4_FLAGS, TSEC4_PHYIDX},
Jon Loeligerdebb7352006-04-26 17:58:56 -050088#else
Jon Loeliger89875e92006-10-10 17:03:43 -050089 {0, 0, 0},
Andy Fleming3a790132007-08-15 20:03:25 -050090#endif /* CONFIG_TSEC4 */
91#endif /* CONFIG_MPC85XX_FEC */
wdenk97d80fc2004-06-09 00:34:46 +000092};
93
Jon Loeligerd9b94f22005-07-25 14:05:07 -050094#define MAXCONTROLLERS (4)
wdenk97d80fc2004-06-09 00:34:46 +000095
96static int relocated = 0;
97
98static struct tsec_private *privlist[MAXCONTROLLERS];
99
wdenk42d1f032003-10-15 23:53:47 +0000100#ifdef __GNUC__
101static RTXBD rtx __attribute__ ((aligned(8)));
102#else
103#error "rtx must be 64-bit aligned"
104#endif
105
Jon Loeliger89875e92006-10-10 17:03:43 -0500106static int tsec_send(struct eth_device *dev,
107 volatile void *packet, int length);
108static int tsec_recv(struct eth_device *dev);
109static int tsec_init(struct eth_device *dev, bd_t * bd);
110static void tsec_halt(struct eth_device *dev);
111static void init_registers(volatile tsec_t * regs);
wdenk97d80fc2004-06-09 00:34:46 +0000112static void startup_tsec(struct eth_device *dev);
113static int init_phy(struct eth_device *dev);
114void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
115uint read_phy_reg(struct tsec_private *priv, uint regnum);
Jon Loeliger89875e92006-10-10 17:03:43 -0500116struct phy_info *get_phy_info(struct eth_device *dev);
wdenk97d80fc2004-06-09 00:34:46 +0000117void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
118static void adjust_link(struct eth_device *dev);
119static void relocate_cmds(void);
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200120static int tsec_miiphy_write(char *devname, unsigned char addr,
Jon Loeliger89875e92006-10-10 17:03:43 -0500121 unsigned char reg, unsigned short value);
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200122static int tsec_miiphy_read(char *devname, unsigned char addr,
Jon Loeliger89875e92006-10-10 17:03:43 -0500123 unsigned char reg, unsigned short *value);
David Updegraff53a5c422007-06-11 10:41:07 -0500124#ifdef CONFIG_MCAST_TFTP
125static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set);
126#endif
wdenk7abf0c52004-04-18 21:45:42 +0000127
wdenk97d80fc2004-06-09 00:34:46 +0000128/* Initialize device structure. Returns success if PHY
129 * initialization succeeded (i.e. if it recognizes the PHY)
130 */
Jon Loeliger89875e92006-10-10 17:03:43 -0500131int tsec_initialize(bd_t * bis, int index, char *devname)
wdenk42d1f032003-10-15 23:53:47 +0000132{
Jon Loeliger89875e92006-10-10 17:03:43 -0500133 struct eth_device *dev;
wdenk42d1f032003-10-15 23:53:47 +0000134 int i;
wdenk97d80fc2004-06-09 00:34:46 +0000135 struct tsec_private *priv;
wdenk42d1f032003-10-15 23:53:47 +0000136
Jon Loeliger89875e92006-10-10 17:03:43 -0500137 dev = (struct eth_device *)malloc(sizeof *dev);
wdenk42d1f032003-10-15 23:53:47 +0000138
Jon Loeliger89875e92006-10-10 17:03:43 -0500139 if (NULL == dev)
wdenk42d1f032003-10-15 23:53:47 +0000140 return 0;
141
142 memset(dev, 0, sizeof *dev);
143
Jon Loeliger89875e92006-10-10 17:03:43 -0500144 priv = (struct tsec_private *)malloc(sizeof(*priv));
wdenk97d80fc2004-06-09 00:34:46 +0000145
Jon Loeliger89875e92006-10-10 17:03:43 -0500146 if (NULL == priv)
wdenk97d80fc2004-06-09 00:34:46 +0000147 return 0;
148
149 privlist[index] = priv;
Jon Loeliger89875e92006-10-10 17:03:43 -0500150 priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE);
wdenk97d80fc2004-06-09 00:34:46 +0000151 priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
Jon Loeliger89875e92006-10-10 17:03:43 -0500152 tsec_info[index].phyregidx *
153 TSEC_SIZE);
wdenk97d80fc2004-06-09 00:34:46 +0000154
155 priv->phyaddr = tsec_info[index].phyaddr;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500156 priv->flags = tsec_info[index].flags;
wdenk97d80fc2004-06-09 00:34:46 +0000157
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500158 sprintf(dev->name, devname);
wdenk42d1f032003-10-15 23:53:47 +0000159 dev->iobase = 0;
Jon Loeliger89875e92006-10-10 17:03:43 -0500160 dev->priv = priv;
161 dev->init = tsec_init;
162 dev->halt = tsec_halt;
163 dev->send = tsec_send;
164 dev->recv = tsec_recv;
David Updegraff53a5c422007-06-11 10:41:07 -0500165#ifdef CONFIG_MCAST_TFTP
166 dev->mcast = tsec_mcast_addr;
167#endif
wdenk42d1f032003-10-15 23:53:47 +0000168
169 /* Tell u-boot to get the addr from the env */
Jon Loeliger89875e92006-10-10 17:03:43 -0500170 for (i = 0; i < 6; i++)
wdenk42d1f032003-10-15 23:53:47 +0000171 dev->enetaddr[i] = 0;
172
173 eth_register(dev);
174
wdenk97d80fc2004-06-09 00:34:46 +0000175 /* Reset the MAC */
176 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
177 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
wdenk7abf0c52004-04-18 21:45:42 +0000178
Jon Loeligercb51c0b2007-07-09 17:39:42 -0500179#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200180 && !defined(BITBANGMII)
181 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
182#endif
183
wdenk97d80fc2004-06-09 00:34:46 +0000184 /* Try to initialize PHY here, and return */
185 return init_phy(dev);
wdenk42d1f032003-10-15 23:53:47 +0000186}
187
wdenk42d1f032003-10-15 23:53:47 +0000188/* Initializes data structures and registers for the controller,
wdenk9d46ea42005-03-14 23:56:42 +0000189 * and brings the interface up. Returns the link status, meaning
wdenk97d80fc2004-06-09 00:34:46 +0000190 * that it returns success if the link is up, failure otherwise.
Jon Loeliger89875e92006-10-10 17:03:43 -0500191 * This allows u-boot to find the first active controller.
192 */
193int tsec_init(struct eth_device *dev, bd_t * bd)
wdenk42d1f032003-10-15 23:53:47 +0000194{
wdenk42d1f032003-10-15 23:53:47 +0000195 uint tempval;
196 char tmpbuf[MAC_ADDR_LEN];
197 int i;
wdenk97d80fc2004-06-09 00:34:46 +0000198 struct tsec_private *priv = (struct tsec_private *)dev->priv;
199 volatile tsec_t *regs = priv->regs;
wdenk42d1f032003-10-15 23:53:47 +0000200
201 /* Make sure the controller is stopped */
202 tsec_halt(dev);
203
wdenk97d80fc2004-06-09 00:34:46 +0000204 /* Init MACCFG2. Defaults to GMII */
wdenk42d1f032003-10-15 23:53:47 +0000205 regs->maccfg2 = MACCFG2_INIT_SETTINGS;
206
207 /* Init ECNTRL */
208 regs->ecntrl = ECNTRL_INIT_SETTINGS;
209
210 /* Copy the station address into the address registers.
211 * Backwards, because little endian MACS are dumb */
Jon Loeliger89875e92006-10-10 17:03:43 -0500212 for (i = 0; i < MAC_ADDR_LEN; i++) {
wdenk97d80fc2004-06-09 00:34:46 +0000213 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
wdenk42d1f032003-10-15 23:53:47 +0000214 }
Jon Loeliger89875e92006-10-10 17:03:43 -0500215 regs->macstnaddr1 = *((uint *) (tmpbuf));
wdenk42d1f032003-10-15 23:53:47 +0000216
Jon Loeliger89875e92006-10-10 17:03:43 -0500217 tempval = *((uint *) (tmpbuf + 4));
wdenk42d1f032003-10-15 23:53:47 +0000218
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200219 regs->macstnaddr2 = tempval;
wdenk42d1f032003-10-15 23:53:47 +0000220
wdenk42d1f032003-10-15 23:53:47 +0000221 /* reset the indices to zero */
222 rxIdx = 0;
223 txIdx = 0;
224
225 /* Clear out (for the most part) the other registers */
226 init_registers(regs);
227
228 /* Ready the device for tx/rx */
wdenk97d80fc2004-06-09 00:34:46 +0000229 startup_tsec(dev);
wdenk42d1f032003-10-15 23:53:47 +0000230
wdenk97d80fc2004-06-09 00:34:46 +0000231 /* If there's no link, fail */
232 return priv->link;
wdenk42d1f032003-10-15 23:53:47 +0000233
234}
235
wdenk97d80fc2004-06-09 00:34:46 +0000236/* Write value to the device's PHY through the registers
237 * specified in priv, modifying the register specified in regnum.
238 * It will wait for the write to be done (or for a timeout to
239 * expire) before exiting
240 */
241void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
242{
243 volatile tsec_t *regbase = priv->phyregs;
244 uint phyid = priv->phyaddr;
Jon Loeliger89875e92006-10-10 17:03:43 -0500245 int timeout = 1000000;
wdenk97d80fc2004-06-09 00:34:46 +0000246
247 regbase->miimadd = (phyid << 8) | regnum;
248 regbase->miimcon = value;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500249 asm("sync");
wdenk97d80fc2004-06-09 00:34:46 +0000250
Jon Loeliger89875e92006-10-10 17:03:43 -0500251 timeout = 1000000;
252 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
wdenk97d80fc2004-06-09 00:34:46 +0000253}
254
wdenk97d80fc2004-06-09 00:34:46 +0000255/* Reads register regnum on the device's PHY through the
wdenk9d46ea42005-03-14 23:56:42 +0000256 * registers specified in priv. It lowers and raises the read
wdenk97d80fc2004-06-09 00:34:46 +0000257 * command, and waits for the data to become valid (miimind
258 * notvalid bit cleared), and the bus to cease activity (miimind
259 * busy bit cleared), and then returns the value
260 */
261uint read_phy_reg(struct tsec_private *priv, uint regnum)
wdenk42d1f032003-10-15 23:53:47 +0000262{
263 uint value;
wdenk97d80fc2004-06-09 00:34:46 +0000264 volatile tsec_t *regbase = priv->phyregs;
265 uint phyid = priv->phyaddr;
wdenk42d1f032003-10-15 23:53:47 +0000266
wdenk97d80fc2004-06-09 00:34:46 +0000267 /* Put the address of the phy, and the register
268 * number into MIIMADD */
269 regbase->miimadd = (phyid << 8) | regnum;
wdenk42d1f032003-10-15 23:53:47 +0000270
271 /* Clear the command register, and wait */
272 regbase->miimcom = 0;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500273 asm("sync");
wdenk42d1f032003-10-15 23:53:47 +0000274
275 /* Initiate a read command, and wait */
276 regbase->miimcom = MIIM_READ_COMMAND;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500277 asm("sync");
wdenk42d1f032003-10-15 23:53:47 +0000278
279 /* Wait for the the indication that the read is done */
Jon Loeliger89875e92006-10-10 17:03:43 -0500280 while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
wdenk42d1f032003-10-15 23:53:47 +0000281
282 /* Grab the value read from the PHY */
283 value = regbase->miimstat;
284
285 return value;
286}
287
wdenk97d80fc2004-06-09 00:34:46 +0000288/* Discover which PHY is attached to the device, and configure it
289 * properly. If the PHY is not recognized, then return 0
290 * (failure). Otherwise, return 1
291 */
292static int init_phy(struct eth_device *dev)
wdenk42d1f032003-10-15 23:53:47 +0000293{
wdenk97d80fc2004-06-09 00:34:46 +0000294 struct tsec_private *priv = (struct tsec_private *)dev->priv;
295 struct phy_info *curphy;
Jon Loeliger89875e92006-10-10 17:03:43 -0500296 volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
wdenk42d1f032003-10-15 23:53:47 +0000297
298 /* Assign a Physical address to the TBI */
Joe Hammandcb84b72007-08-09 09:08:18 -0500299 regs->tbipa = CFG_TBIPA_VALUE;
Jon Loeliger89875e92006-10-10 17:03:43 -0500300 regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
Joe Hammandcb84b72007-08-09 09:08:18 -0500301 regs->tbipa = CFG_TBIPA_VALUE;
Jon Loeliger89875e92006-10-10 17:03:43 -0500302 asm("sync");
wdenk3dd7f0f2005-04-04 23:43:44 +0000303
304 /* Reset MII (due to new addresses) */
305 priv->phyregs->miimcfg = MIIMCFG_RESET;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500306 asm("sync");
wdenk3dd7f0f2005-04-04 23:43:44 +0000307 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500308 asm("sync");
Jon Loeliger89875e92006-10-10 17:03:43 -0500309 while (priv->phyregs->miimind & MIIMIND_BUSY) ;
wdenk42d1f032003-10-15 23:53:47 +0000310
Jon Loeliger89875e92006-10-10 17:03:43 -0500311 if (0 == relocated)
wdenk97d80fc2004-06-09 00:34:46 +0000312 relocate_cmds();
wdenk42d1f032003-10-15 23:53:47 +0000313
wdenk97d80fc2004-06-09 00:34:46 +0000314 /* Get the cmd structure corresponding to the attached
315 * PHY */
316 curphy = get_phy_info(dev);
wdenk42d1f032003-10-15 23:53:47 +0000317
Ben Warren4653f912006-10-26 14:38:25 -0400318 if (curphy == NULL) {
319 priv->phyinfo = NULL;
wdenk97d80fc2004-06-09 00:34:46 +0000320 printf("%s: No PHY found\n", dev->name);
wdenk42d1f032003-10-15 23:53:47 +0000321
wdenk97d80fc2004-06-09 00:34:46 +0000322 return 0;
wdenk42d1f032003-10-15 23:53:47 +0000323 }
324
wdenk97d80fc2004-06-09 00:34:46 +0000325 priv->phyinfo = curphy;
wdenk42d1f032003-10-15 23:53:47 +0000326
wdenk97d80fc2004-06-09 00:34:46 +0000327 phy_run_commands(priv, priv->phyinfo->config);
wdenk42d1f032003-10-15 23:53:47 +0000328
wdenk97d80fc2004-06-09 00:34:46 +0000329 return 1;
wdenk42d1f032003-10-15 23:53:47 +0000330}
331
Jon Loeliger89875e92006-10-10 17:03:43 -0500332/*
333 * Returns which value to write to the control register.
334 * For 10/100, the value is slightly different
335 */
336uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
wdenk97d80fc2004-06-09 00:34:46 +0000337{
Jon Loeliger89875e92006-10-10 17:03:43 -0500338 if (priv->flags & TSEC_GIGABIT)
wdenk97d80fc2004-06-09 00:34:46 +0000339 return MIIM_CONTROL_INIT;
340 else
341 return MIIM_CR_INIT;
342}
343
wdenk97d80fc2004-06-09 00:34:46 +0000344/* Parse the status register for link, and then do
Jon Loeliger89875e92006-10-10 17:03:43 -0500345 * auto-negotiation
346 */
347uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
wdenk97d80fc2004-06-09 00:34:46 +0000348{
Stefan Roese5810dc32005-09-21 18:20:22 +0200349 /*
Jon Loeliger89875e92006-10-10 17:03:43 -0500350 * Wait if PHY is capable of autonegotiation and autonegotiation
351 * is not complete.
Stefan Roese5810dc32005-09-21 18:20:22 +0200352 */
353 mii_reg = read_phy_reg(priv, MIIM_STATUS);
Jon Loeliger89875e92006-10-10 17:03:43 -0500354 if ((mii_reg & PHY_BMSR_AUTN_ABLE)
355 && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
Stefan Roese5810dc32005-09-21 18:20:22 +0200356 int i = 0;
wdenk97d80fc2004-06-09 00:34:46 +0000357
Jon Loeliger89875e92006-10-10 17:03:43 -0500358 puts("Waiting for PHY auto negotiation to complete");
359 while (!((mii_reg & PHY_BMSR_AUTN_COMP)
360 && (mii_reg & MIIM_STATUS_LINK))) {
Stefan Roese5810dc32005-09-21 18:20:22 +0200361 /*
362 * Timeout reached ?
363 */
364 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
Jon Loeliger89875e92006-10-10 17:03:43 -0500365 puts(" TIMEOUT !\n");
Stefan Roese5810dc32005-09-21 18:20:22 +0200366 priv->link = 0;
Jin Zhengxiong-R64188fcfb9a52006-06-27 18:12:23 +0800367 return 0;
Stefan Roese5810dc32005-09-21 18:20:22 +0200368 }
wdenk97d80fc2004-06-09 00:34:46 +0000369
Stefan Roese5810dc32005-09-21 18:20:22 +0200370 if ((i++ % 1000) == 0) {
Jon Loeliger89875e92006-10-10 17:03:43 -0500371 putc('.');
Stefan Roese5810dc32005-09-21 18:20:22 +0200372 }
Jon Loeliger89875e92006-10-10 17:03:43 -0500373 udelay(1000); /* 1 ms */
wdenk97d80fc2004-06-09 00:34:46 +0000374 mii_reg = read_phy_reg(priv, MIIM_STATUS);
Stefan Roese5810dc32005-09-21 18:20:22 +0200375 }
Jon Loeliger89875e92006-10-10 17:03:43 -0500376 puts(" done\n");
Stefan Roese5810dc32005-09-21 18:20:22 +0200377 priv->link = 1;
Jon Loeliger89875e92006-10-10 17:03:43 -0500378 udelay(500000); /* another 500 ms (results in faster booting) */
Stefan Roese5810dc32005-09-21 18:20:22 +0200379 } else {
380 priv->link = 1;
wdenk97d80fc2004-06-09 00:34:46 +0000381 }
382
383 return 0;
384}
385
David Updegraffaf1c2b82007-04-20 14:34:48 -0500386/* Generic function which updates the speed and duplex. If
387 * autonegotiation is enabled, it uses the AND of the link
388 * partner's advertised capabilities and our advertised
389 * capabilities. If autonegotiation is disabled, we use the
390 * appropriate bits in the control register.
391 *
392 * Stolen from Linux's mii.c and phy_device.c
393 */
394uint mii_parse_link(uint mii_reg, struct tsec_private *priv)
395{
396 /* We're using autonegotiation */
397 if (mii_reg & PHY_BMSR_AUTN_ABLE) {
398 uint lpa = 0;
399 uint gblpa = 0;
400
401 /* Check for gigabit capability */
402 if (mii_reg & PHY_BMSR_EXT) {
403 /* We want a list of states supported by
404 * both PHYs in the link
405 */
406 gblpa = read_phy_reg(priv, PHY_1000BTSR);
407 gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2;
408 }
409
410 /* Set the baseline so we only have to set them
411 * if they're different
412 */
413 priv->speed = 10;
414 priv->duplexity = 0;
415
416 /* Check the gigabit fields */
417 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
418 priv->speed = 1000;
419
420 if (gblpa & PHY_1000BTSR_1000FD)
421 priv->duplexity = 1;
422
423 /* We're done! */
424 return 0;
425 }
426
427 lpa = read_phy_reg(priv, PHY_ANAR);
428 lpa &= read_phy_reg(priv, PHY_ANLPAR);
429
430 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) {
431 priv->speed = 100;
432
433 if (lpa & PHY_ANLPAR_TXFD)
434 priv->duplexity = 1;
435
436 } else if (lpa & PHY_ANLPAR_10FD)
437 priv->duplexity = 1;
438 } else {
439 uint bmcr = read_phy_reg(priv, PHY_BMCR);
440
441 priv->speed = 10;
442 priv->duplexity = 0;
443
444 if (bmcr & PHY_BMCR_DPLX)
445 priv->duplexity = 1;
446
447 if (bmcr & PHY_BMCR_1000_MBPS)
448 priv->speed = 1000;
449 else if (bmcr & PHY_BMCR_100_MBPS)
450 priv->speed = 100;
451 }
452
453 return 0;
454}
455
Paul Gortmaker91e25762007-01-16 11:38:14 -0500456/*
457 * Parse the BCM54xx status register for speed and duplex information.
458 * The linux sungem_phy has this information, but in a table format.
459 */
460uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv)
461{
462
463 switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){
464
465 case 1:
466 printf("Enet starting in 10BT/HD\n");
467 priv->duplexity = 0;
468 priv->speed = 10;
469 break;
470
471 case 2:
472 printf("Enet starting in 10BT/FD\n");
473 priv->duplexity = 1;
474 priv->speed = 10;
475 break;
476
477 case 3:
478 printf("Enet starting in 100BT/HD\n");
479 priv->duplexity = 0;
480 priv->speed = 100;
481 break;
482
483 case 5:
484 printf("Enet starting in 100BT/FD\n");
485 priv->duplexity = 1;
486 priv->speed = 100;
487 break;
488
489 case 6:
490 printf("Enet starting in 1000BT/HD\n");
491 priv->duplexity = 0;
492 priv->speed = 1000;
493 break;
494
495 case 7:
496 printf("Enet starting in 1000BT/FD\n");
497 priv->duplexity = 1;
498 priv->speed = 1000;
499 break;
500
501 default:
502 printf("Auto-neg error, defaulting to 10BT/HD\n");
503 priv->duplexity = 0;
504 priv->speed = 10;
505 break;
506 }
507
508 return 0;
509
510}
wdenk97d80fc2004-06-09 00:34:46 +0000511/* Parse the 88E1011's status register for speed and duplex
Jon Loeliger89875e92006-10-10 17:03:43 -0500512 * information
513 */
514uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
wdenk97d80fc2004-06-09 00:34:46 +0000515{
516 uint speed;
517
Stefan Roese5810dc32005-09-21 18:20:22 +0200518 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
519
520 if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
521 (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
522 int i = 0;
523
Jon Loeliger89875e92006-10-10 17:03:43 -0500524 puts("Waiting for PHY realtime link");
Stefan Roese5810dc32005-09-21 18:20:22 +0200525 while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
526 (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
527 /*
528 * Timeout reached ?
529 */
530 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
Jon Loeliger89875e92006-10-10 17:03:43 -0500531 puts(" TIMEOUT !\n");
Stefan Roese5810dc32005-09-21 18:20:22 +0200532 priv->link = 0;
533 break;
534 }
535
536 if ((i++ % 1000) == 0) {
Jon Loeliger89875e92006-10-10 17:03:43 -0500537 putc('.');
Stefan Roese5810dc32005-09-21 18:20:22 +0200538 }
Jon Loeliger89875e92006-10-10 17:03:43 -0500539 udelay(1000); /* 1 ms */
Stefan Roese5810dc32005-09-21 18:20:22 +0200540 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
541 }
Jon Loeliger89875e92006-10-10 17:03:43 -0500542 puts(" done\n");
543 udelay(500000); /* another 500 ms (results in faster booting) */
Stefan Roese5810dc32005-09-21 18:20:22 +0200544 }
545
Jon Loeliger89875e92006-10-10 17:03:43 -0500546 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
wdenk97d80fc2004-06-09 00:34:46 +0000547 priv->duplexity = 1;
548 else
549 priv->duplexity = 0;
550
Jon Loeliger89875e92006-10-10 17:03:43 -0500551 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
wdenk97d80fc2004-06-09 00:34:46 +0000552
Jon Loeliger89875e92006-10-10 17:03:43 -0500553 switch (speed) {
554 case MIIM_88E1011_PHYSTAT_GBIT:
555 priv->speed = 1000;
556 break;
557 case MIIM_88E1011_PHYSTAT_100:
558 priv->speed = 100;
559 break;
560 default:
561 priv->speed = 10;
wdenk97d80fc2004-06-09 00:34:46 +0000562 }
563
564 return 0;
565}
566
wdenk97d80fc2004-06-09 00:34:46 +0000567/* Parse the cis8201's status register for speed and duplex
Jon Loeliger89875e92006-10-10 17:03:43 -0500568 * information
569 */
570uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
wdenk97d80fc2004-06-09 00:34:46 +0000571{
572 uint speed;
573
Jon Loeliger89875e92006-10-10 17:03:43 -0500574 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
wdenk97d80fc2004-06-09 00:34:46 +0000575 priv->duplexity = 1;
576 else
577 priv->duplexity = 0;
578
579 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
Jon Loeliger89875e92006-10-10 17:03:43 -0500580 switch (speed) {
581 case MIIM_CIS8201_AUXCONSTAT_GBIT:
582 priv->speed = 1000;
583 break;
584 case MIIM_CIS8201_AUXCONSTAT_100:
585 priv->speed = 100;
586 break;
587 default:
588 priv->speed = 10;
589 break;
wdenk97d80fc2004-06-09 00:34:46 +0000590 }
591
592 return 0;
593}
Jon Loeliger89875e92006-10-10 17:03:43 -0500594
Jon Loeligerdebb7352006-04-26 17:58:56 -0500595/* Parse the vsc8244's status register for speed and duplex
Jon Loeliger89875e92006-10-10 17:03:43 -0500596 * information
597 */
598uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500599{
Jon Loeliger89875e92006-10-10 17:03:43 -0500600 uint speed;
601
602 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
603 priv->duplexity = 1;
604 else
605 priv->duplexity = 0;
606
607 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
608 switch (speed) {
609 case MIIM_VSC8244_AUXCONSTAT_GBIT:
610 priv->speed = 1000;
611 break;
612 case MIIM_VSC8244_AUXCONSTAT_100:
613 priv->speed = 100;
614 break;
615 default:
616 priv->speed = 10;
617 break;
618 }
619
620 return 0;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500621}
wdenk97d80fc2004-06-09 00:34:46 +0000622
wdenk97d80fc2004-06-09 00:34:46 +0000623/* Parse the DM9161's status register for speed and duplex
Jon Loeliger89875e92006-10-10 17:03:43 -0500624 * information
625 */
626uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
wdenk97d80fc2004-06-09 00:34:46 +0000627{
Jon Loeliger89875e92006-10-10 17:03:43 -0500628 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
wdenk97d80fc2004-06-09 00:34:46 +0000629 priv->speed = 100;
630 else
631 priv->speed = 10;
632
Jon Loeliger89875e92006-10-10 17:03:43 -0500633 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
wdenk97d80fc2004-06-09 00:34:46 +0000634 priv->duplexity = 1;
635 else
636 priv->duplexity = 0;
637
638 return 0;
639}
640
Jon Loeliger89875e92006-10-10 17:03:43 -0500641/*
642 * Hack to write all 4 PHYs with the LED values
643 */
644uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
wdenk97d80fc2004-06-09 00:34:46 +0000645{
646 uint phyid;
647 volatile tsec_t *regbase = priv->phyregs;
Jon Loeliger89875e92006-10-10 17:03:43 -0500648 int timeout = 1000000;
wdenk97d80fc2004-06-09 00:34:46 +0000649
Jon Loeliger89875e92006-10-10 17:03:43 -0500650 for (phyid = 0; phyid < 4; phyid++) {
wdenk97d80fc2004-06-09 00:34:46 +0000651 regbase->miimadd = (phyid << 8) | mii_reg;
652 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500653 asm("sync");
wdenk97d80fc2004-06-09 00:34:46 +0000654
Jon Loeliger89875e92006-10-10 17:03:43 -0500655 timeout = 1000000;
656 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
wdenk97d80fc2004-06-09 00:34:46 +0000657 }
658
659 return MIIM_CIS8204_SLEDCON_INIT;
660}
661
Jon Loeliger89875e92006-10-10 17:03:43 -0500662uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500663{
664 if (priv->flags & TSEC_REDUCED)
665 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
666 else
667 return MIIM_CIS8204_EPHYCON_INIT;
668}
wdenk97d80fc2004-06-09 00:34:46 +0000669
670/* Initialized required registers to appropriate values, zeroing
671 * those we don't care about (unless zero is bad, in which case,
Jon Loeliger89875e92006-10-10 17:03:43 -0500672 * choose a more appropriate value)
673 */
674static void init_registers(volatile tsec_t * regs)
wdenk42d1f032003-10-15 23:53:47 +0000675{
676 /* Clear IEVENT */
677 regs->ievent = IEVENT_INIT_CLEAR;
678
679 regs->imask = IMASK_INIT_CLEAR;
680
681 regs->hash.iaddr0 = 0;
682 regs->hash.iaddr1 = 0;
683 regs->hash.iaddr2 = 0;
684 regs->hash.iaddr3 = 0;
685 regs->hash.iaddr4 = 0;
686 regs->hash.iaddr5 = 0;
687 regs->hash.iaddr6 = 0;
688 regs->hash.iaddr7 = 0;
689
690 regs->hash.gaddr0 = 0;
691 regs->hash.gaddr1 = 0;
692 regs->hash.gaddr2 = 0;
693 regs->hash.gaddr3 = 0;
694 regs->hash.gaddr4 = 0;
695 regs->hash.gaddr5 = 0;
696 regs->hash.gaddr6 = 0;
697 regs->hash.gaddr7 = 0;
698
699 regs->rctrl = 0x00000000;
700
701 /* Init RMON mib registers */
702 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
703
704 regs->rmon.cam1 = 0xffffffff;
705 regs->rmon.cam2 = 0xffffffff;
706
707 regs->mrblr = MRBLR_INIT_SETTINGS;
708
709 regs->minflr = MINFLR_INIT_SETTINGS;
710
711 regs->attr = ATTR_INIT_SETTINGS;
712 regs->attreli = ATTRELI_INIT_SETTINGS;
713
714}
715
wdenk97d80fc2004-06-09 00:34:46 +0000716/* Configure maccfg2 based on negotiated speed and duplex
Jon Loeliger89875e92006-10-10 17:03:43 -0500717 * reported by PHY handling code
718 */
wdenk97d80fc2004-06-09 00:34:46 +0000719static void adjust_link(struct eth_device *dev)
720{
721 struct tsec_private *priv = (struct tsec_private *)dev->priv;
722 volatile tsec_t *regs = priv->regs;
723
Jon Loeliger89875e92006-10-10 17:03:43 -0500724 if (priv->link) {
725 if (priv->duplexity != 0)
wdenk97d80fc2004-06-09 00:34:46 +0000726 regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
727 else
728 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
729
Jon Loeliger89875e92006-10-10 17:03:43 -0500730 switch (priv->speed) {
731 case 1000:
732 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
733 | MACCFG2_GMII);
734 break;
735 case 100:
736 case 10:
737 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
738 | MACCFG2_MII);
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500739
Nick Spencef484dc72006-09-07 07:39:46 -0700740 /* Set R100 bit in all modes although
741 * it is only used in RGMII mode
Jon Loeliger89875e92006-10-10 17:03:43 -0500742 */
Nick Spencef484dc72006-09-07 07:39:46 -0700743 if (priv->speed == 100)
Jon Loeliger89875e92006-10-10 17:03:43 -0500744 regs->ecntrl |= ECNTRL_R100;
745 else
746 regs->ecntrl &= ~(ECNTRL_R100);
747 break;
748 default:
749 printf("%s: Speed was bad\n", dev->name);
750 break;
wdenk97d80fc2004-06-09 00:34:46 +0000751 }
752
753 printf("Speed: %d, %s duplex\n", priv->speed,
Jon Loeliger89875e92006-10-10 17:03:43 -0500754 (priv->duplexity) ? "full" : "half");
wdenk97d80fc2004-06-09 00:34:46 +0000755
756 } else {
757 printf("%s: No link.\n", dev->name);
758 }
759}
760
wdenk97d80fc2004-06-09 00:34:46 +0000761/* Set up the buffers and their descriptors, and bring up the
Jon Loeliger89875e92006-10-10 17:03:43 -0500762 * interface
763 */
wdenk97d80fc2004-06-09 00:34:46 +0000764static void startup_tsec(struct eth_device *dev)
wdenk42d1f032003-10-15 23:53:47 +0000765{
766 int i;
wdenk97d80fc2004-06-09 00:34:46 +0000767 struct tsec_private *priv = (struct tsec_private *)dev->priv;
768 volatile tsec_t *regs = priv->regs;
wdenk42d1f032003-10-15 23:53:47 +0000769
770 /* Point to the buffer descriptors */
771 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
772 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
773
774 /* Initialize the Rx Buffer descriptors */
775 for (i = 0; i < PKTBUFSRX; i++) {
776 rtx.rxbd[i].status = RXBD_EMPTY;
777 rtx.rxbd[i].length = 0;
Jon Loeliger89875e92006-10-10 17:03:43 -0500778 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
wdenk42d1f032003-10-15 23:53:47 +0000779 }
Jon Loeliger89875e92006-10-10 17:03:43 -0500780 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
wdenk42d1f032003-10-15 23:53:47 +0000781
782 /* Initialize the TX Buffer Descriptors */
Jon Loeliger89875e92006-10-10 17:03:43 -0500783 for (i = 0; i < TX_BUF_CNT; i++) {
wdenk42d1f032003-10-15 23:53:47 +0000784 rtx.txbd[i].status = 0;
785 rtx.txbd[i].length = 0;
786 rtx.txbd[i].bufPtr = 0;
787 }
Jon Loeliger89875e92006-10-10 17:03:43 -0500788 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
wdenk42d1f032003-10-15 23:53:47 +0000789
wdenk97d80fc2004-06-09 00:34:46 +0000790 /* Start up the PHY */
Ben Warren4653f912006-10-26 14:38:25 -0400791 if(priv->phyinfo)
792 phy_run_commands(priv, priv->phyinfo->startup);
David Updegraffaf1c2b82007-04-20 14:34:48 -0500793
wdenk97d80fc2004-06-09 00:34:46 +0000794 adjust_link(dev);
795
wdenk42d1f032003-10-15 23:53:47 +0000796 /* Enable Transmit and Receive */
797 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
798
799 /* Tell the DMA it is clear to go */
800 regs->dmactrl |= DMACTRL_INIT_SETTINGS;
801 regs->tstat = TSTAT_CLEAR_THALT;
802 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
803}
804
wdenk9d46ea42005-03-14 23:56:42 +0000805/* This returns the status bits of the device. The return value
wdenk42d1f032003-10-15 23:53:47 +0000806 * is never checked, and this is what the 8260 driver did, so we
wdenk9d46ea42005-03-14 23:56:42 +0000807 * do the same. Presumably, this would be zero if there were no
Jon Loeliger89875e92006-10-10 17:03:43 -0500808 * errors
809 */
810static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
wdenk42d1f032003-10-15 23:53:47 +0000811{
812 int i;
813 int result = 0;
wdenk97d80fc2004-06-09 00:34:46 +0000814 struct tsec_private *priv = (struct tsec_private *)dev->priv;
815 volatile tsec_t *regs = priv->regs;
wdenk42d1f032003-10-15 23:53:47 +0000816
817 /* Find an empty buffer descriptor */
Jon Loeliger89875e92006-10-10 17:03:43 -0500818 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
wdenk42d1f032003-10-15 23:53:47 +0000819 if (i >= TOUT_LOOP) {
Jon Loeliger89875e92006-10-10 17:03:43 -0500820 debug("%s: tsec: tx buffers full\n", dev->name);
wdenk42d1f032003-10-15 23:53:47 +0000821 return result;
822 }
823 }
824
Jon Loeliger89875e92006-10-10 17:03:43 -0500825 rtx.txbd[txIdx].bufPtr = (uint) packet;
wdenk42d1f032003-10-15 23:53:47 +0000826 rtx.txbd[txIdx].length = length;
Jon Loeliger89875e92006-10-10 17:03:43 -0500827 rtx.txbd[txIdx].status |=
828 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
wdenk42d1f032003-10-15 23:53:47 +0000829
830 /* Tell the DMA to go */
831 regs->tstat = TSTAT_CLEAR_THALT;
832
833 /* Wait for buffer to be transmitted */
Jon Loeliger89875e92006-10-10 17:03:43 -0500834 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
wdenk42d1f032003-10-15 23:53:47 +0000835 if (i >= TOUT_LOOP) {
Jon Loeliger89875e92006-10-10 17:03:43 -0500836 debug("%s: tsec: tx error\n", dev->name);
wdenk42d1f032003-10-15 23:53:47 +0000837 return result;
838 }
839 }
840
841 txIdx = (txIdx + 1) % TX_BUF_CNT;
842 result = rtx.txbd[txIdx].status & TXBD_STATS;
843
844 return result;
845}
846
Jon Loeliger89875e92006-10-10 17:03:43 -0500847static int tsec_recv(struct eth_device *dev)
wdenk42d1f032003-10-15 23:53:47 +0000848{
849 int length;
wdenk97d80fc2004-06-09 00:34:46 +0000850 struct tsec_private *priv = (struct tsec_private *)dev->priv;
851 volatile tsec_t *regs = priv->regs;
wdenk42d1f032003-10-15 23:53:47 +0000852
Jon Loeliger89875e92006-10-10 17:03:43 -0500853 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
wdenk42d1f032003-10-15 23:53:47 +0000854
855 length = rtx.rxbd[rxIdx].length;
856
857 /* Send the packet up if there were no errors */
858 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
859 NetReceive(NetRxPackets[rxIdx], length - 4);
wdenk97d80fc2004-06-09 00:34:46 +0000860 } else {
861 printf("Got error %x\n",
Jon Loeliger89875e92006-10-10 17:03:43 -0500862 (rtx.rxbd[rxIdx].status & RXBD_STATS));
wdenk42d1f032003-10-15 23:53:47 +0000863 }
864
865 rtx.rxbd[rxIdx].length = 0;
866
867 /* Set the wrap bit if this is the last element in the list */
Jon Loeliger89875e92006-10-10 17:03:43 -0500868 rtx.rxbd[rxIdx].status =
869 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
wdenk42d1f032003-10-15 23:53:47 +0000870
871 rxIdx = (rxIdx + 1) % PKTBUFSRX;
872 }
873
Jon Loeliger89875e92006-10-10 17:03:43 -0500874 if (regs->ievent & IEVENT_BSY) {
wdenk42d1f032003-10-15 23:53:47 +0000875 regs->ievent = IEVENT_BSY;
876 regs->rstat = RSTAT_CLEAR_RHALT;
877 }
878
879 return -1;
880
881}
882
wdenk97d80fc2004-06-09 00:34:46 +0000883/* Stop the interface */
Jon Loeliger89875e92006-10-10 17:03:43 -0500884static void tsec_halt(struct eth_device *dev)
wdenk42d1f032003-10-15 23:53:47 +0000885{
wdenk97d80fc2004-06-09 00:34:46 +0000886 struct tsec_private *priv = (struct tsec_private *)dev->priv;
887 volatile tsec_t *regs = priv->regs;
wdenk42d1f032003-10-15 23:53:47 +0000888
889 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
890 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
891
Jon Loeliger89875e92006-10-10 17:03:43 -0500892 while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
wdenk42d1f032003-10-15 23:53:47 +0000893
894 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
895
wdenk97d80fc2004-06-09 00:34:46 +0000896 /* Shut down the PHY, as needed */
Ben Warren4653f912006-10-26 14:38:25 -0400897 if(priv->phyinfo)
898 phy_run_commands(priv, priv->phyinfo->shutdown);
wdenk42d1f032003-10-15 23:53:47 +0000899}
wdenk7abf0c52004-04-18 21:45:42 +0000900
Andy Flemingc7e717e2007-08-03 04:05:25 -0500901struct phy_info phy_info_M88E1149S = {
Wolfgang Denk5728be32007-08-06 01:01:49 +0200902 0x1410ca,
903 "Marvell 88E1149S",
904 4,
905 (struct phy_cmd[]){ /* config */
906 /* Reset and configure the PHY */
907 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
908 {0x1d, 0x1f, NULL},
909 {0x1e, 0x200c, NULL},
910 {0x1d, 0x5, NULL},
911 {0x1e, 0x0, NULL},
912 {0x1e, 0x100, NULL},
913 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
914 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
915 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
916 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
917 {miim_end,}
918 },
919 (struct phy_cmd[]){ /* startup */
920 /* Status is read once to clear old link state */
921 {MIIM_STATUS, miim_read, NULL},
922 /* Auto-negotiate */
923 {MIIM_STATUS, miim_read, &mii_parse_sr},
924 /* Read the status */
925 {MIIM_88E1011_PHY_STATUS, miim_read,
926 &mii_parse_88E1011_psr},
927 {miim_end,}
928 },
929 (struct phy_cmd[]){ /* shutdown */
930 {miim_end,}
931 },
Andy Flemingc7e717e2007-08-03 04:05:25 -0500932};
933
Paul Gortmaker91e25762007-01-16 11:38:14 -0500934/* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
935struct phy_info phy_info_BCM5461S = {
936 0x02060c1, /* 5461 ID */
937 "Broadcom BCM5461S",
938 0, /* not clear to me what minor revisions we can shift away */
939 (struct phy_cmd[]) { /* config */
940 /* Reset and configure the PHY */
941 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
942 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
943 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
944 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
945 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
946 {miim_end,}
947 },
948 (struct phy_cmd[]) { /* startup */
949 /* Status is read once to clear old link state */
950 {MIIM_STATUS, miim_read, NULL},
951 /* Auto-negotiate */
952 {MIIM_STATUS, miim_read, &mii_parse_sr},
953 /* Read the status */
954 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
955 {miim_end,}
956 },
957 (struct phy_cmd[]) { /* shutdown */
958 {miim_end,}
959 },
960};
961
Joe Hammanc3243cf2007-04-30 16:47:28 -0500962struct phy_info phy_info_BCM5464S = {
963 0x02060b1, /* 5464 ID */
964 "Broadcom BCM5464S",
965 0, /* not clear to me what minor revisions we can shift away */
966 (struct phy_cmd[]) { /* config */
967 /* Reset and configure the PHY */
968 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
969 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
970 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
971 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
972 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
973 {miim_end,}
974 },
975 (struct phy_cmd[]) { /* startup */
976 /* Status is read once to clear old link state */
977 {MIIM_STATUS, miim_read, NULL},
978 /* Auto-negotiate */
979 {MIIM_STATUS, miim_read, &mii_parse_sr},
980 /* Read the status */
981 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
982 {miim_end,}
983 },
984 (struct phy_cmd[]) { /* shutdown */
985 {miim_end,}
986 },
987};
988
wdenk97d80fc2004-06-09 00:34:46 +0000989struct phy_info phy_info_M88E1011S = {
990 0x01410c6,
991 "Marvell 88E1011S",
992 4,
Jon Loeliger89875e92006-10-10 17:03:43 -0500993 (struct phy_cmd[]){ /* config */
994 /* Reset and configure the PHY */
995 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
996 {0x1d, 0x1f, NULL},
997 {0x1e, 0x200c, NULL},
998 {0x1d, 0x5, NULL},
999 {0x1e, 0x0, NULL},
1000 {0x1e, 0x100, NULL},
1001 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1002 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1003 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1004 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1005 {miim_end,}
1006 },
1007 (struct phy_cmd[]){ /* startup */
1008 /* Status is read once to clear old link state */
1009 {MIIM_STATUS, miim_read, NULL},
1010 /* Auto-negotiate */
1011 {MIIM_STATUS, miim_read, &mii_parse_sr},
1012 /* Read the status */
1013 {MIIM_88E1011_PHY_STATUS, miim_read,
1014 &mii_parse_88E1011_psr},
1015 {miim_end,}
1016 },
1017 (struct phy_cmd[]){ /* shutdown */
1018 {miim_end,}
1019 },
wdenk97d80fc2004-06-09 00:34:46 +00001020};
1021
wdenk9d46ea42005-03-14 23:56:42 +00001022struct phy_info phy_info_M88E1111S = {
1023 0x01410cc,
1024 "Marvell 88E1111S",
1025 4,
Jon Loeliger89875e92006-10-10 17:03:43 -05001026 (struct phy_cmd[]){ /* config */
1027 /* Reset and configure the PHY */
1028 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
Nick Spencef484dc72006-09-07 07:39:46 -07001029 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
Jon Loeliger89875e92006-10-10 17:03:43 -05001030 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1031 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1032 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1033 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1034 {miim_end,}
1035 },
1036 (struct phy_cmd[]){ /* startup */
1037 /* Status is read once to clear old link state */
1038 {MIIM_STATUS, miim_read, NULL},
1039 /* Auto-negotiate */
1040 {MIIM_STATUS, miim_read, &mii_parse_sr},
1041 /* Read the status */
1042 {MIIM_88E1011_PHY_STATUS, miim_read,
1043 &mii_parse_88E1011_psr},
1044 {miim_end,}
1045 },
1046 (struct phy_cmd[]){ /* shutdown */
1047 {miim_end,}
1048 },
wdenk9d46ea42005-03-14 23:56:42 +00001049};
1050
Andy Fleming09f3e092006-09-13 10:34:18 -05001051static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
1052{
Andy Fleming09f3e092006-09-13 10:34:18 -05001053 uint mii_data = read_phy_reg(priv, mii_reg);
1054
Andy Fleming09f3e092006-09-13 10:34:18 -05001055 /* Setting MIIM_88E1145_PHY_EXT_CR */
1056 if (priv->flags & TSEC_REDUCED)
1057 return mii_data |
Jon Loeliger89875e92006-10-10 17:03:43 -05001058 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
Andy Fleming09f3e092006-09-13 10:34:18 -05001059 else
1060 return mii_data;
1061}
1062
1063static struct phy_info phy_info_M88E1145 = {
1064 0x01410cd,
1065 "Marvell 88E1145",
1066 4,
Jon Loeliger89875e92006-10-10 17:03:43 -05001067 (struct phy_cmd[]){ /* config */
Andy Fleming7507d562007-05-08 17:23:02 -05001068 /* Reset the PHY */
1069 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1070
Jon Loeliger89875e92006-10-10 17:03:43 -05001071 /* Errata E0, E1 */
1072 {29, 0x001b, NULL},
1073 {30, 0x418f, NULL},
1074 {29, 0x0016, NULL},
1075 {30, 0xa2da, NULL},
Andy Fleming09f3e092006-09-13 10:34:18 -05001076
Andy Fleming7507d562007-05-08 17:23:02 -05001077 /* Configure the PHY */
Jon Loeliger89875e92006-10-10 17:03:43 -05001078 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1079 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1080 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
1081 NULL},
1082 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
1083 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1084 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
1085 {miim_end,}
1086 },
1087 (struct phy_cmd[]){ /* startup */
1088 /* Status is read once to clear old link state */
1089 {MIIM_STATUS, miim_read, NULL},
1090 /* Auto-negotiate */
1091 {MIIM_STATUS, miim_read, &mii_parse_sr},
1092 {MIIM_88E1111_PHY_LED_CONTROL,
1093 MIIM_88E1111_PHY_LED_DIRECT, NULL},
1094 /* Read the Status */
1095 {MIIM_88E1011_PHY_STATUS, miim_read,
1096 &mii_parse_88E1011_psr},
1097 {miim_end,}
1098 },
1099 (struct phy_cmd[]){ /* shutdown */
1100 {miim_end,}
1101 },
Andy Fleming09f3e092006-09-13 10:34:18 -05001102};
1103
wdenk97d80fc2004-06-09 00:34:46 +00001104struct phy_info phy_info_cis8204 = {
1105 0x3f11,
1106 "Cicada Cis8204",
1107 6,
Jon Loeliger89875e92006-10-10 17:03:43 -05001108 (struct phy_cmd[]){ /* config */
1109 /* Override PHY config settings */
1110 {MIIM_CIS8201_AUX_CONSTAT,
1111 MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1112 /* Configure some basic stuff */
1113 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1114 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
1115 &mii_cis8204_fixled},
1116 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
1117 &mii_cis8204_setmode},
1118 {miim_end,}
1119 },
1120 (struct phy_cmd[]){ /* startup */
1121 /* Read the Status (2x to make sure link is right) */
1122 {MIIM_STATUS, miim_read, NULL},
1123 /* Auto-negotiate */
1124 {MIIM_STATUS, miim_read, &mii_parse_sr},
1125 /* Read the status */
1126 {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1127 &mii_parse_cis8201},
1128 {miim_end,}
1129 },
1130 (struct phy_cmd[]){ /* shutdown */
1131 {miim_end,}
1132 },
wdenk97d80fc2004-06-09 00:34:46 +00001133};
1134
1135/* Cicada 8201 */
1136struct phy_info phy_info_cis8201 = {
1137 0xfc41,
1138 "CIS8201",
1139 4,
Jon Loeliger89875e92006-10-10 17:03:43 -05001140 (struct phy_cmd[]){ /* config */
1141 /* Override PHY config settings */
1142 {MIIM_CIS8201_AUX_CONSTAT,
1143 MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1144 /* Set up the interface mode */
1145 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT,
1146 NULL},
1147 /* Configure some basic stuff */
1148 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1149 {miim_end,}
1150 },
1151 (struct phy_cmd[]){ /* startup */
1152 /* Read the Status (2x to make sure link is right) */
1153 {MIIM_STATUS, miim_read, NULL},
1154 /* Auto-negotiate */
1155 {MIIM_STATUS, miim_read, &mii_parse_sr},
1156 /* Read the status */
1157 {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1158 &mii_parse_cis8201},
1159 {miim_end,}
1160 },
1161 (struct phy_cmd[]){ /* shutdown */
1162 {miim_end,}
1163 },
wdenk97d80fc2004-06-09 00:34:46 +00001164};
Jon Loeligerdebb7352006-04-26 17:58:56 -05001165struct phy_info phy_info_VSC8244 = {
Jon Loeliger89875e92006-10-10 17:03:43 -05001166 0x3f1b,
1167 "Vitesse VSC8244",
1168 6,
1169 (struct phy_cmd[]){ /* config */
1170 /* Override PHY config settings */
1171 /* Configure some basic stuff */
1172 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1173 {miim_end,}
1174 },
1175 (struct phy_cmd[]){ /* startup */
1176 /* Read the Status (2x to make sure link is right) */
1177 {MIIM_STATUS, miim_read, NULL},
1178 /* Auto-negotiate */
1179 {MIIM_STATUS, miim_read, &mii_parse_sr},
1180 /* Read the status */
1181 {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1182 &mii_parse_vsc8244},
1183 {miim_end,}
1184 },
1185 (struct phy_cmd[]){ /* shutdown */
1186 {miim_end,}
1187 },
Jon Loeligerdebb7352006-04-26 17:58:56 -05001188};
wdenk97d80fc2004-06-09 00:34:46 +00001189
wdenk97d80fc2004-06-09 00:34:46 +00001190struct phy_info phy_info_dm9161 = {
1191 0x0181b88,
1192 "Davicom DM9161E",
1193 4,
Jon Loeliger89875e92006-10-10 17:03:43 -05001194 (struct phy_cmd[]){ /* config */
1195 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
1196 /* Do not bypass the scrambler/descrambler */
1197 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
1198 /* Clear 10BTCSR to default */
1199 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT,
1200 NULL},
1201 /* Configure some basic stuff */
1202 {MIIM_CONTROL, MIIM_CR_INIT, NULL},
1203 /* Restart Auto Negotiation */
1204 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
1205 {miim_end,}
1206 },
1207 (struct phy_cmd[]){ /* startup */
1208 /* Status is read once to clear old link state */
1209 {MIIM_STATUS, miim_read, NULL},
1210 /* Auto-negotiate */
1211 {MIIM_STATUS, miim_read, &mii_parse_sr},
1212 /* Read the status */
1213 {MIIM_DM9161_SCSR, miim_read,
1214 &mii_parse_dm9161_scsr},
1215 {miim_end,}
1216 },
1217 (struct phy_cmd[]){ /* shutdown */
1218 {miim_end,}
1219 },
wdenk97d80fc2004-06-09 00:34:46 +00001220};
David Updegraffaf1c2b82007-04-20 14:34:48 -05001221/* a generic flavor. */
1222struct phy_info phy_info_generic = {
1223 0,
1224 "Unknown/Generic PHY",
1225 32,
1226 (struct phy_cmd[]) { /* config */
1227 {PHY_BMCR, PHY_BMCR_RESET, NULL},
1228 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
1229 {miim_end,}
1230 },
1231 (struct phy_cmd[]) { /* startup */
1232 {PHY_BMSR, miim_read, NULL},
1233 {PHY_BMSR, miim_read, &mii_parse_sr},
1234 {PHY_BMSR, miim_read, &mii_parse_link},
1235 {miim_end,}
1236 },
1237 (struct phy_cmd[]) { /* shutdown */
1238 {miim_end,}
1239 }
1240};
1241
wdenk97d80fc2004-06-09 00:34:46 +00001242
wdenk3dd7f0f2005-04-04 23:43:44 +00001243uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1244{
wdenk3c2b3d42005-04-05 23:32:21 +00001245 unsigned int speed;
1246 if (priv->link) {
1247 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
wdenk3dd7f0f2005-04-04 23:43:44 +00001248
wdenk3c2b3d42005-04-05 23:32:21 +00001249 switch (speed) {
1250 case MIIM_LXT971_SR2_10HDX:
1251 priv->speed = 10;
1252 priv->duplexity = 0;
1253 break;
1254 case MIIM_LXT971_SR2_10FDX:
1255 priv->speed = 10;
1256 priv->duplexity = 1;
1257 break;
1258 case MIIM_LXT971_SR2_100HDX:
1259 priv->speed = 100;
1260 priv->duplexity = 0;
1261 default:
1262 priv->speed = 100;
1263 priv->duplexity = 1;
1264 break;
1265 }
1266 } else {
1267 priv->speed = 0;
1268 priv->duplexity = 0;
1269 }
wdenk3dd7f0f2005-04-04 23:43:44 +00001270
wdenk3c2b3d42005-04-05 23:32:21 +00001271 return 0;
wdenk3dd7f0f2005-04-04 23:43:44 +00001272}
1273
wdenk9d46ea42005-03-14 23:56:42 +00001274static struct phy_info phy_info_lxt971 = {
1275 0x0001378e,
1276 "LXT971",
1277 4,
Jon Loeliger89875e92006-10-10 17:03:43 -05001278 (struct phy_cmd[]){ /* config */
1279 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */
1280 {miim_end,}
1281 },
1282 (struct phy_cmd[]){ /* startup - enable interrupts */
1283 /* { 0x12, 0x00f2, NULL }, */
1284 {MIIM_STATUS, miim_read, NULL},
1285 {MIIM_STATUS, miim_read, &mii_parse_sr},
1286 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
1287 {miim_end,}
1288 },
1289 (struct phy_cmd[]){ /* shutdown - disable interrupts */
1290 {miim_end,}
1291 },
wdenk9d46ea42005-03-14 23:56:42 +00001292};
1293
Wolfgang Denkbe5048f2006-03-12 22:50:55 +01001294/* Parse the DP83865's link and auto-neg status register for speed and duplex
Jon Loeliger89875e92006-10-10 17:03:43 -05001295 * information
1296 */
Wolfgang Denkbe5048f2006-03-12 22:50:55 +01001297uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1298{
1299 switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1300
1301 case MIIM_DP83865_SPD_1000:
1302 priv->speed = 1000;
1303 break;
1304
1305 case MIIM_DP83865_SPD_100:
1306 priv->speed = 100;
1307 break;
1308
1309 default:
1310 priv->speed = 10;
1311 break;
1312
1313 }
1314
1315 if (mii_reg & MIIM_DP83865_DPX_FULL)
1316 priv->duplexity = 1;
1317 else
1318 priv->duplexity = 0;
1319
1320 return 0;
1321}
1322
1323struct phy_info phy_info_dp83865 = {
1324 0x20005c7,
1325 "NatSemi DP83865",
1326 4,
Jon Loeliger89875e92006-10-10 17:03:43 -05001327 (struct phy_cmd[]){ /* config */
1328 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1329 {miim_end,}
1330 },
1331 (struct phy_cmd[]){ /* startup */
1332 /* Status is read once to clear old link state */
1333 {MIIM_STATUS, miim_read, NULL},
1334 /* Auto-negotiate */
1335 {MIIM_STATUS, miim_read, &mii_parse_sr},
1336 /* Read the link and auto-neg status */
1337 {MIIM_DP83865_LANR, miim_read,
1338 &mii_parse_dp83865_lanr},
1339 {miim_end,}
1340 },
1341 (struct phy_cmd[]){ /* shutdown */
1342 {miim_end,}
1343 },
Wolfgang Denkbe5048f2006-03-12 22:50:55 +01001344};
1345
wdenk97d80fc2004-06-09 00:34:46 +00001346struct phy_info *phy_info[] = {
wdenk97d80fc2004-06-09 00:34:46 +00001347 &phy_info_cis8204,
Timur Tabi2ad6b512006-10-31 18:44:42 -06001348 &phy_info_cis8201,
Paul Gortmaker91e25762007-01-16 11:38:14 -05001349 &phy_info_BCM5461S,
Joe Hammanc3243cf2007-04-30 16:47:28 -05001350 &phy_info_BCM5464S,
wdenk97d80fc2004-06-09 00:34:46 +00001351 &phy_info_M88E1011S,
wdenk9d46ea42005-03-14 23:56:42 +00001352 &phy_info_M88E1111S,
Andy Fleming09f3e092006-09-13 10:34:18 -05001353 &phy_info_M88E1145,
Wolfgang Denk5728be32007-08-06 01:01:49 +02001354 &phy_info_M88E1149S,
wdenk97d80fc2004-06-09 00:34:46 +00001355 &phy_info_dm9161,
wdenk9d46ea42005-03-14 23:56:42 +00001356 &phy_info_lxt971,
Jon Loeligerdebb7352006-04-26 17:58:56 -05001357 &phy_info_VSC8244,
Wolfgang Denkbe5048f2006-03-12 22:50:55 +01001358 &phy_info_dp83865,
David Updegraffaf1c2b82007-04-20 14:34:48 -05001359 &phy_info_generic,
wdenk97d80fc2004-06-09 00:34:46 +00001360 NULL
1361};
1362
wdenk97d80fc2004-06-09 00:34:46 +00001363/* Grab the identifier of the device's PHY, and search through
wdenk9d46ea42005-03-14 23:56:42 +00001364 * all of the known PHYs to see if one matches. If so, return
Jon Loeliger89875e92006-10-10 17:03:43 -05001365 * it, if not, return NULL
1366 */
1367struct phy_info *get_phy_info(struct eth_device *dev)
wdenk97d80fc2004-06-09 00:34:46 +00001368{
1369 struct tsec_private *priv = (struct tsec_private *)dev->priv;
1370 uint phy_reg, phy_ID;
1371 int i;
1372 struct phy_info *theInfo = NULL;
1373
1374 /* Grab the bits from PHYIR1, and put them in the upper half */
1375 phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1376 phy_ID = (phy_reg & 0xffff) << 16;
1377
1378 /* Grab the bits from PHYIR2, and put them in the lower half */
1379 phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1380 phy_ID |= (phy_reg & 0xffff);
1381
1382 /* loop through all the known PHY types, and find one that */
1383 /* matches the ID we read from the PHY. */
Jon Loeliger89875e92006-10-10 17:03:43 -05001384 for (i = 0; phy_info[i]; i++) {
Andy Fleming2a3cee42007-05-09 00:54:20 -05001385 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
wdenk97d80fc2004-06-09 00:34:46 +00001386 theInfo = phy_info[i];
Andy Fleming2a3cee42007-05-09 00:54:20 -05001387 break;
1388 }
wdenk97d80fc2004-06-09 00:34:46 +00001389 }
1390
Jon Loeliger89875e92006-10-10 17:03:43 -05001391 if (theInfo == NULL) {
wdenk97d80fc2004-06-09 00:34:46 +00001392 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
1393 return NULL;
1394 } else {
Stefan Roese5810dc32005-09-21 18:20:22 +02001395 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
wdenk97d80fc2004-06-09 00:34:46 +00001396 }
1397
1398 return theInfo;
1399}
1400
wdenk97d80fc2004-06-09 00:34:46 +00001401/* Execute the given series of commands on the given device's
Jon Loeliger89875e92006-10-10 17:03:43 -05001402 * PHY, running functions as necessary
1403 */
wdenk97d80fc2004-06-09 00:34:46 +00001404void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1405{
1406 int i;
1407 uint result;
1408 volatile tsec_t *phyregs = priv->phyregs;
1409
1410 phyregs->miimcfg = MIIMCFG_RESET;
1411
1412 phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1413
Jon Loeliger89875e92006-10-10 17:03:43 -05001414 while (phyregs->miimind & MIIMIND_BUSY) ;
wdenk97d80fc2004-06-09 00:34:46 +00001415
Jon Loeliger89875e92006-10-10 17:03:43 -05001416 for (i = 0; cmd->mii_reg != miim_end; i++) {
1417 if (cmd->mii_data == miim_read) {
wdenk97d80fc2004-06-09 00:34:46 +00001418 result = read_phy_reg(priv, cmd->mii_reg);
1419
Jon Loeliger89875e92006-10-10 17:03:43 -05001420 if (cmd->funct != NULL)
1421 (*(cmd->funct)) (result, priv);
wdenk97d80fc2004-06-09 00:34:46 +00001422
1423 } else {
Jon Loeliger89875e92006-10-10 17:03:43 -05001424 if (cmd->funct != NULL)
1425 result = (*(cmd->funct)) (cmd->mii_reg, priv);
wdenk97d80fc2004-06-09 00:34:46 +00001426 else
1427 result = cmd->mii_data;
1428
1429 write_phy_reg(priv, cmd->mii_reg, result);
1430
1431 }
1432 cmd++;
1433 }
1434}
1435
wdenk97d80fc2004-06-09 00:34:46 +00001436/* Relocate the function pointers in the phy cmd lists */
1437static void relocate_cmds(void)
1438{
1439 struct phy_cmd **cmdlistptr;
1440 struct phy_cmd *cmd;
Jon Loeliger89875e92006-10-10 17:03:43 -05001441 int i, j, k;
wdenk97d80fc2004-06-09 00:34:46 +00001442
Jon Loeliger89875e92006-10-10 17:03:43 -05001443 for (i = 0; phy_info[i]; i++) {
wdenk97d80fc2004-06-09 00:34:46 +00001444 /* First thing's first: relocate the pointers to the
1445 * PHY command structures (the structs were done) */
Jon Loeliger89875e92006-10-10 17:03:43 -05001446 phy_info[i] = (struct phy_info *)((uint) phy_info[i]
1447 + gd->reloc_off);
wdenk97d80fc2004-06-09 00:34:46 +00001448 phy_info[i]->name += gd->reloc_off;
1449 phy_info[i]->config =
Jon Loeliger89875e92006-10-10 17:03:43 -05001450 (struct phy_cmd *)((uint) phy_info[i]->config
1451 + gd->reloc_off);
wdenk97d80fc2004-06-09 00:34:46 +00001452 phy_info[i]->startup =
Jon Loeliger89875e92006-10-10 17:03:43 -05001453 (struct phy_cmd *)((uint) phy_info[i]->startup
1454 + gd->reloc_off);
wdenk97d80fc2004-06-09 00:34:46 +00001455 phy_info[i]->shutdown =
Jon Loeliger89875e92006-10-10 17:03:43 -05001456 (struct phy_cmd *)((uint) phy_info[i]->shutdown
1457 + gd->reloc_off);
wdenk97d80fc2004-06-09 00:34:46 +00001458
1459 cmdlistptr = &phy_info[i]->config;
Jon Loeliger89875e92006-10-10 17:03:43 -05001460 j = 0;
1461 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) {
1462 k = 0;
1463 for (cmd = *cmdlistptr;
1464 cmd->mii_reg != miim_end;
1465 cmd++) {
wdenk97d80fc2004-06-09 00:34:46 +00001466 /* Only relocate non-NULL pointers */
Jon Loeliger89875e92006-10-10 17:03:43 -05001467 if (cmd->funct)
wdenk97d80fc2004-06-09 00:34:46 +00001468 cmd->funct += gd->reloc_off;
1469
1470 k++;
1471 }
1472 j++;
1473 }
1474 }
1475
1476 relocated = 1;
1477}
1478
Jon Loeligercb51c0b2007-07-09 17:39:42 -05001479#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001480 && !defined(BITBANGMII)
wdenk97d80fc2004-06-09 00:34:46 +00001481
Jon Loeliger89875e92006-10-10 17:03:43 -05001482struct tsec_private *get_priv_for_phy(unsigned char phyaddr)
wdenk97d80fc2004-06-09 00:34:46 +00001483{
1484 int i;
1485
Jon Loeliger89875e92006-10-10 17:03:43 -05001486 for (i = 0; i < MAXCONTROLLERS; i++) {
1487 if (privlist[i]->phyaddr == phyaddr)
wdenk97d80fc2004-06-09 00:34:46 +00001488 return privlist[i];
1489 }
1490
1491 return NULL;
1492}
1493
wdenk7abf0c52004-04-18 21:45:42 +00001494/*
1495 * Read a MII PHY register.
1496 *
1497 * Returns:
wdenk97d80fc2004-06-09 00:34:46 +00001498 * 0 on success
wdenk7abf0c52004-04-18 21:45:42 +00001499 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001500static int tsec_miiphy_read(char *devname, unsigned char addr,
Jon Loeliger89875e92006-10-10 17:03:43 -05001501 unsigned char reg, unsigned short *value)
wdenk7abf0c52004-04-18 21:45:42 +00001502{
wdenk97d80fc2004-06-09 00:34:46 +00001503 unsigned short ret;
1504 struct tsec_private *priv = get_priv_for_phy(addr);
wdenk7abf0c52004-04-18 21:45:42 +00001505
Jon Loeliger89875e92006-10-10 17:03:43 -05001506 if (NULL == priv) {
wdenk97d80fc2004-06-09 00:34:46 +00001507 printf("Can't read PHY at address %d\n", addr);
1508 return -1;
1509 }
1510
1511 ret = (unsigned short)read_phy_reg(priv, reg);
1512 *value = ret;
wdenk7abf0c52004-04-18 21:45:42 +00001513
1514 return 0;
1515}
1516
1517/*
1518 * Write a MII PHY register.
1519 *
1520 * Returns:
wdenk97d80fc2004-06-09 00:34:46 +00001521 * 0 on success
wdenk7abf0c52004-04-18 21:45:42 +00001522 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001523static int tsec_miiphy_write(char *devname, unsigned char addr,
Jon Loeliger89875e92006-10-10 17:03:43 -05001524 unsigned char reg, unsigned short value)
wdenk7abf0c52004-04-18 21:45:42 +00001525{
wdenk97d80fc2004-06-09 00:34:46 +00001526 struct tsec_private *priv = get_priv_for_phy(addr);
wdenk7abf0c52004-04-18 21:45:42 +00001527
Jon Loeliger89875e92006-10-10 17:03:43 -05001528 if (NULL == priv) {
wdenk97d80fc2004-06-09 00:34:46 +00001529 printf("Can't write PHY at address %d\n", addr);
1530 return -1;
1531 }
1532
1533 write_phy_reg(priv, reg, value);
wdenk7abf0c52004-04-18 21:45:42 +00001534
1535 return 0;
1536}
wdenk97d80fc2004-06-09 00:34:46 +00001537
Jon Loeligercb51c0b2007-07-09 17:39:42 -05001538#endif
wdenk97d80fc2004-06-09 00:34:46 +00001539
David Updegraff53a5c422007-06-11 10:41:07 -05001540#ifdef CONFIG_MCAST_TFTP
1541
1542/* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
1543
1544/* Set the appropriate hash bit for the given addr */
1545
1546/* The algorithm works like so:
1547 * 1) Take the Destination Address (ie the multicast address), and
1548 * do a CRC on it (little endian), and reverse the bits of the
1549 * result.
1550 * 2) Use the 8 most significant bits as a hash into a 256-entry
1551 * table. The table is controlled through 8 32-bit registers:
1552 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1553 * gaddr7. This means that the 3 most significant bits in the
1554 * hash index which gaddr register to use, and the 5 other bits
1555 * indicate which bit (assuming an IBM numbering scheme, which
1556 * for PowerPC (tm) is usually the case) in the tregister holds
1557 * the entry. */
1558static int
1559tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
1560{
1561 struct tsec_private *priv = privlist[1];
1562 volatile tsec_t *regs = priv->regs;
1563 volatile u32 *reg_array, value;
1564 u8 result, whichbit, whichreg;
1565
1566 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff);
1567 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */
1568 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */
1569 value = (1 << (31-whichbit));
1570
1571 reg_array = &(regs->hash.gaddr0);
1572
1573 if (set) {
1574 reg_array[whichreg] |= value;
1575 } else {
1576 reg_array[whichreg] &= ~value;
1577 }
1578 return 0;
1579}
1580#endif /* Multicast TFTP ? */
1581
wdenk42d1f032003-10-15 23:53:47 +00001582#endif /* CONFIG_TSEC_ENET */