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Anatolij Gustschin4387cf12012-08-31 01:29:57 +00001/*
2 * Partially derived from board code for digsyMTC,
3 * (C) Copyright 2009
4 * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
5 *
6 * (C) Copyright 2012
7 * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <mpc5xxx.h>
30#include <asm/processor.h>
31#include <asm/io.h>
32#include <libfdt.h>
33#include <fdt_support.h>
34#include <i2c.h>
35#include <miiphy.h>
36#include <net.h>
37#include <pci.h>
38
39DECLARE_GLOBAL_DATA_PTR;
40
41#define SDRAM_MODE 0x00CD0000
42#define SDRAM_CONTROL 0x504F0000
43#define SDRAM_CONFIG1 0xD2322800
44#define SDRAM_CONFIG2 0x8AD70000
45
46enum ifm_sensor_type {
47 O2DNT = 0x00, /* !< O2DNT 32MB */
48 O2DNT2 = 0x01, /* !< O2DNT2 64MB */
49 O3DNT = 0x02, /* !< O3DNT 32MB */
50 O3DNT_MIN = 0x40, /* !< O3DNT Minerva 32MB */
51 UNKNOWN = 0xff, /* !< Unknow sensor */
52};
53
54static enum ifm_sensor_type gt_ifm_sensor_type;
55
56#ifndef CONFIG_SYS_RAMBOOT
57static void sdram_start(int hi_addr)
58{
59 struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
60 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
61 long control = SDRAM_CONTROL | hi_addr_bit;
62
63 /* unlock mode register */
64 out_be32(&sdram->ctrl, control | 0x80000000);
65
66 /* precharge all banks */
67 out_be32(&sdram->ctrl, control | 0x80000002);
68
69 /* auto refresh */
70 out_be32(&sdram->ctrl, control | 0x80000004);
71
72 /* set mode register */
73 out_be32(&sdram->mode, SDRAM_MODE);
74
75 /* normal operation */
76 out_be32(&sdram->ctrl, control);
77}
78#endif
79
80/*
81 * ATTENTION: Although partially referenced initdram does NOT make real use
82 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
83 * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
84 */
85phys_size_t initdram(int board_type)
86{
87 struct mpc5xxx_mmap_ctl *mmap_ctl =
88 (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
89 struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
90 ulong dramsize = 0;
91 ulong dramsize2 = 0;
92 uint svr, pvr;
93
94 if (gt_ifm_sensor_type == O2DNT2) {
95 /* activate SDRAM CS1 */
96 setbits_be32((void *)MPC5XXX_GPS_PORT_CONFIG, 0x80000000);
97 }
98
99#ifndef CONFIG_SYS_RAMBOOT
100 ulong test1, test2;
101
102 /* setup SDRAM chip selects */
103 out_be32(&mmap_ctl->sdram0, 0x0000001E); /* 2 GB at 0x0 */
104 out_be32(&mmap_ctl->sdram1, 0x00000000); /* disabled */
105
106 /* setup config registers */
107 out_be32(&sdram->config1, SDRAM_CONFIG1);
108 out_be32(&sdram->config2, SDRAM_CONFIG2);
109
110 /* find RAM size using SDRAM CS0 only */
111 sdram_start(0);
112 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
113 sdram_start(1);
114 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
115 if (test1 > test2) {
116 sdram_start(0);
117 dramsize = test1;
118 } else {
119 dramsize = test2;
120 }
121
122 /* memory smaller than 1MB is impossible */
123 if (dramsize < (1 << 20))
124 dramsize = 0;
125
126 /* set SDRAM CS0 size according to the amount of RAM found */
127 if (dramsize > 0) {
128 out_be32(&mmap_ctl->sdram0,
129 (0x13 + __builtin_ffs(dramsize >> 20) - 1));
130 } else {
131 out_be32(&mmap_ctl->sdram0, 0); /* disabled */
132 }
133
134 /* let SDRAM CS1 start right after CS0 */
135 out_be32(&mmap_ctl->sdram1, dramsize + 0x0000001E); /* 2G */
136
137 /* find RAM size using SDRAM CS1 only */
138 if (!dramsize)
139 sdram_start(0);
140
141 test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
142 0x80000000);
143 if (!dramsize) {
144 sdram_start(1);
145 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
146 0x80000000);
147 }
148
149 if (test1 > test2) {
150 sdram_start(0);
151 dramsize2 = test1;
152 } else {
153 dramsize2 = test2;
154 }
155
156 /* memory smaller than 1MB is impossible */
157 if (dramsize2 < (1 << 20))
158 dramsize2 = 0;
159
160 /* set SDRAM CS1 size according to the amount of RAM found */
161 if (dramsize2 > 0) {
162 out_be32(&mmap_ctl->sdram1, (dramsize |
163 (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
164 } else {
165 out_be32(&mmap_ctl->sdram1, dramsize); /* disabled */
166 }
167
168#else /* CONFIG_SYS_RAMBOOT */
169 /* retrieve size of memory connected to SDRAM CS0 */
170 dramsize = in_be32(&mmap_ctl->sdram0) & 0xFF;
171 if (dramsize >= 0x13)
172 dramsize = (1 << (dramsize - 0x13)) << 20;
173 else
174 dramsize = 0;
175
176 /* retrieve size of memory connected to SDRAM CS1 */
177 dramsize2 = in_be32(&mmap_ctl->sdram1) & 0xFF;
178 if (dramsize2 >= 0x13)
179 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
180 else
181 dramsize2 = 0;
182
183#endif /* CONFIG_SYS_RAMBOOT */
184
185 /*
186 * On MPC5200B we need to set the special configuration delay in the
187 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
188 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
189 *
190 * "The SDelay should be written to a value of 0x00000004. It is
191 * required to account for changes caused by normal wafer processing
192 * parameters."
193 */
194 svr = get_svr();
195 pvr = get_pvr();
196 if ((SVR_MJREV(svr) >= 2) &&
197 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
198 out_be32(&sdram->sdelay, 0x04);
199
200 return dramsize + dramsize2;
201}
202
203
204#define GPT_GPIO_IN 0x4
205
206int checkboard(void)
207{
208 struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
209 unsigned char board_config = 0;
210 int i;
211
212 /* switch gpt0 - gpt7 to input */
213 for (i = 0; i < 7; i++)
214 out_be32(&gpt[i].emsr, GPT_GPIO_IN);
215
216 /* get configuration byte on timer-port */
217 for (i = 0; i < 7; i++)
218 board_config |= (in_be32(&gpt[i].sr) & 0x100) >> (8 - i);
219
220 puts("Board: ");
221
222 switch (board_config) {
223 case 0:
224 puts("O2DNT\n");
225 gt_ifm_sensor_type = O2DNT;
226 break;
227 case 1:
228 puts("O3DNT\n");
229 gt_ifm_sensor_type = O3DNT;
230 break;
231 case 2:
232 puts("O2DNT2\n");
233 gt_ifm_sensor_type = O2DNT2;
234 break;
235 case 64:
236 puts("O3DNT Minerva\n");
237 gt_ifm_sensor_type = O3DNT_MIN;
238 break;
239 default:
240 puts("Unknown\n");
241 gt_ifm_sensor_type = UNKNOWN;
242 break;
243 }
244
245 return 0;
246}
247
248int board_early_init_r(void)
249{
250 struct mpc5xxx_lpb *lpb_regs = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
251
252 /*
253 * Now, when we are in RAM, enable flash write access for detection
254 * process. Note that CS_BOOT cannot be cleared when executing in flash.
255 */
256 clrbits_be32(&lpb_regs->cs0_cfg, 1); /* clear RO */
257 /* disable CS_BOOT */
258 clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
259 /* enable CS0 */
260 setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
261
262 return 0;
263}
264
265#define MIIM_LXT971_LED_CFG_REG 0x14
266#define LXT971_LED_CFG_LINK_STATUS 0x4000
267#define LXT971_LED_CFG_RX_TX_ACTIVITY 0x0700
268#define LXT971_LED_CFG_LINK_ACTIVITY 0x00D0
269#define LXT971_LED_CFG_PULSE_STRETCH 0x0002
270/*
271 * Additional PHY intialization after reset in mpc5xxx_fec_init_phy()
272 */
273void reset_phy(void)
274{
275 /*
276 * Set LED configuration bits.
277 * It can't be done in misc_init_r() since FEC is not
278 * initialized at this time. Therefore we do it here.
279 */
280 miiphy_write("FEC", CONFIG_PHY_ADDR, MIIM_LXT971_LED_CFG_REG,
281 LXT971_LED_CFG_LINK_STATUS |
282 LXT971_LED_CFG_RX_TX_ACTIVITY |
283 LXT971_LED_CFG_LINK_ACTIVITY |
284 LXT971_LED_CFG_PULSE_STRETCH);
285}
286
287#if defined(CONFIG_POST)
288/*
289 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
290 * is left open, no keypress is detected.
291 */
292int post_hotkeys_pressed(void)
293{
294 struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *) MPC5XXX_GPIO;
295
296 /*
297 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
298 * CODEC or UART mode. Consumer IrDA should still be possible.
299 */
300 clrbits_be32(&gpio->port_config, 0x07000000);
301 setbits_be32(&gpio->port_config, 0x03000000);
302
303 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
304 setbits_be32(&gpio->simple_gpioe, 0x20000000);
305
306 /* Configure GPIO_IRDA_1 as input */
307 clrbits_be32(&gpio->simple_ddr, 0x20000000);
308
309 return (in_be32(&gpio->simple_ival) & 0x20000000) ? 0 : 1;
310}
311#endif
312
313#ifdef CONFIG_PCI
314static struct pci_controller hose;
315
316void pci_init_board(void)
317{
318 pci_mpc5xxx_init(&hose);
319}
320#endif
321
322#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
323#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
324static void ft_adapt_flash_base(void *blob)
325{
326 flash_info_t *dev = &flash_info[0];
327 int off;
328 struct fdt_property *prop;
329 int len;
330 u32 *reg, *reg2;
331
332 off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
333 if (off < 0) {
334 printf("Could not find fsl,mpc5200b-lpb node.\n");
335 return;
336 }
337
338 /* found compatible property */
339 prop = fdt_get_property_w(blob, off, "ranges", &len);
340 if (prop) {
341 reg = reg2 = (u32 *)&prop->data[0];
342
343 reg[2] = dev->start[0];
344 reg[3] = dev->size;
345 fdt_setprop(blob, off, "ranges", reg2, len);
346 } else
347 printf("Could not find ranges\n");
348}
349
350extern ulong flash_get_size(phys_addr_t base, int banknum);
351
352/* Update the flash baseaddr settings */
353int update_flash_size(int flash_size)
354{
355 struct mpc5xxx_mmap_ctl *mm =
356 (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
357 flash_info_t *dev;
358 int i;
359 int size = 0;
360 unsigned long base = 0x0;
361 u32 *cs_reg = (u32 *)&mm->cs0_start;
362
363 for (i = 0; i < 2; i++) {
364 dev = &flash_info[i];
365
366 if (dev->size) {
367 /* calculate new base addr for this chipselect */
368 base -= dev->size;
369 out_be32(cs_reg, START_REG(base));
370 cs_reg++;
371 out_be32(cs_reg, STOP_REG(base, dev->size));
372 cs_reg++;
373 /* recalculate the sectoraddr in the cfi driver */
374 size += flash_get_size(base, i);
375 }
376 }
377 flash_protect_default();
378 gd->bd->bi_flashstart = base;
379 return 0;
380}
381#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
382
383void ft_board_setup(void *blob, bd_t *bd)
384{
385 int phy_addr = CONFIG_PHY_ADDR;
386 char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
387
388 ft_cpu_setup(blob, bd);
389
390#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
391#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
392 /* Update reg property in all nor flash nodes too */
393 fdt_fixup_nor_flash_size(blob);
394#endif
395 ft_adapt_flash_base(blob);
396#endif
397 /* fix up the phy address */
398 do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
399}
400#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */