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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Ruchika Gupta48ef0d22014-09-09 11:50:30 +05302/*
3 * Common internal memory map for some Freescale SoCs
4 *
5 * Copyright 2014 Freescale Semiconductor, Inc.
Ruchika Gupta48ef0d22014-09-09 11:50:30 +05306 */
7
8#ifndef __FSL_SEC_H
9#define __FSL_SEC_H
10
11#include <common.h>
12#include <asm/io.h>
13
Ruchika Gupta028dbb82014-09-09 11:50:31 +053014#ifdef CONFIG_SYS_FSL_SEC_LE
15#define sec_in32(a) in_le32(a)
16#define sec_out32(a, v) out_le32(a, v)
17#define sec_in16(a) in_le16(a)
18#define sec_clrbits32 clrbits_le32
19#define sec_setbits32 setbits_le32
20#elif defined(CONFIG_SYS_FSL_SEC_BE)
21#define sec_in32(a) in_be32(a)
22#define sec_out32(a, v) out_be32(a, v)
23#define sec_in16(a) in_be16(a)
24#define sec_clrbits32 clrbits_be32
25#define sec_setbits32 setbits_be32
York Sun90b80382016-12-28 08:43:31 -080026#elif defined(CONFIG_SYS_FSL_HAS_SEC)
Ruchika Gupta028dbb82014-09-09 11:50:31 +053027#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
28#endif
29
Ruchika Gupta48ef0d22014-09-09 11:50:30 +053030/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
31#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
Ruchika Guptac5de15c2014-10-07 15:46:20 +053032/* RNG4 TRNG test registers */
33struct rng4tst {
34#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
Alex Porosanuc4065512015-05-05 16:48:35 +030035#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in
36 both entropy shifter and
37 statistical checker */
38#define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both
39 entropy shifter and
40 statistical checker */
41#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
42 entropy shifter, raw data
43 in statistical checker */
44#define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */
Ruchika Guptac5de15c2014-10-07 15:46:20 +053045 u32 rtmctl; /* misc. control register */
46 u32 rtscmisc; /* statistical check misc. register */
47 u32 rtpkrrng; /* poker range register */
Alex Porosanu17649e12015-05-05 16:48:34 +030048#define RTSDCTL_ENT_DLY_MIN 3200
Ruchika Guptac5de15c2014-10-07 15:46:20 +053049#define RTSDCTL_ENT_DLY_MAX 12800
50 union {
51 u32 rtpkrmax; /* PRGM=1: poker max. limit register */
52 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
53 };
54#define RTSDCTL_ENT_DLY_SHIFT 16
55#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
56 u32 rtsdctl; /* seed control register */
57 union {
58 u32 rtsblim; /* PRGM=1: sparse bit limit register */
59 u32 rttotsam; /* PRGM=0: total samples register */
60 };
61 u32 rtfreqmin; /* frequency count min. limit register */
Alex Porosanu026a3f12015-05-05 16:48:33 +030062#define RTFRQMAX_DISABLE (1 << 20)
Ruchika Guptac5de15c2014-10-07 15:46:20 +053063 union {
64 u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */
65 u32 rtfreqcnt; /* PRGM=0: freq. count register */
66 };
67 u32 rsvd1[40];
68#define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
Lukas Auerdfaec762018-01-25 14:11:17 +010069#define RNG_STATE1_HANDLE_INSTANTIATED 0x00000002
70#define RNG_STATE_HANDLE_MASK \
71 (RNG_STATE0_HANDLE_INSTANTIATED | RNG_STATE1_HANDLE_INSTANTIATED)
Ruchika Guptac5de15c2014-10-07 15:46:20 +053072 u32 rdsta; /*RNG DRNG Status Register*/
73 u32 rsvd2[15];
74};
75
Ruchika Gupta48ef0d22014-09-09 11:50:30 +053076typedef struct ccsr_sec {
77 u32 res0;
78 u32 mcfgr; /* Master CFG Register */
79 u8 res1[0x4];
80 u32 scfgr;
81 struct {
82 u32 ms; /* Job Ring LIODN Register, MS */
83 u32 ls; /* Job Ring LIODN Register, LS */
84 } jrliodnr[4];
85 u8 res2[0x2c];
86 u32 jrstartr; /* Job Ring Start Register */
87 struct {
88 u32 ms; /* RTIC LIODN Register, MS */
89 u32 ls; /* RTIC LIODN Register, LS */
90 } rticliodnr[4];
91 u8 res3[0x1c];
92 u32 decorr; /* DECO Request Register */
93 struct {
94 u32 ms; /* DECO LIODN Register, MS */
95 u32 ls; /* DECO LIODN Register, LS */
96 } decoliodnr[8];
97 u8 res4[0x40];
98 u32 dar; /* DECO Avail Register */
99 u32 drr; /* DECO Reset Register */
Ruchika Guptac5de15c2014-10-07 15:46:20 +0530100 u8 res5[0x4d8];
101 struct rng4tst rng; /* RNG Registers */
Ulises Cardenasf91e65a2016-02-02 04:39:39 -0600102 u8 res6[0x8a0];
Ruchika Gupta48ef0d22014-09-09 11:50:30 +0530103 u32 crnr_ms; /* CHA Revision Number Register, MS */
104 u32 crnr_ls; /* CHA Revision Number Register, LS */
105 u32 ctpr_ms; /* Compile Time Parameters Register, MS */
106 u32 ctpr_ls; /* Compile Time Parameters Register, LS */
Ulises Cardenasf91e65a2016-02-02 04:39:39 -0600107 u8 res7[0x10];
Ruchika Gupta48ef0d22014-09-09 11:50:30 +0530108 u32 far_ms; /* Fault Address Register, MS */
109 u32 far_ls; /* Fault Address Register, LS */
110 u32 falr; /* Fault Address LIODN Register */
111 u32 fadr; /* Fault Address Detail Register */
Ulises Cardenasf91e65a2016-02-02 04:39:39 -0600112 u8 res8[0x4];
Ruchika Gupta48ef0d22014-09-09 11:50:30 +0530113 u32 csta; /* CAAM Status Register */
Ulises Cardenasf91e65a2016-02-02 04:39:39 -0600114 u32 smpart; /* Secure Memory Partition Parameters */
115 u32 smvid; /* Secure Memory Version ID */
Ruchika Gupta48ef0d22014-09-09 11:50:30 +0530116 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
117 u32 ccbvid; /* CHA Cluster Block Version ID Register */
118 u32 chavid_ms; /* CHA Version ID Register, MS */
119 u32 chavid_ls; /* CHA Version ID Register, LS */
120 u32 chanum_ms; /* CHA Number Register, MS */
121 u32 chanum_ls; /* CHA Number Register, LS */
122 u32 secvid_ms; /* SEC Version ID Register, MS */
123 u32 secvid_ls; /* SEC Version ID Register, LS */
Laurentiu Tudord8d5fdb2019-02-26 13:18:32 +0200124#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
125 u8 res9[0x6f020];
126#else
Ruchika Gupta48ef0d22014-09-09 11:50:30 +0530127 u8 res9[0x6020];
Laurentiu Tudord8d5fdb2019-02-26 13:18:32 +0200128#endif
Ruchika Gupta48ef0d22014-09-09 11:50:30 +0530129 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
130 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
Laurentiu Tudord8d5fdb2019-02-26 13:18:32 +0200131#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
132 u8 res10[0x8ffd8];
133#else
Ruchika Gupta48ef0d22014-09-09 11:50:30 +0530134 u8 res10[0x8fd8];
Laurentiu Tudord8d5fdb2019-02-26 13:18:32 +0200135#endif
Ruchika Gupta48ef0d22014-09-09 11:50:30 +0530136} ccsr_sec_t;
137
138#define SEC_CTPR_MS_AXI_LIODN 0x08000000
139#define SEC_CTPR_MS_QI 0x02000000
140#define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001
141#define SEC_CTPR_MS_VIRT_EN_POR 0x00000002
142#define SEC_RVID_MA 0x0f000000
143#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
144#define SEC_CHANUM_MS_JRNUM_SHIFT 28
145#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
146#define SEC_CHANUM_MS_DECONUM_SHIFT 24
147#define SEC_SECVID_MS_IPID_MASK 0xffff0000
148#define SEC_SECVID_MS_IPID_SHIFT 16
149#define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
150#define SEC_SECVID_MS_MAJ_REV_SHIFT 8
151#define SEC_CCBVID_ERA_MASK 0xff000000
152#define SEC_CCBVID_ERA_SHIFT 24
153#define SEC_SCFGR_RDBENABLE 0x00000400
154#define SEC_SCFGR_VIRT_EN 0x00008000
155#define SEC_CHAVID_LS_RNG_SHIFT 16
156#define SEC_CHAVID_RNG_LS_MASK 0x000f0000
Ruchika Guptab9eebfa2014-10-15 11:35:30 +0530157
158#define CONFIG_JRSTARTR_JR0 0x00000001
159
160struct jr_regs {
Ulises Cardenasf91e65a2016-02-02 04:39:39 -0600161#if defined(CONFIG_SYS_FSL_SEC_LE) && \
162 !(defined(CONFIG_MX6) || defined(CONFIG_MX7))
Ruchika Guptab9eebfa2014-10-15 11:35:30 +0530163 u32 irba_l;
164 u32 irba_h;
165#else
166 u32 irba_h;
167 u32 irba_l;
168#endif
169 u32 rsvd1;
170 u32 irs;
171 u32 rsvd2;
172 u32 irsa;
173 u32 rsvd3;
174 u32 irja;
Ulises Cardenasf91e65a2016-02-02 04:39:39 -0600175#if defined(CONFIG_SYS_FSL_SEC_LE) && \
176 !(defined(CONFIG_MX6) || defined(CONFIG_MX7))
Ruchika Guptab9eebfa2014-10-15 11:35:30 +0530177 u32 orba_l;
178 u32 orba_h;
179#else
180 u32 orba_h;
181 u32 orba_l;
182#endif
183 u32 rsvd4;
184 u32 ors;
185 u32 rsvd5;
186 u32 orjr;
187 u32 rsvd6;
188 u32 orsf;
189 u32 rsvd7;
190 u32 jrsta;
191 u32 rsvd8;
192 u32 jrint;
193 u32 jrcfg0;
194 u32 jrcfg1;
195 u32 rsvd9;
196 u32 irri;
197 u32 rsvd10;
198 u32 orwi;
199 u32 rsvd11;
200 u32 jrcr;
201};
202
gaurav rana94e3c8c2015-02-20 12:51:46 +0530203/*
204 * Scatter Gather Entry - Specifies the the Scatter Gather Format
205 * related information
206 */
207struct sg_entry {
Ulises Cardenasf91e65a2016-02-02 04:39:39 -0600208#if defined(CONFIG_SYS_FSL_SEC_LE) && \
209 !(defined(CONFIG_MX6) || defined(CONFIG_MX7))
gaurav rana94e3c8c2015-02-20 12:51:46 +0530210 uint32_t addr_lo; /* Memory Address - lo */
Aneesh Bansalf59e69c2015-10-29 22:58:03 +0530211 uint32_t addr_hi; /* Memory Address of start of buffer - hi */
gaurav rana94e3c8c2015-02-20 12:51:46 +0530212#else
Aneesh Bansalf59e69c2015-10-29 22:58:03 +0530213 uint32_t addr_hi; /* Memory Address of start of buffer - hi */
gaurav rana94e3c8c2015-02-20 12:51:46 +0530214 uint32_t addr_lo; /* Memory Address - lo */
215#endif
216
217 uint32_t len_flag; /* Length of the data in the frame */
218#define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF
219#define SG_ENTRY_EXTENSION_BIT 0x80000000
220#define SG_ENTRY_FINAL_BIT 0x40000000
221 uint32_t bpid_offset;
222#define SG_ENTRY_BPID_MASK 0x00FF0000
223#define SG_ENTRY_BPID_SHIFT 16
224#define SG_ENTRY_OFFSET_MASK 0x00001FFF
225#define SG_ENTRY_OFFSET_SHIFT 0
226};
227
Clemens Gruber598e9dc2018-01-07 20:26:29 +0100228#define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */
229
Ulises Cardenasf91e65a2016-02-02 04:39:39 -0600230#if defined(CONFIG_MX6) || defined(CONFIG_MX7)
231/* Job Ring Base Address */
232#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
233/* Secure Memory Offset varies accross versions */
234#define SM_V1_OFFSET 0x0f4
235#define SM_V2_OFFSET 0xa00
236/*Secure Memory Versioning */
237#define SMVID_V2 0x20105
238#define SM_VERSION(x) (x < SMVID_V2 ? 1 : 2)
239#define SM_OFFSET(x) (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET)
Raul Cardenas02000202015-02-27 11:22:06 -0600240/* CAAM Job Ring 0 Registers */
241/* Secure Memory Partition Owner register */
242#define SMCSJR_PO (3 << 6)
243/* JR Allocation Error */
244#define SMCSJR_AERR (3 << 12)
245/* Secure memory partition 0 page 0 owner register */
Ulises Cardenasf91e65a2016-02-02 04:39:39 -0600246#define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC)
Raul Cardenas02000202015-02-27 11:22:06 -0600247/* Secure memory command register */
Ulises Cardenasf91e65a2016-02-02 04:39:39 -0600248#define CAAM_SMCJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v))
Raul Cardenas02000202015-02-27 11:22:06 -0600249/* Secure memory command status register */
Ulises Cardenasf91e65a2016-02-02 04:39:39 -0600250#define CAAM_SMCSJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v))
Raul Cardenas02000202015-02-27 11:22:06 -0600251/* Secure memory access permissions register */
Ulises Cardenasf91e65a2016-02-02 04:39:39 -0600252#define CAAM_SMAPJR(v, jr, y) \
253 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16)
Raul Cardenas02000202015-02-27 11:22:06 -0600254/* Secure memory access group 2 register */
Ulises Cardenasf91e65a2016-02-02 04:39:39 -0600255#define CAAM_SMAG2JR(v, jr, y) \
256 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16)
Raul Cardenas02000202015-02-27 11:22:06 -0600257/* Secure memory access group 1 register */
Ulises Cardenasf91e65a2016-02-02 04:39:39 -0600258#define CAAM_SMAG1JR(v, jr, y) \
259 (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP1(v) + y * 16)
Raul Cardenas02000202015-02-27 11:22:06 -0600260
261/* Commands and macros for secure memory */
Ulises Cardenasf91e65a2016-02-02 04:39:39 -0600262#define SM_CMD(v) (v == 1 ? 0x0 : 0x1E4)
263#define SM_STATUS(v) (v == 1 ? 0x8 : 0x1EC)
264#define SM_PERM(v) (v == 1 ? 0x10 : 0x4)
265#define SM_GROUP2(v) (v == 1 ? 0x14 : 0x8)
266#define SM_GROUP1(v) (v == 1 ? 0x18 : 0xC)
Raul Cardenas02000202015-02-27 11:22:06 -0600267#define CMD_PAGE_ALLOC 0x1
268#define CMD_PAGE_DEALLOC 0x2
269#define CMD_PART_DEALLOC 0x3
270#define CMD_INQUIRY 0x5
271#define CMD_COMPLETE (3 << 14)
272#define PAGE_AVAILABLE 0
273#define PAGE_OWNED (3 << 6)
274#define PAGE(x) (x << 16)
275#define PARTITION(x) (x << 8)
276#define PARTITION_OWNER(x) (0x3 << (x*2))
277
278/* Address of secure 4kbyte pages */
279#define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR
280#define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000)
281#define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000)
282#define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000)
283
284#define JR_MID 2 /* Matches ROM configuration */
285#define KS_G1 (1 << JR_MID) /* CAAM only */
286#define PERM 0x0000B008 /* Clear on release, lock SMAP
287 * lock SMAG group 1 Blob */
288
Raul Cardenas02000202015-02-27 11:22:06 -0600289/* HAB WRAPPED KEY header */
290#define WRP_HDR_SIZE 0x08
291#define HDR_TAG 0x81
292#define HDR_PAR 0x41
293/* HAB WRAPPED KEY Data */
294#define HAB_MOD 0x66
295#define HAB_ALG 0x55
296#define HAB_FLG 0x00
297
298/* Partition and Page IDs */
299#define PARTITION_1 1
300#define PAGE_1 1
301
302#define ERROR_IN_PAGE_ALLOC 1
303#define ECONSTRJDESC -1
304
305#endif
306
Raul Cardenas02000202015-02-27 11:22:06 -0600307/* blob_dek:
308 * Encapsulates the src in a secure blob and stores it dst
309 * @src: reference to the plaintext
310 * @dst: reference to the output adrress
311 * @len: size in bytes of src
312 * @return: 0 on success, error otherwise
313 */
314int blob_dek(const u8 *src, u8 *dst, u8 len);
315
York Sun4fd64742016-11-15 18:44:22 -0800316#if defined(CONFIG_ARCH_C29X)
Alex Porosanu76394c92016-04-29 15:18:00 +0300317int sec_init_idx(uint8_t);
318#endif
319int sec_init(void);
Ruchika Gupta48ef0d22014-09-09 11:50:30 +0530320#endif
321
322#endif /* __FSL_SEC_H */