blob: 2e6147d8228d27d210477301638e2de36870b66f [file] [log] [blame]
David Lechner2ac07f72016-02-26 00:46:07 -06001/*
2 * Copyright (C) 2016 David Lechner <david@lechnology.com>
3 *
4 * Based on da850evm.h
5 *
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 * Based on davinci_dvevm.h. Original Copyrights follow:
9 *
10 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
11 *
12 * SPDX-License-Identifier: GPL-2.0+
13 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18/*
19 * SoC Configuration
20 */
21#define CONFIG_MACH_DAVINCI_DA850_EVM
22#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
23#define CONFIG_SOC_DA850 /* TI DA850 SoC */
24#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
25#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
26#define CONFIG_SYS_OSCIN_FREQ 24000000
27#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
28#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
David Lechner2ac07f72016-02-26 00:46:07 -060029
30#define CONFIG_SYS_TEXT_BASE 0xc1080000
31
David Lechner2ac07f72016-02-26 00:46:07 -060032/*
33 * Memory Info
34 */
35#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
36#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
37#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
38#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
39
40/* memtest start addr */
41#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
42
43/* memtest will be run on 16MB */
44#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
45
46#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
47
48#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
49 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
50 DAVINCI_SYSCFG_SUSPSRC_SPI0 | \
51 DAVINCI_SYSCFG_SUSPSRC_UART1 | \
52 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
53 DAVINCI_SYSCFG_SUSPSRC_I2C)
54
55/*
56 * PLL configuration
57 */
58#define CONFIG_SYS_DV_CLKMODE 0
59#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
60#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
61#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
62#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
63#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
64#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
65#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
66#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
67
68#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
69#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
70#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
71#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
72
73#define CONFIG_SYS_DA850_PLL0_PLLM 24
74#define CONFIG_SYS_DA850_PLL1_PLLM 21
75
76/*
77 * DDR2 memory configuration
78 */
79#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
80 DV_DDR_PHY_EXT_STRBEN | \
81 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
82
83#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
84 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
85 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
86 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
87 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
88 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
89 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
90 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
91
92/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
93#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
94
95#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
96 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
97 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
98 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
99 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
100 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
101 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
102 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
103 (0 << DV_DDR_SDTMR1_WTR_SHIFT))
104
105#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
106 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
107 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \
108 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
109 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
110 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
111 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
112 (0 << DV_DDR_SDTMR2_CKE_SHIFT))
113
114#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
115#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
116
117/*
118 * Serial Driver info
119 */
120#define CONFIG_SYS_NS16550_SERIAL
121#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
122#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART1_BASE /* Base address of UART1 */
123#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
124#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
David Lechner2ac07f72016-02-26 00:46:07 -0600125
126#define CONFIG_SPI
David Lechner2ac07f72016-02-26 00:46:07 -0600127#define CONFIG_DAVINCI_SPI
128#define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE
129#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
130#define CONFIG_SF_DEFAULT_SPEED 50000000
131#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
132
133/*
134 * I2C Configuration
135 */
136#define CONFIG_SYS_I2C
137#define CONFIG_SYS_I2C_DAVINCI
138#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
139#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
140
141/*
142 * U-Boot general configuration
143 */
David Lechner2ac07f72016-02-26 00:46:07 -0600144#define CONFIG_BOOTFILE "uImage" /* Boot file name */
145#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
146#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
147#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
148#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
149#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
David Lechner2ac07f72016-02-26 00:46:07 -0600150#define CONFIG_AUTO_COMPLETE
David Lechner2ac07f72016-02-26 00:46:07 -0600151#define CONFIG_CMDLINE_EDITING
152#define CONFIG_SYS_LONGHELP
David Lechner2ac07f72016-02-26 00:46:07 -0600153#define CONFIG_MX_CYCLIC
David Lechner2ac07f72016-02-26 00:46:07 -0600154
155/*
156 * Linux Information
157 */
158#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
159#define CONFIG_HWCONFIG /* enable hwconfig */
160#define CONFIG_CMDLINE_TAG
161#define CONFIG_REVISION_TAG
162#define CONFIG_SERIAL_TAG
163#define CONFIG_SETUP_MEMORY_TAGS
164#define CONFIG_SETUP_INITRD_TAG
David Lechner2ac07f72016-02-26 00:46:07 -0600165#define CONFIG_BOOTCOMMAND \
166 "if mmc rescan; then " \
167 "if run loadbootscr; then " \
168 "run bootscript; " \
169 "else " \
170 "if run loadimage; then " \
171 "run mmcargs; " \
172 "run mmcboot; " \
173 "else " \
174 "run flashargs; " \
175 "run flashboot; " \
176 "fi; " \
177 "fi; " \
178 "else " \
179 "run flashargs; " \
180 "run flashboot; " \
181 "fi"
182#define CONFIG_EXTRA_ENV_SETTINGS \
183 "hostname=EV3\0" \
184 "memsize=64M\0" \
185 "filesyssize=10M\0" \
186 "verify=n\0" \
187 "console=ttyS1,115200n8\0" \
188 "bootscraddr=0xC0600000\0" \
189 "loadaddr=0xC0007FC0\0" \
190 "filesysaddr=0xC1180000\0" \
191 "fwupdateboot=mw 0xFFFF1FFC 0x5555AAAA; reset\0" \
192 "mmcargs=setenv bootargs mem=${memsize} console=${console} root=/dev/mmcblk0p2 rw rootwait lpj=747520\0" \
193 "mmcboot=bootm ${loadaddr}\0" \
194 "flashargs=setenv bootargs mem=${memsize} initrd=${filesysaddr},${filesyssize} root=/dev/ram0 rw rootfstype=squashfs console=${console} lpj=747520\0" \
195 "flashboot=sf probe 0; sf read ${loadaddr} 0x50000 0x300000; sf read ${filesysaddr} 0x350000 0x960000; bootm ${loadaddr}\0" \
196 "loadimage=fatload mmc 0 ${loadaddr} uImage\0" \
197 "loadbootscr=fatload mmc 0 ${bootscraddr} boot.scr\0" \
198 "bootscript=source ${bootscraddr}\0" \
199
David Lechner2ac07f72016-02-26 00:46:07 -0600200#ifdef CONFIG_CMD_BDI
201#define CONFIG_CLOCKS
202#endif
203
David Lechner2ac07f72016-02-26 00:46:07 -0600204#define CONFIG_ENV_SIZE (16 << 10)
205
David Lechner2ac07f72016-02-26 00:46:07 -0600206/* additions for new relocation code, must added to all boards */
207#define CONFIG_SYS_SDRAM_BASE 0xc0000000
208
209#define CONFIG_SYS_INIT_SP_ADDR 0x80010000
210
Simon Glass89f5eaa2017-05-17 08:23:09 -0600211#include <asm/arch/hardware.h>
212
David Lechner2ac07f72016-02-26 00:46:07 -0600213#endif /* __CONFIG_H */