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Yoshihiro Shimoda320cf352013-12-18 16:03:44 +09001/*
2 * Configuation settings for the sh7753evb board
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __SH7753EVB_H
10#define __SH7753EVB_H
11
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090012#define CONFIG_CPU_SH7753 1
13#define CONFIG_SH7753EVB 1
14
15#define CONFIG_SYS_TEXT_BASE 0x5ff80000
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090016
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090017#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"
18
Vladimir Zapolskiy18a40e82016-11-28 00:15:30 +020019#define CONFIG_DISPLAY_BOARDINFO
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090020#undef CONFIG_SHOW_BOOT_PROGRESS
21#define CONFIG_CMDLINE_EDITING
22#define CONFIG_AUTO_COMPLETE
23
24/* MEMORY */
25#define SH7753EVB_SDRAM_BASE (0x40000000)
26#define SH7753EVB_SDRAM_SIZE (512 * 1024 * 1024)
27
28#define CONFIG_SYS_LONGHELP
29#define CONFIG_SYS_CBSIZE 256
30#define CONFIG_SYS_PBSIZE 256
31#define CONFIG_SYS_MAXARGS 16
32#define CONFIG_SYS_BARGSIZE 512
33#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
34
35/* SCIF */
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090036#define CONFIG_CONS_SCIF2 1
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090037
38#define CONFIG_SYS_MEMTEST_START (SH7753EVB_SDRAM_BASE)
39#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
40 480 * 1024 * 1024)
41#undef CONFIG_SYS_ALT_MEMTEST
42#undef CONFIG_SYS_MEMTEST_SCRATCH
43#undef CONFIG_SYS_LOADS_BAUD_CHANGE
44
45#define CONFIG_SYS_SDRAM_BASE (SH7753EVB_SDRAM_BASE)
46#define CONFIG_SYS_SDRAM_SIZE (SH7753EVB_SDRAM_SIZE)
47#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
48 128 * 1024 * 1024)
49
50#define CONFIG_SYS_MONITOR_BASE 0x00000000
51#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
52#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
53#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
54
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090055/* Ether */
56#define CONFIG_SH_ETHER 1
57#define CONFIG_SH_ETHER_USE_PORT 0
58#define CONFIG_SH_ETHER_PHY_ADDR 18
59#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
60#define CONFIG_SH_ETHER_USE_GETHER 1
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090061#define CONFIG_BITBANGMII
62#define CONFIG_BITBANGMII_MULTI
63#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
64#define CONFIG_PHY_VITESSE
65
66#define SH7753EVB_ETHERNET_MAC_BASE_SPI 0x00090000
67#define SH7753EVB_SPI_SECTOR_SIZE (64 * 1024)
68#define SH7753EVB_ETHERNET_MAC_BASE SH7753EVB_ETHERNET_MAC_BASE_SPI
69#define SH7753EVB_ETHERNET_MAC_SIZE 17
70#define SH7753EVB_ETHERNET_NUM_CH 2
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090071
72/* SPI */
73#define CONFIG_SH_SPI 1
74#define CONFIG_SH_SPI_BASE 0xfe002000
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090075
76/* MMCIF */
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090077#define CONFIG_SH_MMCIF 1
78#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
79#define CONFIG_SH_MMCIF_CLK 48000000
80
81/* ENV setting */
82#define CONFIG_ENV_IS_EMBEDDED
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090083#define CONFIG_ENV_SECT_SIZE (64 * 1024)
84#define CONFIG_ENV_ADDR (0x00080000)
85#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
86#define CONFIG_ENV_OVERWRITE 1
87#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
88#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
89#define CONFIG_EXTRA_ENV_SETTINGS \
90 "netboot=bootp; bootm\0"
91
92/* Board Clock */
93#define CONFIG_SYS_CLK_FREQ 48000000
94#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
95#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
96#define CONFIG_SYS_TMU_CLK_DIV 4
97#endif /* __SH7753EVB_H */