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Soeren Moch05d492a2014-11-03 13:57:01 +01001/*
2 * Copyright (C) 2014 Soeren Moch <smoch@web.de>
3 *
4 * Configuration settings for the TBS2910 MatrixARM board.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __TBS2910_CONFIG_H
10#define __TBS2910_CONFIG_H
11
12#include "mx6_common.h"
Soeren Moch05d492a2014-11-03 13:57:01 +010013
14/* General configuration */
Soeren Moch05d492a2014-11-03 13:57:01 +010015
16#define CONFIG_MACH_TYPE 3980
17
Soeren Moch05d492a2014-11-03 13:57:01 +010018#define CONFIG_SYS_HZ 1000
19
Adrian Alonso1368f992015-09-02 13:54:13 -050020#define CONFIG_IMX_THERMAL
Soeren Mochfbd18aa2015-05-29 20:32:41 +020021
Soeren Moch05d492a2014-11-03 13:57:01 +010022/* Physical Memory Map */
23#define CONFIG_NR_DRAM_BANKS 1
24#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
25
26#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
27#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
28#define CONFIG_SYS_INIT_SP_OFFSET \
29 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
30#define CONFIG_SYS_INIT_SP_ADDR \
31 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
32
33#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024)
34
35#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
36#define CONFIG_SYS_MEMTEST_END \
37 (CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024)
38
Soeren Moch29138c62016-09-21 13:16:21 +020039#define CONFIG_SYS_BOOTMAPSZ 0x10000000
Soeren Moch05d492a2014-11-03 13:57:01 +010040
41/* Serial console */
42#define CONFIG_MXC_UART
43#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */
Soeren Moch05d492a2014-11-03 13:57:01 +010044
Soeren Moch05d492a2014-11-03 13:57:01 +010045#define CONFIG_CONS_INDEX 1
46
Soeren Moch05d492a2014-11-03 13:57:01 +010047/* Filesystems / image support */
Soeren Moch05d492a2014-11-03 13:57:01 +010048
49/* MMC */
Soeren Moch05d492a2014-11-03 13:57:01 +010050#define CONFIG_SYS_FSL_USDHC_NUM 3
51#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
Soeren Moch9927d602015-05-05 23:09:21 +020052#define CONFIG_SUPPORT_EMMC_BOOT
Soeren Moch05d492a2014-11-03 13:57:01 +010053
54/* Ethernet */
55#define CONFIG_FEC_MXC
Soeren Moch05d492a2014-11-03 13:57:01 +010056#define CONFIG_FEC_MXC
57#define CONFIG_MII
58#define IMX_FEC_BASE ENET_BASE_ADDR
59#define CONFIG_FEC_XCV_TYPE RGMII
60#define CONFIG_ETHPRIME "FEC"
61#define CONFIG_FEC_MXC_PHYADDR 4
Soeren Moch05d492a2014-11-03 13:57:01 +010062#define CONFIG_PHY_ATHEROS
63
64/* Framebuffer */
Soeren Moch05d492a2014-11-03 13:57:01 +010065#ifdef CONFIG_VIDEO
66#define CONFIG_VIDEO_IPUV3
67#define CONFIG_IPUV3_CLK 260000000
Soeren Moch05d492a2014-11-03 13:57:01 +010068#define CONFIG_VIDEO_BMP_RLE8
69#define CONFIG_IMX_HDMI
70#define CONFIG_IMX_VIDEO_SKIP
Soeren Moch05d492a2014-11-03 13:57:01 +010071#endif
72
73/* PCI */
Soeren Moch05d492a2014-11-03 13:57:01 +010074#ifdef CONFIG_CMD_PCI
Soeren Moch05d492a2014-11-03 13:57:01 +010075#define CONFIG_PCI_SCAN_SHOW
76#define CONFIG_PCIE_IMX
77#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
78#endif
79
80/* SATA */
Soeren Moch05d492a2014-11-03 13:57:01 +010081#ifdef CONFIG_CMD_SATA
82#define CONFIG_DWC_AHSATA
83#define CONFIG_SYS_SATA_MAX_DEVICE 1
84#define CONFIG_DWC_AHSATA_PORT_ID 0
85#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
86#define CONFIG_LBA48
87#define CONFIG_LIBATA
88#endif
89
90/* USB */
Soeren Moch05d492a2014-11-03 13:57:01 +010091#ifdef CONFIG_CMD_USB
Soeren Moch05d492a2014-11-03 13:57:01 +010092#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Soeren Mochd8962762015-05-05 23:09:18 +020093#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Soeren Moch05d492a2014-11-03 13:57:01 +010094#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
Soeren Moch6628aa52015-02-26 19:50:02 +010095#ifdef CONFIG_CMD_USB_MASS_STORAGE
Soeren Moch6628aa52015-02-26 19:50:02 +010096#define CONFIG_USBD_HS
Paul Kocialkowski01acd6a2015-06-12 19:56:58 +020097#define CONFIG_USB_FUNCTION_MASS_STORAGE
Soeren Moch6628aa52015-02-26 19:50:02 +010098#endif /* CONFIG_CMD_USB_MASS_STORAGE */
Soeren Moch05d492a2014-11-03 13:57:01 +010099#ifdef CONFIG_USB_KEYBOARD
Soeren Mochdaa12e32014-11-27 21:21:44 +0100100#define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
Soeren Moch54ca1832015-05-05 23:09:19 +0200101#define CONFIG_PREBOOT \
Soeren Moch8741a372016-07-27 16:07:16 +0200102 "usb start; " \
Soeren Moch54ca1832015-05-05 23:09:19 +0200103 "if hdmidet; then " \
Soeren Moch8741a372016-07-27 16:07:16 +0200104 "run set_con_hdmi; " \
Soeren Moch54ca1832015-05-05 23:09:19 +0200105 "else " \
106 "run set_con_serial; " \
107 "fi;"
Soeren Moch05d492a2014-11-03 13:57:01 +0100108#endif /* CONFIG_USB_KEYBOARD */
109#endif /* CONFIG_CMD_USB */
110
111/* RTC */
Soeren Moch05d492a2014-11-03 13:57:01 +0100112#ifdef CONFIG_CMD_DATE
Soeren Moch05d492a2014-11-03 13:57:01 +0100113#define CONFIG_RTC_DS1307
114#define CONFIG_SYS_RTC_BUS_NUM 2
115#endif
116
117/* I2C */
Soeren Moch05d492a2014-11-03 13:57:01 +0100118#ifdef CONFIG_CMD_I2C
119#define CONFIG_SYS_I2C
120#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)03544c62015-09-21 22:43:38 +0200121#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
122#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf8cb1012015-03-20 10:20:40 -0700123#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
Soeren Moch05d492a2014-11-03 13:57:01 +0100124#define CONFIG_SYS_I2C_SPEED 100000
125#define CONFIG_I2C_EDID
126#endif
127
Peter Robinson056845c2015-05-22 17:30:45 +0100128/* Environment organization */
Soeren Mocha6684362016-02-04 14:41:16 +0100129#define CONFIG_SYS_MMC_ENV_DEV 2 /* overwritten on SD boot */
130#define CONFIG_SYS_MMC_ENV_PART 1 /* overwritten on SD boot */
Soeren Moch05d492a2014-11-03 13:57:01 +0100131#define CONFIG_ENV_SIZE (8 * 1024)
132#define CONFIG_ENV_OFFSET (384 * 1024)
133#define CONFIG_ENV_OVERWRITE
134
135#define CONFIG_EXTRA_ENV_SETTINGS \
136 "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
137 "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \
138 "video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \
139 "bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \
140 "bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \
141 "${bootargs_mmc3}\0" \
142 "bootargs_upd=setenv bootargs console=ttymxc0,115200 " \
143 "rdinit=/sbin/init enable_wait_mode=off\0" \
144 "bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \
Soeren Mochb9a16092015-10-01 22:48:04 +0200145 "mmc read 0x10800000 0x800 0x4000; bootm 0x10800000\0" \
Soeren Moch05d492a2014-11-03 13:57:01 +0100146 "bootcmd_up1=load mmc 1 0x10800000 uImage\0" \
147 "bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \
148 "run bootargs_upd; " \
149 "bootm 0x10800000 0x10d00000\0" \
150 "console=ttymxc0\0" \
151 "fan=gpio set 92\0" \
Soeren Moch8741a372016-07-27 16:07:16 +0200152 "set_con_serial=setenv stdout serial; " \
Soeren Moch54ca1832015-05-05 23:09:19 +0200153 "setenv stderr serial;\0" \
Soeren Moch8741a372016-07-27 16:07:16 +0200154 "set_con_hdmi=setenv stdout serial,vga; " \
155 "setenv stderr serial,vga;\0" \
Soeren Moch8ce747f2016-07-27 16:07:17 +0200156 "stderr=serial,vga;\0" \
157 "stdin=serial,usbkbd;\0" \
158 "stdout=serial,vga;\0"
Soeren Moch05d492a2014-11-03 13:57:01 +0100159
160#define CONFIG_BOOTCOMMAND \
161 "mmc rescan; " \
162 "if run bootcmd_up1; then " \
163 "run bootcmd_up2; " \
164 "else " \
165 "run bootcmd_mmc; " \
166 "fi"
167
168#endif /* __TBS2910_CONFIG_H * */