blob: 91686d66a71469b773ca73c624646c4a713d68e4 [file] [log] [blame]
wdenkdc7c9a12003-03-26 06:55:25 +00001/*
2 * (C) Copyright 2000, 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific,
26 * for SinoVee Microsystems SC8xx series SBC
27 * http://www.fel.com.cn (Chinese)
28 * http://www.sinovee.com (English)
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
Wolfgang Denk2ae18242010-10-06 09:05:45 +020034#define CONFIG_SYS_TEXT_BASE 0x40000000
35
wdenkdc7c9a12003-03-26 06:55:25 +000036/* Custom configuration */
37/* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */
38/* SC85T,SC860T, FEL8xx-AT(855T/860T) */
39/*#define CONFIG_FEL8xx_AT */
40/*#define CONFIG_LCD */
41/* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */
42/* #define CONFIG_50MHz */
43/* #define CONFIG_66MHz */
44/* #define CONFIG_75MHz */
45#define CONFIG_80MHz
46/*#define CONFIG_100MHz */
47/* #define CONFIG_BUS_DIV2 1 */
48/* for BOOT device port size */
49/* #define CONFIG_BOOT_8B */
50#define CONFIG_BOOT_16B
51/* #define CONFIG_BOOT_32B */
52/* #define CONFIG_CAN_DRIVER */
53/* #define DEBUG */
54#define CONFIG_FEC_ENET
55
56/* #define CONFIG_SDRAM_16M */
57#define CONFIG_SDRAM_32M
58/* #define CONFIG_SDRAM_64M */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_RESET_ADDRESS 0xffffffff
wdenkdc7c9a12003-03-26 06:55:25 +000060/*
61 * High Level Configuration Options
62 * (easy to change)
63 */
64
65/* #define CONFIG_MPC823 1 */
66/* #define CONFIG_MPC850 1 */
67#define CONFIG_MPC855 1
68/* #define CONFIG_MPC860 1 */
69/* #define CONFIG_MPC860T 1 */
70
71#undef CONFIG_WATCHDOG /* watchdog */
72
Wolfgang Denk53677ef2008-05-20 16:00:29 +020073#define CONFIG_SVM_SC8xx 1 /* ...on SVM SC8xx series */
wdenkdc7c9a12003-03-26 06:55:25 +000074
75#ifdef CONFIG_LCD /* with LCD controller ? */
wdenkfd3103b2003-11-25 16:55:19 +000076/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */
wdenkdc7c9a12003-03-26 06:55:25 +000077#endif
78
79#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
80#undef CONFIG_8xx_CONS_SMC2
81#undef CONFIG_8xx_CONS_NONE
82#define CONFIG_BAUDRATE 19200 /* console baudrate = 115kbps */
83#if 0
84#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
85#else
86#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
87#endif
88
89#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
90
91#define CONFIG_BOARD_TYPES 1 /* support board types */
92
93#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot SVM port;echo;echo Type \"? or help\" to get on-line help;echo"
94
95#undef CONFIG_BOOTARGS
96#define CONFIG_EXTRA_ENV_SETTINGS \
wdenk8bde7f72003-06-27 21:31:46 +000097 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010098 "nfsroot=${serverip}:${rootpath}\0" \
wdenk8bde7f72003-06-27 21:31:46 +000099 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100100 "addip=setenv bootargs ${bootargs} " \
101 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
102 ":${hostname}:${netdev}:off panic=1\0" \
wdenk8bde7f72003-06-27 21:31:46 +0000103 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100104 "bootm ${kernel_addr}\0" \
wdenk8bde7f72003-06-27 21:31:46 +0000105 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100106 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
107 "net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk8bde7f72003-06-27 21:31:46 +0000108 "rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0" \
109 "bootfile=pImage-sc855t\0" \
110 "kernel_addr=48000000\0" \
111 "ramdisk_addr=48100000\0" \
112 ""
wdenkdc7c9a12003-03-26 06:55:25 +0000113#define CONFIG_BOOTCOMMAND \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200114 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
115 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenkdc7c9a12003-03-26 06:55:25 +0000116 "tftpboot 0x210000 pImage-sc855t;bootm 0x210000"
117
118#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkdc7c9a12003-03-26 06:55:25 +0000120
121
122#ifdef CONFIG_LCD
123# undef CONFIG_STATUS_LED /* disturbs display */
124#else
125# define CONFIG_STATUS_LED 1 /* Status LED enabled */
126#endif /* CONFIG_LCD */
127
128#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
129
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500130/*
131 * BOOTP options
132 */
133#define CONFIG_BOOTP_SUBNETMASK
134#define CONFIG_BOOTP_GATEWAY
135#define CONFIG_BOOTP_HOSTNAME
136#define CONFIG_BOOTP_BOOTPATH
137#define CONFIG_BOOTP_BOOTFILESIZE
wdenkdc7c9a12003-03-26 06:55:25 +0000138
139#define CONFIG_MAC_PARTITION
140#define CONFIG_DOS_PARTITION
141
142#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
143
wdenkdc7c9a12003-03-26 06:55:25 +0000144
Jon Loeliger46da1e92007-07-04 22:33:30 -0500145/*
146 * Command line configuration.
147 */
148#include <config_cmd_default.h>
149
150#define CONFIG_CMD_ASKENV
151#define CONFIG_CMD_DHCP
Jon Loeliger46da1e92007-07-04 22:33:30 -0500152#define CONFIG_CMD_DATE
153
wdenkdc7c9a12003-03-26 06:55:25 +0000154/*
155 * Miscellaneous configurable options
156 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_LONGHELP /* undef to save memory */
158#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenkdc7c9a12003-03-26 06:55:25 +0000159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#ifdef CONFIG_SYS_HUSH_PARSER
wdenkdc7c9a12003-03-26 06:55:25 +0000161#endif
162
Jon Loeliger46da1e92007-07-04 22:33:30 -0500163#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkdc7c9a12003-03-26 06:55:25 +0000165#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkdc7c9a12003-03-26 06:55:25 +0000167#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
169#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
170#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkdc7c9a12003-03-26 06:55:25 +0000171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
173#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkdc7c9a12003-03-26 06:55:25 +0000174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkdc7c9a12003-03-26 06:55:25 +0000176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkdc7c9a12003-03-26 06:55:25 +0000178
wdenkdc7c9a12003-03-26 06:55:25 +0000179/*
180 * Low Level Configuration Settings
181 * (address mappings, register initial values, etc.)
182 * You should know what you are doing if you make changes here.
183 */
184/*-----------------------------------------------------------------------
185 * Internal Memory Mapped Register
186 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_IMMR 0xFF000000
wdenkdc7c9a12003-03-26 06:55:25 +0000188
189/*-----------------------------------------------------------------------
190 * Definitions for initial stack pointer and data area (in DPRAM)
191 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200193#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200194#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkdc7c9a12003-03-26 06:55:25 +0000196
197/*-----------------------------------------------------------------------
198 * Start addresses for the final memory configuration
199 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkdc7c9a12003-03-26 06:55:25 +0000201 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_SDRAM_BASE 0x00000000
203#define CONFIG_SYS_FLASH_BASE 0x40000000
204#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */
205#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
206#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkdc7c9a12003-03-26 06:55:25 +0000207
208/*
209 * For booting Linux, the board info and command line data
210 * have to be in the first 8 MB of memory, since this is
211 * the maximum mapped by the Linux kernel during initialization.
212 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkdc7c9a12003-03-26 06:55:25 +0000214
215/*-----------------------------------------------------------------------
216 * FLASH organization
217 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
219#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
wdenkdc7c9a12003-03-26 06:55:25 +0000220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
222#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkdc7c9a12003-03-26 06:55:25 +0000223
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200224#define CONFIG_ENV_IS_IN_FLASH 1
wdenkdc7c9a12003-03-26 06:55:25 +0000225
226#ifdef CONFIG_BOOT_8B
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200227#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
228#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
wdenkdc7c9a12003-03-26 06:55:25 +0000229#elif defined (CONFIG_BOOT_16B)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200230#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
231#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
wdenkdc7c9a12003-03-26 06:55:25 +0000232#elif defined (CONFIG_BOOT_32B)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200233#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
234#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenkdc7c9a12003-03-26 06:55:25 +0000235#endif
236
237/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200238#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
239#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkdc7c9a12003-03-26 06:55:25 +0000240
241
242/*-----------------------------------------------------------------------
243 * Hardware Information Block
244 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
246#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
247#define CONFIG_SYS_HWINFO_MAGIC 0x46454C38 /* 'SVM8' */
wdenkdc7c9a12003-03-26 06:55:25 +0000248
249/*-----------------------------------------------------------------------
250 * Cache Configuration
251 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500253#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkdc7c9a12003-03-26 06:55:25 +0000255#endif
256
257/*-----------------------------------------------------------------------
258 * SYPCR - System Protection Control 11-9
259 * SYPCR can only be written once after reset!
260 *-----------------------------------------------------------------------
261 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
262 */
263#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264/*#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkdc7c9a12003-03-26 06:55:25 +0000265 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
266*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \
wdenkdc7c9a12003-03-26 06:55:25 +0000268 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
269#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_SYPCR 0xffffff88
wdenkdc7c9a12003-03-26 06:55:25 +0000271#endif
272
273/*-----------------------------------------------------------------------
274 * SIUMCR - SIU Module Configuration 11-6
275 *-----------------------------------------------------------------------
276 * PCMCIA config., multi-function pin tri-state
277 */
278#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279/*#define CONFIG_SYS_SIUMCR 0x00610c00 */
280#define CONFIG_SYS_SIUMCR 0x00000000
wdenkdc7c9a12003-03-26 06:55:25 +0000281#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkdc7c9a12003-03-26 06:55:25 +0000283#endif /* CONFIG_CAN_DRIVER */
284
285/*-----------------------------------------------------------------------
286 * TBSCR - Time Base Status and Control 11-26
287 *-----------------------------------------------------------------------
288 * Clear Reference Interrupt Status, Timebase freezing enabled
289 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_TBSCR 0x0001
wdenkdc7c9a12003-03-26 06:55:25 +0000291
292/*-----------------------------------------------------------------------
293 * RTCSC - Real-Time Clock Status and Control Register 11-27
294 *-----------------------------------------------------------------------
295 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_RTCSC 0x00c3
wdenkdc7c9a12003-03-26 06:55:25 +0000297
298/*-----------------------------------------------------------------------
299 * PISCR - Periodic Interrupt Status and Control 11-31
300 *-----------------------------------------------------------------------
301 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
302 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_PISCR 0x0000
wdenkdc7c9a12003-03-26 06:55:25 +0000304
305/*-----------------------------------------------------------------------
306 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
307 *-----------------------------------------------------------------------
308 * Reset PLL lock status sticky bit, timer expired status bit and timer
309 * interrupt status bit
310 */
311#if defined (CONFIG_100MHz)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_PLPRCR 0x06301000
wdenkdc7c9a12003-03-26 06:55:25 +0000313#define CONFIG_8xx_GCLK_FREQ 100000000
314#elif defined (CONFIG_80MHz)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_PLPRCR 0x04f01000
wdenkdc7c9a12003-03-26 06:55:25 +0000316#define CONFIG_8xx_GCLK_FREQ 80000000
wdenk8bde7f72003-06-27 21:31:46 +0000317#elif defined(CONFIG_75MHz)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_PLPRCR 0x04a00100
wdenkdc7c9a12003-03-26 06:55:25 +0000319#define CONFIG_8xx_GCLK_FREQ 75000000
wdenk8bde7f72003-06-27 21:31:46 +0000320#elif defined(CONFIG_66MHz)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_PLPRCR 0x04101000
wdenkdc7c9a12003-03-26 06:55:25 +0000322#define CONFIG_8xx_GCLK_FREQ 66000000
wdenk8bde7f72003-06-27 21:31:46 +0000323#elif defined(CONFIG_50MHz)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_PLPRCR 0x03101000
wdenkdc7c9a12003-03-26 06:55:25 +0000325#define CONFIG_8xx_GCLK_FREQ 50000000
wdenk8bde7f72003-06-27 21:31:46 +0000326#endif
wdenkdc7c9a12003-03-26 06:55:25 +0000327
328/*-----------------------------------------------------------------------
329 * SCCR - System Clock and reset Control Register 15-27
330 *-----------------------------------------------------------------------
331 * Set clock output, timebase and RTC source and divider,
332 * power management and some other internal clocks
333 */
334#define SCCR_MASK SCCR_EBDF11
wdenk8bde7f72003-06-27 21:31:46 +0000335#ifdef CONFIG_BUS_DIV2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_SCCR 0x02020000 | SCCR_RTSEL
wdenkdc7c9a12003-03-26 06:55:25 +0000337#else /* up to 50 MHz we use a 1:1 clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_SCCR 0x02000000 | SCCR_RTSEL
wdenk8bde7f72003-06-27 21:31:46 +0000339#endif
wdenkdc7c9a12003-03-26 06:55:25 +0000340
341/*-----------------------------------------------------------------------
342 * PCMCIA stuff
343 *-----------------------------------------------------------------------
344 *
345 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
347#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
348#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
349#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
350#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
351#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
352#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
353#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkdc7c9a12003-03-26 06:55:25 +0000354
355/*-----------------------------------------------------------------------
356 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
357 *-----------------------------------------------------------------------
358 */
359
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200360#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
wdenkdc7c9a12003-03-26 06:55:25 +0000361
362#define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */
363#undef CONFIG_IDE_LED /* LED for ide not supported */
364#undef CONFIG_IDE_RESET /* reset for ide not supported */
365
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
367#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkdc7c9a12003-03-26 06:55:25 +0000368
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100010
370#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
371/*#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0C00 */
372#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O
wdenkdc7c9a12003-03-26 06:55:25 +0000373 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_ATA_REG_OFFSET 0x0200 /* Offset for normal register accesses
wdenkdc7c9a12003-03-26 06:55:25 +0000375 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_ATA_ALT_OFFSET 0x0210 /* Offset for alternate registers
wdenkdc7c9a12003-03-26 06:55:25 +0000377 */
wdenk8bde7f72003-06-27 21:31:46 +0000378#define CONFIG_ATAPI
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_PIO_MODE 0
wdenkdc7c9a12003-03-26 06:55:25 +0000380
381/*-----------------------------------------------------------------------
382 *
383 *-----------------------------------------------------------------------
384 *
385 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386/*#define CONFIG_SYS_DER 0x2002000F*/
387#define CONFIG_SYS_DER 0x0
wdenkdc7c9a12003-03-26 06:55:25 +0000388
389/*
390 * Init Memory Controller:
391 *
392 * BR0/1 and OR0/1 (FLASH)
393 */
394
395#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
396#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
397
398/* used to re-map FLASH both when starting from SRAM or FLASH:
399 * restrict access enough to keep SRAM working (if any)
400 * but not too much to meddle with FLASH accesses
401 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
403#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkdc7c9a12003-03-26 06:55:25 +0000404
405/*
406 * FLASH timing:
407 */
wdenk8bde7f72003-06-27 21:31:46 +0000408#if defined(CONFIG_100MHz)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_OR_TIMING_FLASH 0x000002f4
410#define CONFIG_SYS_OR_TIMING_DOC 0x000002f4
411#define CONFIG_SYS_MxMR_PTx 0x61000000
412#define CONFIG_SYS_MPTPR 0x400
wdenkdc7c9a12003-03-26 06:55:25 +0000413
414#elif defined(CONFIG_80MHz)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4
416#define CONFIG_SYS_OR_TIMING_DOC 0x000001f4
417#define CONFIG_SYS_MxMR_PTx 0x4e000000
418#define CONFIG_SYS_MPTPR 0x400
wdenkdc7c9a12003-03-26 06:55:25 +0000419
wdenk8bde7f72003-06-27 21:31:46 +0000420#elif defined(CONFIG_75MHz)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#define CONFIG_SYS_OR_TIMING_FLASH 0x000008f4
422#define CONFIG_SYS_OR_TIMING_DOC 0x000002f4
423#define CONFIG_SYS_MxMR_PTx 0x49000000
424#define CONFIG_SYS_MPTPR 0x400
wdenkdc7c9a12003-03-26 06:55:25 +0000425
426#elif defined(CONFIG_66MHz)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenk8bde7f72003-06-27 21:31:46 +0000428 OR_SCY_3_CLK | OR_EHTR | OR_BI)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429/*#define CONFIG_SYS_OR_TIMING_FLASH 0x000001f4 */
430#define CONFIG_SYS_OR_TIMING_DOC 0x000003f4
431#define CONFIG_SYS_MxMR_PTx 0x40000000
432#define CONFIG_SYS_MPTPR 0x400
wdenkdc7c9a12003-03-26 06:55:25 +0000433
434#else /* 50 MHz */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4
436#define CONFIG_SYS_OR_TIMING_DOC 0x000001f4
437#define CONFIG_SYS_MxMR_PTx 0x30000000
438#define CONFIG_SYS_MPTPR 0x400
wdenkdc7c9a12003-03-26 06:55:25 +0000439#endif /*CONFIG_??MHz */
440
441
442#if defined (CONFIG_BOOT_8B) /* 512K X 8 ,29F040 , 2MB space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443#define CONFIG_SYS_OR0_PRELIM (0xffe00000 | CONFIG_SYS_OR_TIMING_FLASH)
444#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8)
wdenkdc7c9a12003-03-26 06:55:25 +0000445#elif defined (CONFIG_BOOT_16B) /* 29lv160 X 16 , 4MB space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200446#define CONFIG_SYS_OR0_PRELIM (0xffc00000 | CONFIG_SYS_OR_TIMING_FLASH)
447#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
wdenkdc7c9a12003-03-26 06:55:25 +0000448#elif defined( CONFIG_BOOT_32B ) /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200449#define CONFIG_SYS_OR0_PRELIM (0xfc000000 | CONFIG_SYS_OR_TIMING_FLASH)
450#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkdc7c9a12003-03-26 06:55:25 +0000451#else
452#error Boot device port size missing.
453#endif
454
455/*
456 * Disk-On-Chip configuration
457 */
458
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459#define CONFIG_SYS_DOC_SHORT_TIMEOUT
460#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
wdenkdc7c9a12003-03-26 06:55:25 +0000461
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462#define CONFIG_SYS_DOC_SUPPORT_2000
463#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
464#define CONFIG_SYS_DOC_BASE 0x80000000
wdenkdc7c9a12003-03-26 06:55:25 +0000465
wdenkdc7c9a12003-03-26 06:55:25 +0000466#endif /* __CONFIG_H */