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Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +08001/*
2 * (C) Copyright 2009 Faraday Technology
3 * Po-Yu Chuang <ratbert@faraday-tech.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20/*
21 * SDRAM Controller
22 */
23#ifndef __FTSDMC020_H
24#define __FTSDMC020_H
25
26#define FTSDMC020_OFFSET_TP0 0x00
27#define FTSDMC020_OFFSET_TP1 0x04
28#define FTSDMC020_OFFSET_CR 0x08
29#define FTSDMC020_OFFSET_BANK0_BSR 0x0C
30#define FTSDMC020_OFFSET_BANK1_BSR 0x10
31#define FTSDMC020_OFFSET_BANK2_BSR 0x14
32#define FTSDMC020_OFFSET_BANK3_BSR 0x18
33#define FTSDMC020_OFFSET_BANK4_BSR 0x1C
34#define FTSDMC020_OFFSET_BANK5_BSR 0x20
35#define FTSDMC020_OFFSET_BANK6_BSR 0x24
36#define FTSDMC020_OFFSET_BANK7_BSR 0x28
37#define FTSDMC020_OFFSET_ACR 0x34
38
39/*
40 * Timing Parametet 0 Register
41 */
42#define FTSDMC020_TP0_TCL(x) ((x) & 0x3)
43#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4)
44#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8)
45#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12)
46#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16)
47#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20)
48
49/*
50 * Timing Parametet 1 Register
51 */
52#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff)
53#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16)
54#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20)
55
56/*
57 * Configuration Register
58 */
59#define FTSDMC020_CR_SREF (1 << 0)
60#define FTSDMC020_CR_PWDN (1 << 1)
61#define FTSDMC020_CR_ISMR (1 << 2)
62#define FTSDMC020_CR_IREF (1 << 3)
63#define FTSDMC020_CR_IPREC (1 << 4)
64#define FTSDMC020_CR_REFTYPE (1 << 5)
65
66/*
67 * SDRAM External Bank Base/Size Register
68 */
69#define FTSDMC020_BANK_ENABLE (1 << 28)
70
71#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16)
72
73#define FTSDMC020_BANK_DDW_X4 (0 << 12)
74#define FTSDMC020_BANK_DDW_X8 (1 << 12)
75#define FTSDMC020_BANK_DDW_X16 (2 << 12)
76#define FTSDMC020_BANK_DDW_X32 (3 << 12)
77
78#define FTSDMC020_BANK_DSZ_16M (0 << 8)
79#define FTSDMC020_BANK_DSZ_64M (1 << 8)
80#define FTSDMC020_BANK_DSZ_128M (2 << 8)
81#define FTSDMC020_BANK_DSZ_256M (3 << 8)
82
83#define FTSDMC020_BANK_MBW_8 (0 << 4)
84#define FTSDMC020_BANK_MBW_16 (1 << 4)
85#define FTSDMC020_BANK_MBW_32 (2 << 4)
86
87#define FTSDMC020_BANK_SIZE_1M 0x0
88#define FTSDMC020_BANK_SIZE_2M 0x1
89#define FTSDMC020_BANK_SIZE_4M 0x2
90#define FTSDMC020_BANK_SIZE_8M 0x3
91#define FTSDMC020_BANK_SIZE_16M 0x4
92#define FTSDMC020_BANK_SIZE_32M 0x5
93#define FTSDMC020_BANK_SIZE_64M 0x6
94#define FTSDMC020_BANK_SIZE_128M 0x7
95#define FTSDMC020_BANK_SIZE_256M 0x8
96
97/*
98 * Arbiter Control Register
99 */
100#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f)
101#define FTSDMC020_ACR_TOE (1 << 8)
102
103#endif /* __FTSDMC020_H */