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Mingkai Hua8d97582013-07-04 17:33:43 +08001/**
2 * Copyright 2013 Freescale Semiconductor
3 * Author: Mingkai Hu <Mingkai.hu@freescale.com>
4 * Po Liu <Po.Liu@freescale.com>
5 *
York Sun3aab0cd2013-08-12 14:57:12 -07006 * SPDX-License-Identifier: GPL-2.0+
Mingkai Hua8d97582013-07-04 17:33:43 +08007 *
8 * This file provides support for the board-specific CPLD used on some Freescale
9 * reference boards.
10 *
11 * The following macros need to be defined:
12 *
13 * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
14 * CPLD register map
15 *
16 */
17
18#include <common.h>
19#include <command.h>
20#include <asm/io.h>
21
22#include "cpld.h"
23/**
24 * Set the boot bank to the alternate bank
25 */
26void cpld_set_altbank(u8 banksel)
27{
28 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
29 u8 reg11;
30
31 reg11 = in_8(&cpld_data->flhcsr);
32
33 switch (banksel) {
34 case 1:
35 out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
36 | CPLD_BANKSEL_EN | CPLD_SELECT_BANK1);
37 break;
38 case 2:
39 out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
40 | CPLD_BANKSEL_EN | CPLD_SELECT_BANK2);
41 break;
42 case 3:
43 out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
44 | CPLD_BANKSEL_EN | CPLD_SELECT_BANK3);
45 break;
46 case 4:
47 out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
48 | CPLD_BANKSEL_EN | CPLD_SELECT_BANK4);
49 break;
50 default:
51 printf("Invalid value! [1-4]\n");
52 return;
53 }
54
55 udelay(100);
56 do_reset(NULL, 0, 0, NULL);
57}
58
59/**
60 * Set the boot bank to the default bank
61 */
62void cpld_set_defbank(void)
63{
64 cpld_set_altbank(4);
65}
66
67#ifdef DEBUG
68static void cpld_dump_regs(void)
69{
70 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
71
72 printf("chipid1 = 0x%02x\n", in_8(&cpld_data->chipid1));
73 printf("chipid2 = 0x%02x\n", in_8(&cpld_data->chipid2));
74 printf("hwver = 0x%02x\n", in_8(&cpld_data->hwver));
75 printf("cpldver = 0x%02x\n", in_8(&cpld_data->cpldver));
76 printf("rstcon = 0x%02x\n", in_8(&cpld_data->rstcon));
77 printf("flhcsr = 0x%02x\n", in_8(&cpld_data->flhcsr));
78 printf("wdcsr = 0x%02x\n", in_8(&cpld_data->wdcsr));
79 printf("wdkick = 0x%02x\n", in_8(&cpld_data->wdkick));
80 printf("fancsr = 0x%02x\n", in_8(&cpld_data->fancsr));
81 printf("ledcsr = 0x%02x\n", in_8(&cpld_data->ledcsr));
82 printf("misc = 0x%02x\n", in_8(&cpld_data->misccsr));
83 printf("bootor = 0x%02x\n", in_8(&cpld_data->bootor));
84 printf("bootcfg1 = 0x%02x\n", in_8(&cpld_data->bootcfg1));
85 printf("bootcfg2 = 0x%02x\n", in_8(&cpld_data->bootcfg2));
86 printf("bootcfg3 = 0x%02x\n", in_8(&cpld_data->bootcfg3));
87 printf("bootcfg4 = 0x%02x\n", in_8(&cpld_data->bootcfg4));
88 putc('\n');
89}
90#endif
91
92int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
93{
94 int rc = 0;
95 unsigned char value;
96
97 if (argc <= 1)
98 return cmd_usage(cmdtp);
99
100 if (strcmp(argv[1], "reset") == 0) {
101 if (!strcmp(argv[2], "altbank") && argv[3]) {
102 value = (u8)simple_strtoul(argv[3], NULL, 16);
103 cpld_set_altbank(value);
104 } else if (!argv[2])
105 cpld_set_defbank();
106 else
107 cmd_usage(cmdtp);
108#ifdef DEBUG
109 } else if (strcmp(argv[1], "dump") == 0) {
110 cpld_dump_regs();
111#endif
112 } else
113 rc = cmd_usage(cmdtp);
114
115 return rc;
116}
117
118U_BOOT_CMD(
119 cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
120 "Reset the board using the CPLD sequencer",
121 "reset - hard reset to default bank 4\n"
122 "cpld_cmd reset altbank [bank]- reset to alternate bank\n"
123 " - [bank] bank value select 1-4\n"
124 " - bank 1 on the flash 0x0000000~0x0ffffff\n"
125 " - bank 2 on the flash 0x1000000~0x1ffffff\n"
126 " - bank 3 on the flash 0x2000000~0x2ffffff\n"
127 " - bank 4 on the flash 0x3000000~0x3ffffff\n"
128#ifdef DEBUG
129 "cpld_cmd dump - display the CPLD registers\n"
130#endif
131 );