blob: 599cb6dc42ddbf82ac524d10d4dedaf145baf331 [file] [log] [blame]
wdenk1c437712004-01-16 00:30:56 +00001#ifndef __LINUX_PS2MULT_H
2#define __LINUX_PS2MULT_H
3
4#define kbd_request_region() ps2mult_init()
5#define kbd_request_irq(handler) ps2mult_request_irq(handler)
6
7#define kbd_read_input() ps2mult_read_input()
8#define kbd_read_status() ps2mult_read_status()
9#define kbd_write_output(val) ps2mult_write_output(val)
10#define kbd_write_command(val) ps2mult_write_command(val)
11
12#define aux_request_irq(hand, dev_id) 0
13#define aux_free_irq(dev_id)
14
15#define PS2MULT_KB_SELECTOR 0xA0
16#define PS2MULT_MS_SELECTOR 0xA1
17#define PS2MULT_ESCAPE 0x7D
18#define PS2MULT_BSYNC 0x7E
19#define PS2MULT_SESSION_START 0x55
20#define PS2MULT_SESSION_END 0x56
21
22#define PS2BUF_SIZE 512 /* power of 2, please */
23
wdenkc837dcb2004-01-20 23:12:12 +000024#ifndef CONFIG_PS2MULT_DELAY
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020025#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
wdenkc837dcb2004-01-20 23:12:12 +000026#endif
27
wdenk1c437712004-01-16 00:30:56 +000028 /* PS/2 controller interface (include/asm/keyboard.h)
29 */
30extern int ps2mult_init (void);
31extern int ps2mult_request_irq(void (*handler)(void *));
32extern u_char ps2mult_read_input(void);
33extern u_char ps2mult_read_status(void);
34extern void ps2mult_write_output(u_char val);
35extern void ps2mult_write_command(u_char val);
36
wdenkc837dcb2004-01-20 23:12:12 +000037extern void ps2mult_early_init (void);
wdenk1c437712004-01-16 00:30:56 +000038extern void ps2mult_callback (int in_cnt);
39
40 /* Simple serial interface
41 */
42extern int ps2ser_init(void);
43extern void ps2ser_putc(int chr);
44extern int ps2ser_getc(void);
45extern int ps2ser_check(void);
46
47
48 /* Serial related stuff
49 */
50struct serial_state {
51 int baud_base;
52 int irq;
53 u8 *iomem_base;
54};
55
56#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
57#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
58#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
59
60#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
61#define UART_IER 1 /* Out: Interrupt Enable Register */
62
63#define UART_IIR 2 /* In: Interrupt ID Register */
64#define UART_FCR 2 /* Out: FIFO Control Register */
65
66#define UART_LCR 3 /* Out: Line Control Register */
67#define UART_MCR 4 /* Out: Modem Control Register */
68#define UART_LSR 5 /* In: Line Status Register */
69#define UART_MSR 6 /* In: Modem Status Register */
70#define UART_SCR 7 /* I/O: Scratch Register */
71
72/*
73 * These are the definitions for the FIFO Control Register
74 * (16650 only)
75 */
76#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
77#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
78#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
79#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
80#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
81#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
82#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
83#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
84#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
85
86/*
87 * These are the definitions for the Line Control Register
88 *
89 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
90 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
91 */
92#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
93#define UART_LCR_SBC 0x40 /* Set break control */
94#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
95#define UART_LCR_EPAR 0x10 /* Even parity select */
96#define UART_LCR_PARITY 0x08 /* Parity Enable */
97#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
98#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
99#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
100#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
101#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
102
103/*
104 * These are the definitions for the Line Status Register
105 */
106#define UART_LSR_TEMT 0x40 /* Transmitter empty */
107#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
108#define UART_LSR_BI 0x10 /* Break interrupt indicator */
109#define UART_LSR_FE 0x08 /* Frame error indicator */
110#define UART_LSR_PE 0x04 /* Parity error indicator */
111#define UART_LSR_OE 0x02 /* Overrun error indicator */
112#define UART_LSR_DR 0x01 /* Receiver data ready */
113
114/*
115 * These are the definitions for the Interrupt Identification Register
116 */
117#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
118#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
119
120#define UART_IIR_MSI 0x00 /* Modem status interrupt */
121#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
122#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
123#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
124
125/*
126 * These are the definitions for the Interrupt Enable Register
127 */
128#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
129#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
130#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
131#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
132
133/*
134 * These are the definitions for the Modem Control Register
135 */
136#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
137#define UART_MCR_OUT2 0x08 /* Out2 complement */
138#define UART_MCR_OUT1 0x04 /* Out1 complement */
139#define UART_MCR_RTS 0x02 /* RTS complement */
140#define UART_MCR_DTR 0x01 /* DTR complement */
141
142/*
143 * These are the definitions for the Modem Status Register
144 */
145#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
146#define UART_MSR_RI 0x40 /* Ring Indicator */
147#define UART_MSR_DSR 0x20 /* Data Set Ready */
148#define UART_MSR_CTS 0x10 /* Clear to Send */
149#define UART_MSR_DDCD 0x08 /* Delta DCD */
150#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
151#define UART_MSR_DDSR 0x02 /* Delta DSR */
152#define UART_MSR_DCTS 0x01 /* Delta CTS */
153#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
154
155#endif /* __LINUX_PS2MULT_H */