blob: 7d82c27c6edd7d35c9b15fc3ec6f62dce4f035bb [file] [log] [blame]
wdenk3f85ce22004-02-23 16:11:30 +00001/*
2 * Copyright (c) 2004 Picture Elements, Inc.
3 * Stephen Williams (XXXXXXXXXXXXXXXX)
4 *
5 * This source code is free software; you can redistribute it
6 * and/or modify it in source code form under the terms of the GNU
7 * General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
19 */
wdenk3f85ce22004-02-23 16:11:30 +000020
21/*
22 * The Xilinx SystemACE chip support is activated by defining
23 * CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE
24 * to set the base address of the device. This code currently
25 * assumes that the chip is connected via a byte-wide bus.
26 *
27 * The CONFIG_SYSTEMACE also adds to fat support the device class
28 * "ace" that allows the user to execute "fatls ace 0" and the
29 * like. This works by making the systemace_get_dev function
30 * available to cmd_fat.c:get_dev and filling in a block device
31 * description that has all the bits needed for FAT support to
32 * read sectors.
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +020033 *
Wolfgang Denkfe599e12005-08-07 23:55:50 +020034 * According to Xilinx technical support, before accessing the
35 * SystemACE CF you need to set the following control bits:
Grant Likely984618f2007-02-20 09:05:16 +010036 * FORCECFGMODE : 1
37 * CFGMODE : 0
38 * CFGSTART : 0
wdenk3f85ce22004-02-23 16:11:30 +000039 */
40
Grant Likely984618f2007-02-20 09:05:16 +010041#include <common.h>
42#include <command.h>
43#include <systemace.h>
44#include <part.h>
45#include <asm/io.h>
wdenk3f85ce22004-02-23 16:11:30 +000046
47#ifdef CONFIG_SYSTEMACE
48
49/*
50 * The ace_readw and writew functions read/write 16bit words, but the
51 * offset value is the BYTE offset as most used in the Xilinx
52 * datasheet for the SystemACE chip. The CFG_SYSTEMACE_BASE is defined
53 * to be the base address for the chip, usually in the local
54 * peripheral bus.
55 */
wdenka5bbcc32004-09-29 22:55:14 +000056#if (CFG_SYSTEMACE_WIDTH == 8)
57#if !defined(__BIG_ENDIAN)
Grant Likelyf4852eb2007-02-20 09:05:31 +010058#define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)<<8) | \
Wolfgang Denk74357112007-02-27 14:26:04 +010059 (readb(CFG_SYSTEMACE_BASE+off+1)))
Stefan Roeseda049952007-02-21 13:44:34 +010060#define ace_writew(val, off) {writeb(val>>8, CFG_SYSTEMACE_BASE+off); \
61 writeb(val, CFG_SYSTEMACE_BASE+off+1);}
wdenka5bbcc32004-09-29 22:55:14 +000062#else
Grant Likelyf4852eb2007-02-20 09:05:31 +010063#define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)) | \
Wolfgang Denk74357112007-02-27 14:26:04 +010064 (readb(CFG_SYSTEMACE_BASE+off+1)<<8))
Stefan Roeseda049952007-02-21 13:44:34 +010065#define ace_writew(val, off) {writeb(val, CFG_SYSTEMACE_BASE+off); \
66 writeb(val>>8, CFG_SYSTEMACE_BASE+off+1);}
wdenka5bbcc32004-09-29 22:55:14 +000067#endif
68#else
Stefan Roesed93e2212007-02-20 13:17:42 +010069#define ace_readw(off) (in16(CFG_SYSTEMACE_BASE+off))
70#define ace_writew(val, off) (out16(CFG_SYSTEMACE_BASE+off,val))
wdenka5bbcc32004-09-29 22:55:14 +000071#endif
wdenk3f85ce22004-02-23 16:11:30 +000072
73/* */
74
Grant Likely984618f2007-02-20 09:05:16 +010075static unsigned long systemace_read(int dev, unsigned long start,
Wolfgang Denk74357112007-02-27 14:26:04 +010076 unsigned long blkcnt, void *buffer);
wdenk3f85ce22004-02-23 16:11:30 +000077
Grant Likely984618f2007-02-20 09:05:16 +010078static block_dev_desc_t systemace_dev = { 0 };
wdenk3f85ce22004-02-23 16:11:30 +000079
80static int get_cf_lock(void)
81{
Grant Likely984618f2007-02-20 09:05:16 +010082 int retry = 10;
wdenk3f85ce22004-02-23 16:11:30 +000083
84 /* CONTROLREG = LOCKREG */
Grant Likely984618f2007-02-20 09:05:16 +010085 unsigned val = ace_readw(0x18);
86 val |= 0x0002;
87 ace_writew((val & 0xffff), 0x18);
wdenk3f85ce22004-02-23 16:11:30 +000088
89 /* Wait for MPULOCK in STATUSREG[15:0] */
Grant Likely984618f2007-02-20 09:05:16 +010090 while (!(ace_readw(0x04) & 0x0002)) {
wdenk3f85ce22004-02-23 16:11:30 +000091
Grant Likely984618f2007-02-20 09:05:16 +010092 if (retry < 0)
93 return -1;
wdenk3f85ce22004-02-23 16:11:30 +000094
Grant Likely984618f2007-02-20 09:05:16 +010095 udelay(100000);
96 retry -= 1;
97 }
wdenk3f85ce22004-02-23 16:11:30 +000098
Grant Likely984618f2007-02-20 09:05:16 +010099 return 0;
wdenk3f85ce22004-02-23 16:11:30 +0000100}
101
102static void release_cf_lock(void)
103{
Grant Likely984618f2007-02-20 09:05:16 +0100104 unsigned val = ace_readw(0x18);
105 val &= ~(0x0002);
106 ace_writew((val & 0xffff), 0x18);
wdenk3f85ce22004-02-23 16:11:30 +0000107}
108
Grant Likely984618f2007-02-20 09:05:16 +0100109block_dev_desc_t *systemace_get_dev(int dev)
wdenk3f85ce22004-02-23 16:11:30 +0000110{
111 /* The first time through this, the systemace_dev object is
112 not yet initialized. In that case, fill it in. */
Grant Likely984618f2007-02-20 09:05:16 +0100113 if (systemace_dev.blksz == 0) {
114 systemace_dev.if_type = IF_TYPE_UNKNOWN;
115 systemace_dev.dev = 0;
116 systemace_dev.part_type = PART_TYPE_UNKNOWN;
117 systemace_dev.type = DEV_TYPE_HARDDISK;
118 systemace_dev.blksz = 512;
119 systemace_dev.removable = 1;
120 systemace_dev.block_read = systemace_read;
Wolfgang Denkfe599e12005-08-07 23:55:50 +0200121
Stefan Roesed93e2212007-02-20 13:17:42 +0100122 /*
Stefan Roese8274ec02007-02-22 07:40:23 +0100123 * Ensure the correct bus mode (8/16 bits) gets enabled
Stefan Roesed93e2212007-02-20 13:17:42 +0100124 */
Stefan Roese8274ec02007-02-22 07:40:23 +0100125 ace_writew(CFG_SYSTEMACE_WIDTH == 8 ? 0 : 0x0001, 0);
Stefan Roesed93e2212007-02-20 13:17:42 +0100126
Grant Likely984618f2007-02-20 09:05:16 +0100127 init_part(&systemace_dev);
Wolfgang Denkfe599e12005-08-07 23:55:50 +0200128
Grant Likely984618f2007-02-20 09:05:16 +0100129 }
wdenk3f85ce22004-02-23 16:11:30 +0000130
Grant Likely984618f2007-02-20 09:05:16 +0100131 return &systemace_dev;
wdenk3f85ce22004-02-23 16:11:30 +0000132}
133
134/*
135 * This function is called (by dereferencing the block_read pointer in
136 * the dev_desc) to read blocks of data. The return value is the
137 * number of blocks read. A zero return indicates an error.
138 */
Grant Likely984618f2007-02-20 09:05:16 +0100139static unsigned long systemace_read(int dev, unsigned long start,
Wolfgang Denk74357112007-02-27 14:26:04 +0100140 unsigned long blkcnt, void *buffer)
wdenk3f85ce22004-02-23 16:11:30 +0000141{
Grant Likely984618f2007-02-20 09:05:16 +0100142 int retry;
143 unsigned blk_countdown;
Grant Likelyeb867a72007-02-20 09:05:45 +0100144 unsigned char *dp = buffer;
Grant Likely984618f2007-02-20 09:05:16 +0100145 unsigned val;
wdenk3f85ce22004-02-23 16:11:30 +0000146
Grant Likely984618f2007-02-20 09:05:16 +0100147 if (get_cf_lock() < 0) {
148 unsigned status = ace_readw(0x04);
wdenk3f85ce22004-02-23 16:11:30 +0000149
Grant Likely984618f2007-02-20 09:05:16 +0100150 /* If CFDETECT is false, card is missing. */
151 if (!(status & 0x0010)) {
152 printf("** CompactFlash card not present. **\n");
153 return 0;
154 }
wdenk3f85ce22004-02-23 16:11:30 +0000155
Grant Likely984618f2007-02-20 09:05:16 +0100156 printf("**** ACE locked away from me (STATUSREG=%04x)\n",
157 status);
158 return 0;
159 }
wdenke7c85682004-02-27 08:21:54 +0000160#ifdef DEBUG_SYSTEMACE
Grant Likely984618f2007-02-20 09:05:16 +0100161 printf("... systemace read %lu sectors at %lu\n", blkcnt, start);
wdenke7c85682004-02-27 08:21:54 +0000162#endif
163
Grant Likely984618f2007-02-20 09:05:16 +0100164 retry = 2000;
165 for (;;) {
166 val = ace_readw(0x04);
wdenk3f85ce22004-02-23 16:11:30 +0000167
Grant Likely984618f2007-02-20 09:05:16 +0100168 /* If CFDETECT is false, card is missing. */
169 if (!(val & 0x0010)) {
170 printf("**** ACE CompactFlash not found.\n");
171 release_cf_lock();
172 return 0;
173 }
wdenk3f85ce22004-02-23 16:11:30 +0000174
Grant Likely984618f2007-02-20 09:05:16 +0100175 /* If RDYFORCMD, then we are ready to go. */
176 if (val & 0x0100)
177 break;
wdenk3f85ce22004-02-23 16:11:30 +0000178
Grant Likely984618f2007-02-20 09:05:16 +0100179 if (retry < 0) {
180 printf("**** SystemACE not ready.\n");
181 release_cf_lock();
182 return 0;
183 }
wdenk3f85ce22004-02-23 16:11:30 +0000184
Grant Likely984618f2007-02-20 09:05:16 +0100185 udelay(1000);
186 retry -= 1;
187 }
wdenk3f85ce22004-02-23 16:11:30 +0000188
wdenke7c85682004-02-27 08:21:54 +0000189 /* The SystemACE can only transfer 256 sectors at a time, so
190 limit the current chunk of sectors. The blk_countdown
191 variable is the number of sectors left to transfer. */
wdenk3f85ce22004-02-23 16:11:30 +0000192
Grant Likely984618f2007-02-20 09:05:16 +0100193 blk_countdown = blkcnt;
194 while (blk_countdown > 0) {
195 unsigned trans = blk_countdown;
wdenk3f85ce22004-02-23 16:11:30 +0000196
Grant Likely984618f2007-02-20 09:05:16 +0100197 if (trans > 256)
198 trans = 256;
wdenk3f85ce22004-02-23 16:11:30 +0000199
wdenke7c85682004-02-27 08:21:54 +0000200#ifdef DEBUG_SYSTEMACE
Grant Likely984618f2007-02-20 09:05:16 +0100201 printf("... transfer %lu sector in a chunk\n", trans);
wdenke7c85682004-02-27 08:21:54 +0000202#endif
Grant Likely984618f2007-02-20 09:05:16 +0100203 /* Write LBA block address */
204 ace_writew((start >> 0) & 0xffff, 0x10);
Stefan Roesed93e2212007-02-20 13:17:42 +0100205 ace_writew((start >> 16) & 0x0fff, 0x12);
wdenk3f85ce22004-02-23 16:11:30 +0000206
Grant Likely984618f2007-02-20 09:05:16 +0100207 /* NOTE: in the Write Sector count below, a count of 0
208 causes a transfer of 256, so &0xff gives the right
209 value for whatever transfer count we want. */
wdenke7c85682004-02-27 08:21:54 +0000210
Grant Likely984618f2007-02-20 09:05:16 +0100211 /* Write sector count | ReadMemCardData. */
212 ace_writew((trans & 0xff) | 0x0300, 0x14);
wdenke7c85682004-02-27 08:21:54 +0000213
Wolfgang Denkd62f64c2007-05-16 00:13:33 +0200214/*
Michal Simek32556442007-04-21 21:07:22 +0200215 * For FPGA configuration via SystemACE is reset unacceptable
216 * CFGDONE bit in STATUSREG is not set to 1.
217 */
218#ifndef SYSTEMACE_CONFIG_FPGA
Grant Likely984618f2007-02-20 09:05:16 +0100219 /* Reset the configruation controller */
220 val = ace_readw(0x18);
221 val |= 0x0080;
222 ace_writew(val, 0x18);
Michal Simek32556442007-04-21 21:07:22 +0200223#endif
Wolfgang Denkfe599e12005-08-07 23:55:50 +0200224
Grant Likely984618f2007-02-20 09:05:16 +0100225 retry = trans * 16;
226 while (retry > 0) {
227 int idx;
wdenke7c85682004-02-27 08:21:54 +0000228
Grant Likely984618f2007-02-20 09:05:16 +0100229 /* Wait for buffer to become ready. */
230 while (!(ace_readw(0x04) & 0x0020)) {
231 udelay(100);
232 }
wdenke7c85682004-02-27 08:21:54 +0000233
Grant Likely984618f2007-02-20 09:05:16 +0100234 /* Read 16 words of 2bytes from the sector buffer. */
235 for (idx = 0; idx < 16; idx += 1) {
236 unsigned short val = ace_readw(0x40);
237 *dp++ = val & 0xff;
238 *dp++ = (val >> 8) & 0xff;
239 }
wdenke7c85682004-02-27 08:21:54 +0000240
Grant Likely984618f2007-02-20 09:05:16 +0100241 retry -= 1;
242 }
wdenk3f85ce22004-02-23 16:11:30 +0000243
Grant Likely984618f2007-02-20 09:05:16 +0100244 /* Clear the configruation controller reset */
245 val = ace_readw(0x18);
246 val &= ~0x0080;
247 ace_writew(val, 0x18);
Wolfgang Denkfe599e12005-08-07 23:55:50 +0200248
Grant Likely984618f2007-02-20 09:05:16 +0100249 /* Count the blocks we transfer this time. */
250 start += trans;
251 blk_countdown -= trans;
252 }
wdenk3f85ce22004-02-23 16:11:30 +0000253
Grant Likely984618f2007-02-20 09:05:16 +0100254 release_cf_lock();
wdenk3f85ce22004-02-23 16:11:30 +0000255
Grant Likely984618f2007-02-20 09:05:16 +0100256 return blkcnt;
wdenk3f85ce22004-02-23 16:11:30 +0000257}
Grant Likely984618f2007-02-20 09:05:16 +0100258#endif /* CONFIG_SYSTEMACE */