blob: 3e686beedc16cc6c2e956ebe1122c4d4b360252a [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Stephen Warren074a1fd2016-05-25 14:38:51 -06002/*
3 * Copyright (c) 2016, NVIDIA CORPORATION.
Stephen Warren074a1fd2016-05-25 14:38:51 -06004 */
5
6#ifndef _TEGRA186_GPIO_PRIV_H_
7#define _TEGRA186_GPIO_PRIV_H_
8
9/*
10 * For each GPIO, there are a set of registers than affect it, all packed
11 * back-to-back.
12 */
Simon Glasscd93d622020-05-10 11:40:13 -060013#include <linux/bitops.h>
Stephen Warren074a1fd2016-05-25 14:38:51 -060014#define TEGRA186_GPIO_ENABLE_CONFIG 0x00
15#define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
16#define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
17#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SHIFT 2
18#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK 3
19#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE 0
20#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL 1
21#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE 2
22#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE 3
23#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL_HIGH_RISING BIT(4)
24#define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE_ENABLE BIT(5)
25#define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT_ENABLE BIT(6)
26#define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMPING_ENABLE BIT(7)
27
28#define TEGRA186_GPIO_DEBOUNCE_THRESHOLD 0x04
29
30#define TEGRA186_GPIO_INPUT 0x08
31
32#define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
33#define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
34
35#define TEGRA186_GPIO_OUTPUT_VALUE 0x10
36#define TEGRA186_GPIO_OUTPUT_VALUE_HIGH 1
37
38#define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
39
40/*
41 * 8 GPIOs are packed into a port. Their registers appear back-to-back in the
42 * port's address space.
43 */
44#define TEGRA186_GPIO_PER_GPIO_STRIDE 0x20
45#define TEGRA186_GPIO_PER_GPIO_COUNT 8
46
47/*
48 * Per-port registers are packed immediately following all of a port's
49 * per-GPIO registers.
50 */
51#define TEGRA186_GPIO_INTERRUPT_STATUS_G 0x100
52#define TEGRA186_GPIO_INTERRUPT_STATUS_G_STRIDE 4
53#define TEGRA186_GPIO_INTERRUPT_STATUS_G_COUNT 8
54
55/*
56 * The registers for multiple ports are packed together back-to-back to form
57 * the overall controller.
58 */
59#define TEGRA186_GPIO_PER_PORT_STRIDE 0x200
60
61#endif