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Lukasz Majewski0f666532019-06-19 17:31:06 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5 */
6
7#include <common.h>
Simon Glass336d4612020-02-03 07:36:16 -07008#include <dm/device_compat.h>
Simon Glass61b29b82020-02-03 07:36:15 -07009#include <dm/devres.h>
Lukasz Majewski0f666532019-06-19 17:31:06 +020010#include <linux/io.h>
11#include <linux/err.h>
12#include <dm.h>
13#include <dm/pinctrl.h>
14#include <dm/read.h>
15#include "pinctrl-mxs.h"
16
17DECLARE_GLOBAL_DATA_PTR;
18
19struct mxs_pinctrl_priv {
20 void __iomem *base;
21 const struct mxs_regs *regs;
22};
23
24static unsigned long mxs_dt_node_to_map(struct udevice *conf)
25{
26 unsigned long config = 0;
27 int ret;
28 u32 val;
29
30 ret = dev_read_u32(conf, "fsl,drive-strength", &val);
31 if (!ret)
32 config = val | MA_PRESENT;
33
34 ret = dev_read_u32(conf, "fsl,voltage", &val);
35 if (!ret)
36 config |= val << VOL_SHIFT | VOL_PRESENT;
37
38 ret = dev_read_u32(conf, "fsl,pull-up", &val);
39 if (!ret)
40 config |= val << PULL_SHIFT | PULL_PRESENT;
41
42 return config;
43}
44
45static int mxs_pinctrl_set_mux(struct udevice *dev, u32 val, int bank, int pin)
46{
47 struct mxs_pinctrl_priv *iomux = dev_get_priv(dev);
48 int muxsel = MUXID_TO_MUXSEL(val), shift;
49 void __iomem *reg;
50
51 reg = iomux->base + iomux->regs->muxsel;
52 reg += bank * 0x20 + pin / 16 * 0x10;
53 shift = pin % 16 * 2;
54
55 mxs_pinctrl_rmwl(muxsel, 0x3, shift, reg);
56 debug(" mux %d,", muxsel);
57
58 return 0;
59}
60
61static int mxs_pinctrl_set_state(struct udevice *dev, struct udevice *conf)
62{
63 struct mxs_pinctrl_priv *iomux = dev_get_priv(dev);
64 u32 *pin_data, val, ma, vol, pull;
65 int npins, size, i, ret;
66 unsigned long config;
67
68 debug("\n%s: set state: %s\n", __func__, conf->name);
69
70 size = dev_read_size(conf, "fsl,pinmux-ids");
71 if (size < 0)
72 return size;
73
74 if (!size || size % sizeof(int)) {
75 dev_err(dev, "Invalid fsl,pinmux-ids property in %s\n",
76 conf->name);
77 return -EINVAL;
78 }
79
80 npins = size / sizeof(int);
81
82 pin_data = devm_kzalloc(dev, size, 0);
83 if (!pin_data)
84 return -ENOMEM;
85
86 ret = dev_read_u32_array(conf, "fsl,pinmux-ids", pin_data, npins);
87 if (ret) {
88 dev_err(dev, "Error reading pin data.\n");
89 devm_kfree(dev, pin_data);
90 return -EINVAL;
91 }
92
93 config = mxs_dt_node_to_map(conf);
94
95 ma = CONFIG_TO_MA(config);
96 vol = CONFIG_TO_VOL(config);
97 pull = CONFIG_TO_PULL(config);
98
99 for (i = 0; i < npins; i++) {
100 int pinid, bank, pin, shift;
101 void __iomem *reg;
102
103 val = pin_data[i];
104
105 pinid = MUXID_TO_PINID(val);
106 bank = PINID_TO_BANK(pinid);
107 pin = PINID_TO_PIN(pinid);
108
109 debug("(val: 0x%x) pin %d,", val, pinid);
110 /* Setup pinmux */
111 mxs_pinctrl_set_mux(dev, val, bank, pin);
112
113 debug(" ma: %d, vol: %d, pull: %d\n", ma, vol, pull);
114
115 /* drive */
116 reg = iomux->base + iomux->regs->drive;
117 reg += bank * 0x40 + pin / 8 * 0x10;
118
119 /* mA */
120 if (config & MA_PRESENT) {
121 shift = pin % 8 * 4;
122 mxs_pinctrl_rmwl(ma, 0x3, shift, reg);
123 }
124
125 /* vol */
126 if (config & VOL_PRESENT) {
127 shift = pin % 8 * 4 + 2;
128 if (vol)
129 writel(1 << shift, reg + SET);
130 else
131 writel(1 << shift, reg + CLR);
132 }
133
134 /* pull */
135 if (config & PULL_PRESENT) {
136 reg = iomux->base + iomux->regs->pull;
137 reg += bank * 0x10;
138 shift = pin;
139 if (pull)
140 writel(1 << shift, reg + SET);
141 else
142 writel(1 << shift, reg + CLR);
143 }
144 }
145
146 devm_kfree(dev, pin_data);
147 return 0;
148}
149
150static struct pinctrl_ops mxs_pinctrl_ops = {
151 .set_state = mxs_pinctrl_set_state,
152};
153
154static int mxs_pinctrl_probe(struct udevice *dev)
155{
156 struct mxs_pinctrl_priv *iomux = dev_get_priv(dev);
157
158 iomux->base = dev_read_addr_ptr(dev);
159 iomux->regs = (struct mxs_regs *)dev_get_driver_data(dev);
160
161 return 0;
162}
163
164static const struct mxs_regs imx23_regs = {
165 .muxsel = 0x100,
166 .drive = 0x200,
167 .pull = 0x400,
168};
169
170static const struct mxs_regs imx28_regs = {
171 .muxsel = 0x100,
172 .drive = 0x300,
173 .pull = 0x600,
174};
175
176static const struct udevice_id mxs_pinctrl_match[] = {
177 { .compatible = "fsl,imx23-pinctrl", .data = (ulong)&imx23_regs },
178 { .compatible = "fsl,imx28-pinctrl", .data = (ulong)&imx28_regs },
179 { /* sentinel */ }
180};
181
182U_BOOT_DRIVER(mxs_pinctrl) = {
183 .name = "mxs-pinctrl",
184 .id = UCLASS_PINCTRL,
185 .of_match = of_match_ptr(mxs_pinctrl_match),
186 .probe = mxs_pinctrl_probe,
187#if !CONFIG_IS_ENABLED(OF_PLATDATA)
188 .bind = dm_scan_fdt_dev,
189#endif
190 .priv_auto_alloc_size = sizeof(struct mxs_pinctrl_priv),
191 .ops = &mxs_pinctrl_ops,
192};