blob: 0235545ae47d1dd82520a35a5550628140e5f751 [file] [log] [blame]
Ron Madrid5bb907a2009-01-22 15:05:24 -08001/*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
3 * Copyright (C) Sheldon Instruments, Inc. 2008
4 *
5 * Author: Ron Madrid <info@sheldoninst.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <libfdt.h>
28#include <pci.h>
29#include <mpc83xx.h>
30#include <ns16550.h>
31#include <nand.h>
Ron Madrid3b439792010-04-28 16:04:43 -070032#include <asm/io.h>
Ron Madrid5bb907a2009-01-22 15:05:24 -080033
34DECLARE_GLOBAL_DATA_PTR;
35
36int checkboard(void)
37{
38 puts("Board: Sheldon Instruments SIMPC8313\n");
39 return 0;
40}
41
42#ifndef CONFIG_NAND_SPL
43static struct pci_region pci_regions[] = {
44 {
45 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
46 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
47 size: CONFIG_SYS_PCI1_MEM_SIZE,
48 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
49 },
50 {
51 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
52 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
53 size: CONFIG_SYS_PCI1_MMIO_SIZE,
54 flags: PCI_REGION_MEM
55 },
56 {
57 bus_start: CONFIG_SYS_PCI1_IO_BASE,
58 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
59 size: CONFIG_SYS_PCI1_IO_SIZE,
60 flags: PCI_REGION_IO
61 }
62};
63
64void pci_init_board(void)
65{
66 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
67 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
68 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
69 struct pci_region *reg[] = { pci_regions };
70 int warmboot;
71
72 /* Enable all 3 PCI_CLK_OUTPUTs. */
73 clk->occr |= 0xe0000000;
74
75 /*
76 * Configure PCI Local Access Windows
77 */
78 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
79 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
80
81 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
82 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
83
84 warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
85
86 mpc83xx_pci_init(1, reg, warmboot);
87}
88
89/*
90 * Miscellaneous late-boot configurations
91 */
92int misc_init_r(void)
93{
94 int rc = 0;
Ron Madrid3b439792010-04-28 16:04:43 -070095 immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
96 fsl_lbus_t *lbus = &immap->lbus;
97 u32 *mxmr = &lbus->mamr; /* Pointer to mamr */
98
99 /* UPM Table Configuration Code */
100 static uint UPMATable[] = {
101 /* Read Single-Beat (RSS) */
102 0x0fff0c00, 0x0fffdc00, 0x0fff0c05, 0xfffffc00,
103 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
104 /* Read Burst (RBS) */
105 0x0fff0c00, 0x0ffcdc00, 0x0ffc0c00, 0x0ffc0f0c,
106 0x0ffccf0c, 0x0ffc0f0c, 0x0ffcce0c, 0x3ffc0c05,
107 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
108 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
109 /* Write Single-Beat (WSS) */
110 0x0ffc0c00, 0x0ffcdc00, 0x0ffc0c05, 0xfffffc00,
111 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
112 /* Write Burst (WBS) */
113 0x0ffc0c00, 0x0fffcc0c, 0x0fff0c00, 0x0fffcc00,
114 0x0fff1c00, 0x0fffcf0c, 0x0fff0f0c, 0x0fffcf0c,
115 0x0fff0c0c, 0x0fffcc0c, 0x0fff0c05, 0xfffffc00,
116 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
117 /* Refresh Timer (RTS) */
118 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
119 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
120 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
121 /* Exception Condition (EXS) */
122 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
123 };
124
125 upmconfig(UPMA, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
126
127 /* Set LUPWAIT to be active low and enabled */
128 out_be32(mxmr, MxMR_UWPL | MxMR_GPL_x4DIS);
Ron Madrid5bb907a2009-01-22 15:05:24 -0800129
130 return rc;
131}
132
133#if defined(CONFIG_OF_BOARD_SETUP)
134void ft_board_setup(void *blob, bd_t *bd)
135{
136 ft_cpu_setup(blob, bd);
137#ifdef CONFIG_PCI
138 ft_pci_setup(blob, bd);
139#endif
140}
141#endif
142#else /* CONFIG_NAND_SPL */
143void board_init_f(ulong bootflag)
144{
145 NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
146 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
147 puts("NAND boot... ");
148 init_timebase();
149 initdram(0);
Mingkai Hu6e1385d2009-09-11 10:53:08 +0800150 relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
Ron Madrid5bb907a2009-01-22 15:05:24 -0800151 CONFIG_SYS_NAND_U_BOOT_RELOC);
152}
153
154void board_init_r(gd_t *gd, ulong dest_addr)
155{
156 nand_boot();
157}
158
159void putc(char c)
160{
161 if (gd->flags & GD_FLG_SILENT)
162 return;
163
164 if (c == '\n')
165 NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
166
167 NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
168}
169#endif