Prabhakar Kushwaha | 3b6e389 | 2016-06-03 18:41:35 +0530 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 2016 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <i2c.h> |
| 9 | #include <asm/io.h> |
| 10 | #include <asm/arch/clock.h> |
| 11 | #include <asm/arch/fsl_serdes.h> |
| 12 | #include <asm/arch/soc.h> |
| 13 | #include <hwconfig.h> |
| 14 | #include <ahci.h> |
| 15 | #include <mmc.h> |
| 16 | #include <scsi.h> |
| 17 | #include <fsl_csu.h> |
| 18 | #include <fsl_esdhc.h> |
| 19 | #include <environment.h> |
| 20 | #include <fsl_mmdc.h> |
| 21 | #include <netdev.h> |
| 22 | |
| 23 | DECLARE_GLOBAL_DATA_PTR; |
| 24 | |
| 25 | static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) |
| 26 | { |
| 27 | int timeout = 1000; |
| 28 | |
| 29 | out_be32(ptr, value); |
| 30 | |
| 31 | while (in_be32(ptr) & bits) { |
| 32 | udelay(100); |
| 33 | timeout--; |
| 34 | } |
| 35 | if (timeout <= 0) |
| 36 | puts("Error: wait for clear timeout.\n"); |
| 37 | } |
| 38 | |
| 39 | int checkboard(void) |
| 40 | { |
| 41 | u8 in1; |
| 42 | |
| 43 | puts("Board: LS1012ARDB "); |
| 44 | |
| 45 | /* Initialize i2c early for Serial flash bank information */ |
| 46 | i2c_set_bus_num(0); |
| 47 | |
| 48 | if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) { |
| 49 | printf("Error reading i2c boot information!\n"); |
| 50 | return 0; /* Don't want to hang() on this error */ |
| 51 | } |
| 52 | |
| 53 | puts("Version"); |
| 54 | if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A) |
| 55 | puts(": RevA"); |
| 56 | else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B) |
| 57 | puts(": RevB"); |
| 58 | else |
| 59 | puts(": unknown"); |
| 60 | |
| 61 | printf(", boot from QSPI"); |
| 62 | if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU) |
| 63 | puts(": emu\n"); |
| 64 | else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1) |
| 65 | puts(": bank1\n"); |
| 66 | else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2) |
| 67 | puts(": bank2\n"); |
| 68 | else |
| 69 | puts("unknown\n"); |
| 70 | |
| 71 | return 0; |
| 72 | } |
| 73 | |
| 74 | void mmdc_init(void) |
| 75 | { |
| 76 | struct mmdc_p_regs *mmdc = |
| 77 | (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; |
| 78 | |
| 79 | out_be32(&mmdc->mdscr, CONFIGURATION_REQ); |
| 80 | |
| 81 | /* configure timing parms */ |
| 82 | out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); |
| 83 | out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); |
| 84 | out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); |
| 85 | out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); |
| 86 | |
| 87 | /* other parms */ |
| 88 | out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); |
| 89 | out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); |
| 90 | out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); |
| 91 | out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); |
| 92 | |
| 93 | /* out of reset delays */ |
| 94 | out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); |
| 95 | |
| 96 | /* physical parms */ |
| 97 | out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); |
| 98 | out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); |
| 99 | |
| 100 | /* Enable MMDC */ |
| 101 | out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); |
| 102 | |
| 103 | /* dram init sequence: update MRs */ |
| 104 | out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ | |
| 105 | CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); |
| 106 | out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | |
| 107 | CMD_BANK_ADDR_3)); |
| 108 | out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | |
| 109 | CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); |
| 110 | out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) | |
| 111 | CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ | |
| 112 | CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0)); |
| 113 | |
| 114 | /* dram init sequence: ZQCL */ |
| 115 | out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | |
| 116 | CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); |
| 117 | set_wait_for_bits_clear(&mmdc->mpzqhwctrl, |
| 118 | CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, |
| 119 | FORCE_ZQ_AUTO_CALIBRATION); |
| 120 | |
| 121 | /* Calibrations now: wr lvl */ |
| 122 | out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) | |
| 123 | CONFIGURATION_REQ | CMD_LOAD_MODE_REG | |
| 124 | CMD_BANK_ADDR_1)); |
| 125 | out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); |
| 126 | set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); |
| 127 | |
| 128 | mdelay(1); |
| 129 | |
| 130 | out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | |
| 131 | CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); |
| 132 | out_be32(&mmdc->mdscr, CONFIGURATION_REQ); |
| 133 | |
| 134 | mdelay(1); |
| 135 | |
| 136 | /* Calibrations now: Read DQS gating calibration */ |
| 137 | out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | |
| 138 | CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); |
| 139 | out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | |
| 140 | CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); |
| 141 | out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); |
| 142 | out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); |
| 143 | set_wait_for_bits_clear(&mmdc->mpdgctrl0, |
| 144 | AUTO_RD_DQS_GATING_CALIBRATION_EN, |
| 145 | AUTO_RD_DQS_GATING_CALIBRATION_EN); |
| 146 | |
| 147 | out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | |
| 148 | CMD_BANK_ADDR_3)); |
| 149 | |
| 150 | /* Calibrations now: Read calibration */ |
| 151 | out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | |
| 152 | CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); |
| 153 | out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | |
| 154 | CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); |
| 155 | out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); |
| 156 | set_wait_for_bits_clear(&mmdc->mprddlhwctl, |
| 157 | AUTO_RD_CALIBRATION_EN, |
| 158 | AUTO_RD_CALIBRATION_EN); |
| 159 | |
| 160 | out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | |
| 161 | CMD_BANK_ADDR_3)); |
| 162 | |
| 163 | /* PD, SR */ |
| 164 | out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); |
| 165 | out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); |
| 166 | |
| 167 | /* refresh scheme */ |
| 168 | set_wait_for_bits_clear(&mmdc->mdref, |
| 169 | CONFIG_SYS_MMDC_CORE_REFRESH_CTL, |
| 170 | START_REFRESH); |
| 171 | |
| 172 | /* disable CON_REQ */ |
| 173 | out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); |
| 174 | } |
| 175 | |
| 176 | int dram_init(void) |
| 177 | { |
| 178 | mmdc_init(); |
| 179 | |
| 180 | gd->ram_size = CONFIG_SYS_SDRAM_SIZE; |
| 181 | |
| 182 | return 0; |
| 183 | } |
| 184 | |
| 185 | int board_eth_init(bd_t *bis) |
| 186 | { |
| 187 | return pci_eth_init(bis); |
| 188 | } |
| 189 | |
| 190 | int board_early_init_f(void) |
| 191 | { |
| 192 | fsl_lsch2_early_init_f(); |
| 193 | |
| 194 | return 0; |
| 195 | } |
| 196 | |
| 197 | int board_init(void) |
| 198 | { |
| 199 | struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; |
| 200 | /* |
| 201 | * Set CCI-400 control override register to enable barrier |
| 202 | * transaction |
| 203 | */ |
| 204 | out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); |
| 205 | |
| 206 | #ifdef CONFIG_ENV_IS_NOWHERE |
| 207 | gd->env_addr = (ulong)&default_environment[0]; |
| 208 | #endif |
| 209 | |
| 210 | #ifdef CONFIG_LAYERSCAPE_NS_ACCESS |
| 211 | enable_layerscape_ns_access(); |
| 212 | #endif |
| 213 | |
| 214 | return 0; |
| 215 | } |
| 216 | |
| 217 | int ft_board_setup(void *blob, bd_t *bd) |
| 218 | { |
| 219 | arch_fixup_fdt(blob); |
| 220 | |
| 221 | ft_cpu_setup(blob, bd); |
| 222 | |
| 223 | return 0; |
| 224 | } |