Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 3b804b370dd8027a6d450c447247855a149ea2ec / . / arch / arm / dts / rk3399-u-boot.dtsi
blob: 3423b882c43733654d2f74a0a58caa604424b9d8 [file] [log] [blame]
Jagan Tekie05b4a42019-03-11 13:50:03 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
4 */
Peter Robinson5532e3b2020-01-20 09:17:00 +0000[diff] [blame]5#define USB_CLASS_HUB 9
Jagan Tekie05b4a42019-03-11 13:50:03 +0530[diff] [blame]6
Simon Glassc4cea2b2020-07-19 13:55:58 -0600[diff] [blame]7#include "rockchip-u-boot.dtsi"
8
Peter Robinson5532e3b2020-01-20 09:17:00 +0000[diff] [blame]9/ {
10 aliases {
11 mmc0 = &sdhci;
12 mmc1 = &sdmmc;
Jagan Teki765a12d2020-05-09 22:26:23 +0530[diff] [blame]13 pci0 = &pcie0;
Simon Glassc4cea2b2020-07-19 13:55:58 -0600[diff] [blame]14 spi1 = &spi1;
Peter Robinson5532e3b2020-01-20 09:17:00 +0000[diff] [blame]15 };
16
17 cic: syscon@ff620000 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]18 bootph-all;
Peter Robinson5532e3b2020-01-20 09:17:00 +0000[diff] [blame]19 compatible = "rockchip,rk3399-cic", "syscon";
20 reg = <0x0 0xff620000 0x0 0x100>;
21 };
22
23 dfi: dfi@ff630000 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]24 bootph-all;
Peter Robinson5532e3b2020-01-20 09:17:00 +0000[diff] [blame]25 reg = <0x00 0xff630000 0x00 0x4000>;
26 compatible = "rockchip,rk3399-dfi";
27 rockchip,pmu = <&pmugrf>;
28 clocks = <&cru PCLK_DDR_MON>;
29 clock-names = "pclk_ddr_mon";
30 };
31
Lin Jinhan91e858d2020-03-31 17:39:57 +0800[diff] [blame]32 rng: rng@ff8b8000 {
33 compatible = "rockchip,cryptov1-rng";
34 reg = <0x0 0xff8b8000 0x0 0x1000>;
Peter Robinson5972c572020-12-16 15:48:42 +0000[diff] [blame]35 status = "okay";
Lin Jinhan91e858d2020-03-31 17:39:57 +0800[diff] [blame]36 };
37
Peter Robinson5532e3b2020-01-20 09:17:00 +0000[diff] [blame]38 dmc: dmc {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]39 bootph-all;
Peter Robinson5532e3b2020-01-20 09:17:00 +0000[diff] [blame]40 compatible = "rockchip,rk3399-dmc";
41 devfreq-events = <&dfi>;
42 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
43 clocks = <&cru SCLK_DDRCLK>;
44 clock-names = "dmc_clk";
45 reg = <0x0 0xffa80000 0x0 0x0800
46 0x0 0xffa80800 0x0 0x1800
47 0x0 0xffa82000 0x0 0x2000
48 0x0 0xffa84000 0x0 0x1000
49 0x0 0xffa88000 0x0 0x0800
50 0x0 0xffa88800 0x0 0x1800
51 0x0 0xffa8a000 0x0 0x2000
52 0x0 0xffa8c000 0x0 0x1000>;
53 };
54
55 pmusgrf: syscon@ff330000 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]56 bootph-all;
Peter Robinson5532e3b2020-01-20 09:17:00 +0000[diff] [blame]57 compatible = "rockchip,rk3399-pmusgrf", "syscon";
58 reg = <0x0 0xff330000 0x0 0xe3d4>;
59 };
60
Peter Robinsonf459e232019-11-09 20:30:05 +0000[diff] [blame]61};
62
Quentin Schulza4bb36d2022-09-02 15:10:54 +0200[diff] [blame]63#if defined(CONFIG_ROCKCHIP_SPI_IMAGE) && defined(CONFIG_HAS_ROM)
Simon Glassc4cea2b2020-07-19 13:55:58 -0600[diff] [blame]64&binman {
Simon Glass4170dd92023-01-07 14:07:17 -0700[diff] [blame]65 multiple-images;
Simon Glassc4cea2b2020-07-19 13:55:58 -0600[diff] [blame]66 rom {
67 filename = "u-boot.rom";
68 size = <0x400000>;
69 pad-byte = <0xff>;
70
71 mkimage {
72 args = "-n rk3399 -T rkspi";
73 u-boot-spl {
74 };
75 };
76 u-boot-img {
77 offset = <0x40000>;
78 };
79 u-boot {
80 offset = <0x300000>;
81 };
82 fdtmap {
83 };
84 };
85};
Simon Glass4170dd92023-01-07 14:07:17 -0700[diff] [blame]86#endif /* CONFIG_ROCKCHIP_SPI_IMAGE && CONFIG_HAS_ROM */
Simon Glassc4cea2b2020-07-19 13:55:58 -0600[diff] [blame]87
Peter Robinsonf459e232019-11-09 20:30:05 +0000[diff] [blame]88&cru {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]89 bootph-all;
Peter Robinsonf459e232019-11-09 20:30:05 +0000[diff] [blame]90};
91
Yifeng Zhaof8b36082021-11-01 12:43:47 +0800[diff] [blame]92&emmc_phy {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]93 bootph-all;
Yifeng Zhaof8b36082021-11-01 12:43:47 +0800[diff] [blame]94};
95
Peter Robinsonf459e232019-11-09 20:30:05 +0000[diff] [blame]96&grf {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]97 bootph-all;
Peter Robinsonf459e232019-11-09 20:30:05 +0000[diff] [blame]98};
99
100&pinctrl {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]101 bootph-all;
Peter Robinsonf459e232019-11-09 20:30:05 +0000[diff] [blame]102};
103
Jagan Tekiab0ce362019-07-16 17:27:34 +0530[diff] [blame]104&pmu {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]105 bootph-all;
Jagan Tekiab0ce362019-07-16 17:27:34 +0530[diff] [blame]106};
107
Peter Robinsonf459e232019-11-09 20:30:05 +0000[diff] [blame]108&pmugrf {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]109 bootph-all;
Peter Robinsonf459e232019-11-09 20:30:05 +0000[diff] [blame]110};
111
112&pmu {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]113 bootph-all;
Peter Robinsonf459e232019-11-09 20:30:05 +0000[diff] [blame]114};
115
116&pmucru {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]117 bootph-all;
Peter Robinsonf459e232019-11-09 20:30:05 +0000[diff] [blame]118};
119
Peter Robinsonf459e232019-11-09 20:30:05 +0000[diff] [blame]120&sdhci {
Jagan Teki167efc22020-04-28 15:30:17 +0530[diff] [blame]121 max-frequency = <200000000>;
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]122 bootph-all;
Jonas Karlman3b804b32023-05-06 17:41:11 +0000[diff] [blame^]123 u-boot,spl-fifo-mode;
Peter Robinsonf459e232019-11-09 20:30:05 +0000[diff] [blame]124};
125
Jagan Tekie05b4a42019-03-11 13:50:03 +0530[diff] [blame]126&sdmmc {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]127 bootph-all;
Deepak Das5c606ca2020-04-15 08:55:24 +0530[diff] [blame]128
129 /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
130 u-boot,spl-fifo-mode;
Jagan Tekie05b4a42019-03-11 13:50:03 +0530[diff] [blame]131};
Jagan Tekib5f88912019-05-07 23:51:51 +0530[diff] [blame]132
133&spi1 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]134 bootph-all;
Jagan Tekib5f88912019-05-07 23:51:51 +0530[diff] [blame]135};
Jagan Teki16b0dd42019-06-21 00:25:02 +0530[diff] [blame]136
137&uart0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]138 bootph-all;
Jagan Teki16b0dd42019-06-21 00:25:02 +0530[diff] [blame]139};
140
141&uart2 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]142 bootph-all;
Jagan Teki16b0dd42019-06-21 00:25:02 +0530[diff] [blame]143};
Peter Robinsonf459e232019-11-09 20:30:05 +0000[diff] [blame]144
145&vopb {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]146 bootph-all;
Peter Robinsonf459e232019-11-09 20:30:05 +0000[diff] [blame]147};
148
149&vopl {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]150 bootph-all;
Peter Robinsonf459e232019-11-09 20:30:05 +0000[diff] [blame]151};