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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_OCRTC 1 /* ...on a OCRTC board */
wdenkc6097192002-11-03 00:24:07 +000039
wdenkc837dcb2004-01-20 23:12:12 +000040#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
wdenkc6097192002-11-03 00:24:07 +000041
wdenkc837dcb2004-01-20 23:12:12 +000042#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
wdenkc6097192002-11-03 00:24:07 +000043
44#define CONFIG_BAUDRATE 9600
45#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
46
47#undef CONFIG_BOOTARGS
48#define CONFIG_BOOTCOMMAND "go fff00100"
49
50#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkc6097192002-11-03 00:24:07 +000052
Ben Warren96e21f82008-10-27 23:50:15 -070053#define CONFIG_PPC4xx_EMAC
wdenkc6097192002-11-03 00:24:07 +000054#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000055#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000056#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Ben Warren18cc7af2009-04-28 16:50:53 -070057#define CONFIG_NET_MULTI
wdenkc6097192002-11-03 00:24:07 +000058
Jon Loeligere18a1062007-07-08 14:21:43 -050059
60/*
Jon Loeliger659e2f62007-07-10 09:10:49 -050061 * BOOTP options
62 */
63#define CONFIG_BOOTP_BOOTFILESIZE
64#define CONFIG_BOOTP_BOOTPATH
65#define CONFIG_BOOTP_GATEWAY
66#define CONFIG_BOOTP_HOSTNAME
67
68
69/*
Jon Loeligere18a1062007-07-08 14:21:43 -050070 * Command line configuration.
71 */
72#include <config_cmd_default.h>
73
74#define CONFIG_CMD_PCI
75#define CONFIG_CMD_IRQ
76#define CONFIG_CMD_ASKENV
77#define CONFIG_CMD_ELF
78#define CONFIG_CMD_BSP
79#define CONFIG_CMD_EEPROM
80
wdenkc6097192002-11-03 00:24:07 +000081
82#define CONFIG_MAC_PARTITION
83#define CONFIG_DOS_PARTITION
84
wdenkc837dcb2004-01-20 23:12:12 +000085#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenkc6097192002-11-03 00:24:07 +000086
wdenkc837dcb2004-01-20 23:12:12 +000087#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
wdenkc6097192002-11-03 00:24:07 +000088
89/*
90 * Miscellaneous configurable options
91 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_LONGHELP /* undef to save memory */
93#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligere18a1062007-07-08 14:21:43 -050094#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000096#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000098#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
100#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
101#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000102
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenkc6097192002-11-03 00:24:07 +0000104
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
106#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000107
Stefan Roese550650d2010-09-20 16:05:31 +0200108#define CONFIG_CONS_INDEX 1 /* Use UART0 */
109#define CONFIG_SYS_NS16550
110#define CONFIG_SYS_NS16550_SERIAL
111#define CONFIG_SYS_NS16550_REG_SIZE 1
112#define CONFIG_SYS_NS16550_CLK get_serial_clock()
113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_BASE_BAUD 691200
wdenkc6097192002-11-03 00:24:07 +0000116
117/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk8bde7f72003-06-27 21:31:46 +0000119 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
120 57600, 115200, 230400, 460800, 921600 }
wdenkc6097192002-11-03 00:24:07 +0000121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
123#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenkc6097192002-11-03 00:24:07 +0000124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc6097192002-11-03 00:24:07 +0000126
127#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
128
129/*-----------------------------------------------------------------------
130 * PCI stuff
131 *-----------------------------------------------------------------------
132 */
wdenkc837dcb2004-01-20 23:12:12 +0000133#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
134#define PCI_HOST_FORCE 1 /* configure as pci host */
135#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenkc6097192002-11-03 00:24:07 +0000136
wdenkc837dcb2004-01-20 23:12:12 +0000137#define CONFIG_PCI /* include pci support */
138#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
139#define CONFIG_PCI_PNP /* do pci plug-and-play */
140 /* resource configuration */
wdenkc6097192002-11-03 00:24:07 +0000141
wdenkc837dcb2004-01-20 23:12:12 +0000142#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
wdenkc6097192002-11-03 00:24:07 +0000143
stroesea20b27a2004-12-16 18:05:42 +0000144#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/
stroesead10dd92003-02-14 11:21:23 +0000145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
147#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0410 /* PCI Device ID: OCRTC */
148#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
149#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
150#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
151#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
152#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
153#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
154#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000155
156/*-----------------------------------------------------------------------
157 * Start addresses for the final memory configuration
158 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000160 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_SDRAM_BASE 0x00000000
162#define CONFIG_SYS_FLASH_BASE 0xFFFD0000
163#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
164#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
165#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000166
167/*
168 * For booting Linux, the board info and command line data
169 * have to be in the first 8 MB of memory, since this is
170 * the maximum mapped by the Linux kernel during initialization.
171 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000173/*-----------------------------------------------------------------------
174 * FLASH organization
175 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
177#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkc6097192002-11-03 00:24:07 +0000178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
180#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000181
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
183#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
184#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenkc6097192002-11-03 00:24:07 +0000185/*
186 * The following defines are added for buggy IOP480 byte interface.
187 * All other boards should use the standard values (CPCI405 etc.)
188 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
190#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
191#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
wdenkc6097192002-11-03 00:24:07 +0000192
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenkc6097192002-11-03 00:24:07 +0000194
195#if 0 /* Use NVRAM for environment variables */
196/*-----------------------------------------------------------------------
197 * NVRAM organization
198 */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200199#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
201#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200202#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
203#define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
205#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */
wdenkc6097192002-11-03 00:24:07 +0000206
207#else /* Use EEPROM for environment variables */
208
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200209#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200210#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
211#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */
wdenk8bde7f72003-06-27 21:31:46 +0000212 /* total size of a CAT24WC08 is 1024 bytes */
wdenkc6097192002-11-03 00:24:07 +0000213#endif
214
215/*-----------------------------------------------------------------------
216 * I2C EEPROM (CAT24WC08) for environment
217 */
218#define CONFIG_HARD_I2C /* I2c with hardware support */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200219#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
221#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenkc6097192002-11-03 00:24:07 +0000222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
224#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
wdenkc837dcb2004-01-20 23:12:12 +0000225/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
227#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
wdenkc6097192002-11-03 00:24:07 +0000228 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000229 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenkc6097192002-11-03 00:24:07 +0000231
wdenkc6097192002-11-03 00:24:07 +0000232/*
233 * Init Memory Controller:
234 *
235 * BR0/1 and OR0/1 (FLASH)
236 */
237
238#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
239#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
240
241/*-----------------------------------------------------------------------
242 * External Bus Controller (EBC) Setup
243 */
244
wdenkc837dcb2004-01-20 23:12:12 +0000245/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_EBC_PB0AP 0x92015480
247#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000248
wdenkc837dcb2004-01-20 23:12:12 +0000249/* Memory Bank 1 (Flash Bank 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_EBC_PB1AP 0x92015480
251#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000252
wdenkc837dcb2004-01-20 23:12:12 +0000253/* Memory Bank 2 (PLD - FPGA-boot) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
wdenk8bde7f72003-06-27 21:31:46 +0000255 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000257
wdenkc837dcb2004-01-20 23:12:12 +0000258/* Memory Bank 3 (PLD - OSL) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
wdenk8bde7f72003-06-27 21:31:46 +0000260 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000262
wdenkc837dcb2004-01-20 23:12:12 +0000263/* Memory Bank 4 (Spartan2 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
wdenk8bde7f72003-06-27 21:31:46 +0000265 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
wdenkc6097192002-11-03 00:24:07 +0000267
wdenkc837dcb2004-01-20 23:12:12 +0000268/* Memory Bank 5 (Spartan2 2) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
wdenk8bde7f72003-06-27 21:31:46 +0000270 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
wdenkc6097192002-11-03 00:24:07 +0000272
wdenkc837dcb2004-01-20 23:12:12 +0000273/* Memory Bank 6 (Virtex 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
wdenk8bde7f72003-06-27 21:31:46 +0000275 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
wdenkc6097192002-11-03 00:24:07 +0000277
wdenkc837dcb2004-01-20 23:12:12 +0000278/* Memory Bank 7 (Virtex 2) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
wdenk8bde7f72003-06-27 21:31:46 +0000280 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
wdenkc6097192002-11-03 00:24:07 +0000282
283
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
wdenkc6097192002-11-03 00:24:07 +0000285
286/*-----------------------------------------------------------------------
287 * Definitions for initial stack pointer and data area (in DPRAM)
288 */
289
290/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_TEMP_STACK_OCM 1
wdenkc6097192002-11-03 00:24:07 +0000292
293/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
295#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
wdenkc6097192002-11-03 00:24:07 +0000296
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
298#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
299#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
300#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
301#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000302
303
304/*
305 * Internal Definitions
306 *
307 * Boot Flags
308 */
309#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
310#define BOOTFLAG_WARM 0x02 /* Software reboot */
311
312#endif /* __CONFIG_H */