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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 3b8dfc42a239cbb1561e7ecbc116b69fb6913355 / . / configs / chromebook_speedy_defconfig
blob: d5aaee9dde176c85cb670e524b3ce57afce9695e [file] [log] [blame]
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]1CONFIG_ARM=y
Tom Rinia2ac2b92021-08-27 21:18:30 -0400[diff] [blame]2CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
Tom Rinif76750d2021-12-11 14:55:51 -0500[diff] [blame]3CONFIG_SYS_ARCH_TIMER=y
Urja Rannikko7ba79f22019-05-13 13:51:05 +0000[diff] [blame]4# CONFIG_SPL_USE_ARCH_MEMCPY is not set
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]5CONFIG_ARCH_ROCKCHIP=y
Simon Glass98463902022-10-20 18:22:39 -0600[diff] [blame]6CONFIG_TEXT_BASE=0x00100000
Tom Rini554e5512020-08-10 15:31:07 -0400[diff] [blame]7CONFIG_NR_DRAM_BANKS=1
Tom Rini2bba7802021-06-28 10:17:29 -0400[diff] [blame]8CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy"
Tom Rinic5a6e9f2020-07-06 13:54:25 -0400[diff] [blame]9CONFIG_SPL_TEXT_BASE=0xff704000
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]10CONFIG_ROCKCHIP_RK3288=y
Simon Glass103c5f12021-08-08 12:20:09 -0600[diff] [blame]11# CONFIG_SPL_MMC is not set
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]12CONFIG_TARGET_CHROMEBOOK_SPEEDY=y
Tom Rinid168bcb2019-04-29 15:54:04 -0400[diff] [blame]13CONFIG_SPL_STACK_R_ADDR=0x80000
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]14CONFIG_DEBUG_UART_BASE=0xff690000
15CONFIG_DEBUG_UART_CLOCK=24000000
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]16CONFIG_SPL_SPI_FLASH_SUPPORT=y
Simon Glassea2ca7e2021-08-08 12:20:14 -0600[diff] [blame]17CONFIG_SPL_SPI=y
Tom Rinid46e86d2022-04-08 13:36:51 -0400[diff] [blame]18CONFIG_SYS_LOAD_ADDR=0x800800
Tom Rini556fd592020-04-28 16:15:47 -0400[diff] [blame]19CONFIG_SPL_PAYLOAD="u-boot.img"
Tom Rinif7d0ae92020-07-28 08:46:52 -0400[diff] [blame]20CONFIG_DEBUG_UART=y
Tom Rinieaf6ea62022-05-25 12:16:03 -0400[diff] [blame]21CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
22CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
Tom Rini08574ed2022-10-28 20:27:07 -0400[diff] [blame]23CONFIG_SYS_MONITOR_LEN=614400
Simon Glass37304aa2019-07-20 20:51:14 -0600[diff] [blame]24CONFIG_USE_PREBOOT=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]25CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
Tom Rini0817daa2020-10-09 12:22:06 -0400[diff] [blame]26CONFIG_SILENT_CONSOLE=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]27# CONFIG_DISPLAY_CPUINFO is not set
28CONFIG_DISPLAY_BOARDINFO_LATE=y
Urja Rannikkofffdf722020-05-13 19:15:21 +0000[diff] [blame]29CONFIG_BOARD_EARLY_INIT_R=y
Tom Rinica8a3292022-05-16 17:20:26 -0400[diff] [blame]30CONFIG_SPL_PAD_TO=0x7f8000
Tom Rini9b5f9ae2022-05-19 15:09:22 -0400[diff] [blame]31CONFIG_SPL_NO_BSS_LIMIT=y
Urja Rannikko7ba79f22019-05-13 13:51:05 +0000[diff] [blame]32# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Tom Rinif113d7d2022-05-26 13:13:21 -0400[diff] [blame]33# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
34CONFIG_SPL_STACK=0xff718000
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]35CONFIG_SPL_STACK_R=y
36CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Urja Rannikko7ba79f22019-05-13 13:51:05 +0000[diff] [blame]37# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
Simon Glass1e52db62021-07-14 17:05:32 -0500[diff] [blame]38# CONFIG_SPL_CRC32 is not set
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]39CONFIG_SPL_SPI_LOAD=y
Tom Rini3e5b62f2021-08-10 15:08:46 -0400[diff] [blame]40CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
Tom Rinic45568c2022-06-25 19:29:46 -0400[diff] [blame]41CONFIG_SYS_BOOTM_LEN=0x4000000
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]42CONFIG_CMD_GPIO=y
43CONFIG_CMD_GPT=y
44CONFIG_CMD_I2C=y
45CONFIG_CMD_MMC=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]46CONFIG_CMD_SF_TEST=y
47CONFIG_CMD_SPI=y
48CONFIG_CMD_USB=y
49# CONFIG_CMD_SETEXPR is not set
50CONFIG_CMD_CACHE=y
51CONFIG_CMD_TIME=y
52CONFIG_CMD_PMIC=y
53CONFIG_CMD_REGULATOR=y
54# CONFIG_SPL_DOS_PARTITION is not set
55# CONFIG_SPL_EFI_PARTITION is not set
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]56CONFIG_SPL_OF_CONTROL=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]57CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
58CONFIG_SPL_OF_PLATDATA=y
Tom Rini8d8ee472019-11-12 22:46:36 -0500[diff] [blame]59CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]60CONFIG_REGMAP=y
61CONFIG_SPL_REGMAP=y
62CONFIG_SYSCON=y
63CONFIG_SPL_SYSCON=y
64# CONFIG_SPL_SIMPLE_BUS is not set
Urja Rannikko7ba79f22019-05-13 13:51:05 +0000[diff] [blame]65# CONFIG_SPL_BLK is not set
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]66CONFIG_CLK=y
67CONFIG_SPL_CLK=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]68CONFIG_ROCKCHIP_GPIO=y
69CONFIG_I2C_CROS_EC_TUNNEL=y
70CONFIG_SYS_I2C_ROCKCHIP=y
71CONFIG_I2C_MUX=y
72CONFIG_DM_KEYBOARD=y
73CONFIG_CROS_EC_KEYB=y
74CONFIG_CROS_EC=y
75CONFIG_CROS_EC_SPI=y
76CONFIG_PWRSEQ=y
Jaehoon Chung144d0572021-02-16 10:16:56 +0900[diff] [blame]77CONFIG_MMC_PWRSEQ=y
Urja Rannikko7ba79f22019-05-13 13:51:05 +0000[diff] [blame]78# CONFIG_SPL_DM_MMC is not set
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]79CONFIG_MMC_DW=y
80CONFIG_MMC_DW_ROCKCHIP=y
Miquel Raynal888f1842019-10-03 19:50:05 +0200[diff] [blame]81CONFIG_MTD=y
Urja Rannikko7ba79f22019-05-13 13:51:05 +0000[diff] [blame]82CONFIG_SF_DEFAULT_BUS=2
Patrick Delaunay14453fb2019-02-27 15:20:36 +0100[diff] [blame]83CONFIG_SF_DEFAULT_SPEED=20000000
Urja Rannikko64df5122019-05-13 13:51:03 +0000[diff] [blame]84CONFIG_SPI_FLASH_GIGADEVICE=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]85CONFIG_PINCTRL=y
Urja Rannikko7ba79f22019-05-13 13:51:05 +0000[diff] [blame]86CONFIG_PINCONF=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]87CONFIG_SPL_PINCTRL=y
Urja Rannikko5e50f872020-05-13 19:15:23 +0000[diff] [blame]88# CONFIG_SPL_PINCTRL_FULL is not set
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]89CONFIG_DM_PMIC=y
90# CONFIG_SPL_PMIC_CHILDREN is not set
91CONFIG_PMIC_RK8XX=y
92CONFIG_DM_REGULATOR_FIXED=y
93CONFIG_REGULATOR_RK8XX=y
94CONFIG_PWM_ROCKCHIP=y
95CONFIG_RAM=y
96CONFIG_SPL_RAM=y
97CONFIG_DEBUG_UART_SHIFT=2
Tom Rini9591b632022-12-04 09:39:03 -0500[diff] [blame]98CONFIG_SYS_NS16550_MEM32=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]99CONFIG_ROCKCHIP_SERIAL=y
100CONFIG_ROCKCHIP_SPI=y
101CONFIG_SYSRESET=y
102CONFIG_USB=y
Urja Rannikko7ba79f22019-05-13 13:51:05 +0000[diff] [blame]103# CONFIG_SPL_DM_USB is not set
104CONFIG_USB_DWC2=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]105CONFIG_ROCKCHIP_USB2_PHY=y
Simon Glassb86986c2022-10-18 07:46:31 -0600[diff] [blame]106CONFIG_VIDEO=y
Anatolij Gustschin8a6ffed2020-02-04 22:43:06 +0100[diff] [blame]107# CONFIG_VIDEO_BPP8 is not set
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]108CONFIG_CONSOLE_TRUETYPE=y
109CONFIG_DISPLAY=y
110CONFIG_VIDEO_ROCKCHIP=y
111CONFIG_DISPLAY_ROCKCHIP_EDP=y
112CONFIG_DISPLAY_ROCKCHIP_HDMI=y
113# CONFIG_USE_PRIVATE_LIBGCC is not set
Urja Rannikko7ba79f22019-05-13 13:51:05 +0000[diff] [blame]114CONFIG_SPL_TINY_MEMSET=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]115CONFIG_CMD_DHRYSTONE=y
116CONFIG_ERRNO_STR=y