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Wolfgang Denk6cb142f2006-03-12 02:12:27 +01001/*
2 * U-boot - cpu.c CPU specific functions
3 *
Aubrey Li155fd762007-04-05 18:31:18 +08004 * Copyright (c) 2005-2007 Analog Devices Inc.
Wolfgang Denk6cb142f2006-03-12 02:12:27 +01005 *
6 * (C) Copyright 2000-2004
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
Aubrey Li155fd762007-04-05 18:31:18 +080024 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
25 * MA 02110-1301 USA
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010026 */
27
28#include <common.h>
29#include <asm/blackfin.h>
30#include <command.h>
31#include <asm/entry.h>
Aubrey.Li3f0606a2007-03-09 13:38:44 +080032#include <asm/cplb.h>
Aubrey Li8440bb12007-03-12 00:25:14 +080033#include <asm/io.h>
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010034
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010035#define CACHE_ON 1
36#define CACHE_OFF 0
37
Aubrey.Li3f0606a2007-03-09 13:38:44 +080038extern unsigned int icplb_table[page_descriptor_table_size][2];
39extern unsigned int dcplb_table[page_descriptor_table_size][2];
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010040
Aubrey.Li3f0606a2007-03-09 13:38:44 +080041int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
42{
43 __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM)
44 );
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010045
46 return 0;
47}
48
49/* These functions are just used to satisfy the linker */
50int cpu_init(void)
51{
52 return 0;
53}
54
55int cleanup_before_linux(void)
56{
57 return 0;
58}
59
60void icache_enable(void)
61{
Aubrey.Li3f0606a2007-03-09 13:38:44 +080062 unsigned int *I0, *I1;
63 int i, j = 0;
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010064
Aubrey.Li3f0606a2007-03-09 13:38:44 +080065 /* Before enable icache, disable it first */
66 icache_disable();
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010067 I0 = (unsigned int *)ICPLB_ADDR0;
68 I1 = (unsigned int *)ICPLB_DATA0;
Wolfgang Denk8e7b7032006-03-12 02:55:22 +010069
Aubrey.Li3f0606a2007-03-09 13:38:44 +080070 /* make sure the locked ones go in first */
71 for (i = 0; i < page_descriptor_table_size; i++) {
72 if (CPLB_LOCK & icplb_table[i][1]) {
Aubrey Li8440bb12007-03-12 00:25:14 +080073 debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
Aubrey.Li3f0606a2007-03-09 13:38:44 +080074 icplb_table[i][0], icplb_table[i][1]);
75 *I0++ = icplb_table[i][0];
76 *I1++ = icplb_table[i][1];
77 j++;
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010078 }
Aubrey.Li3f0606a2007-03-09 13:38:44 +080079 }
80
81 for (i = 0; i < page_descriptor_table_size; i++) {
82 if (!(CPLB_LOCK & icplb_table[i][1])) {
Aubrey Li8440bb12007-03-12 00:25:14 +080083 debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
Aubrey.Li3f0606a2007-03-09 13:38:44 +080084 icplb_table[i][0], icplb_table[i][1]);
85 *I0++ = icplb_table[i][0];
86 *I1++ = icplb_table[i][1];
87 j++;
88 if (j == 16) {
89 break;
90 }
91 }
92 }
93
94 /* Fill the rest with invalid entry */
95 if (j <= 15) {
Aubrey Li7b7e30a2007-04-05 18:33:04 +080096 for (; j < 16; j++) {
Aubrey Li8440bb12007-03-12 00:25:14 +080097 debug("filling %i with 0", j);
Aubrey.Li3f0606a2007-03-09 13:38:44 +080098 *I1++ = 0x0;
99 }
100
101 }
102
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100103 cli();
Aubrey Li8440bb12007-03-12 00:25:14 +0800104 sync();
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800105 asm(" .align 8; ");
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100106 *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
Aubrey Li8440bb12007-03-12 00:25:14 +0800107 sync();
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100108 sti();
109}
110
111void icache_disable(void)
112{
113 cli();
Aubrey Li8440bb12007-03-12 00:25:14 +0800114 sync();
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800115 asm(" .align 8; ");
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100116 *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
Aubrey Li8440bb12007-03-12 00:25:14 +0800117 sync();
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100118 sti();
119}
120
121int icache_status(void)
122{
123 unsigned int value;
124 value = *(unsigned int *)IMEM_CONTROL;
125
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800126 if (value & (IMC | ENICPLB))
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100127 return CACHE_ON;
128 else
129 return CACHE_OFF;
130}
131
132void dcache_enable(void)
133{
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800134 unsigned int *I0, *I1;
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100135 unsigned int temp;
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800136 int i, j = 0;
137
138 /* Before enable dcache, disable it first */
139 dcache_disable();
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100140 I0 = (unsigned int *)DCPLB_ADDR0;
141 I1 = (unsigned int *)DCPLB_DATA0;
142
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800143 /* make sure the locked ones go in first */
144 for (i = 0; i < page_descriptor_table_size; i++) {
145 if (CPLB_LOCK & dcplb_table[i][1]) {
Aubrey Li8440bb12007-03-12 00:25:14 +0800146 debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800147 dcplb_table[i][0], dcplb_table[i][1]);
148 *I0++ = dcplb_table[i][0];
149 *I1++ = dcplb_table[i][1];
150 j++;
151 } else {
Aubrey Li8440bb12007-03-12 00:25:14 +0800152 debug("skip %02i %02i 0x%08x 0x%08x\n", i, j,
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800153 dcplb_table[i][0], dcplb_table[i][1]);
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100154 }
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800155 }
156
157 for (i = 0; i < page_descriptor_table_size; i++) {
158 if (!(CPLB_LOCK & dcplb_table[i][1])) {
Aubrey Li8440bb12007-03-12 00:25:14 +0800159 debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800160 dcplb_table[i][0], dcplb_table[i][1]);
161 *I0++ = dcplb_table[i][0];
162 *I1++ = dcplb_table[i][1];
163 j++;
164 if (j == 16) {
165 break;
166 }
167 }
168 }
169
170 /* Fill the rest with invalid entry */
171 if (j <= 15) {
Aubrey Li7b7e30a2007-04-05 18:33:04 +0800172 for (; j < 16; j++) {
Aubrey Li8440bb12007-03-12 00:25:14 +0800173 debug("filling %i with 0", j);
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800174 *I1++ = 0x0;
175 }
176 }
177
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100178 cli();
Wolfgang Denk8e7b7032006-03-12 02:55:22 +0100179 temp = *(unsigned int *)DMEM_CONTROL;
Aubrey Li8440bb12007-03-12 00:25:14 +0800180 sync();
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800181 asm(" .align 8; ");
182 *(unsigned int *)DMEM_CONTROL =
183 ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
Aubrey Li8440bb12007-03-12 00:25:14 +0800184 sync();
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100185 sti();
186}
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100187
188void dcache_disable(void)
189{
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800190 unsigned int *I0, *I1;
191 int i;
192
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100193 cli();
Aubrey Li8440bb12007-03-12 00:25:14 +0800194 sync();
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800195 asm(" .align 8; ");
196 *(unsigned int *)DMEM_CONTROL &=
197 ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
Aubrey Li8440bb12007-03-12 00:25:14 +0800198 sync();
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100199 sti();
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800200
201 /* after disable dcache,
202 * clear it so we don't confuse the next application
203 */
204 I0 = (unsigned int *)DCPLB_ADDR0;
205 I1 = (unsigned int *)DCPLB_DATA0;
206
207 for (i = 0; i < 16; i++) {
208 *I0++ = 0x0;
209 *I1++ = 0x0;
210 }
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100211}
212
213int dcache_status(void)
214{
215 unsigned int value;
216 value = *(unsigned int *)DMEM_CONTROL;
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800217 if (value & (ENDCPLB))
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100218 return CACHE_ON;
219 else
220 return CACHE_OFF;
221}