blob: 04d97cd1dcdd406600605559bdae5ba9a6fd3c64 [file] [log] [blame]
Andre Schwarzc005b932008-06-10 09:13:16 +02001/*
2 * Copyright (C) Matrix Vision GmbH 2008
3 *
4 * Matrix Vision mvBlueLYNX-M7 configuration file
5 * based on Freescale's MPC8349ITX.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
Andre Schwarz5ed546f2008-07-02 18:54:08 +020030#include <version.h>
Andre Schwarzc005b932008-06-10 09:13:16 +020031
32/*
33 * High Level Configuration Options
34 */
35#define CONFIG_E300 1
Peter Tyser0f898602009-05-22 17:23:24 -050036#define CONFIG_MPC83xx 1
Peter Tyser2c7920a2009-05-22 17:23:25 -050037#define CONFIG_MPC834x 1
Andre Schwarzc005b932008-06-10 09:13:16 +020038#define CONFIG_MPC8343 1
39
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040#define CONFIG_SYS_TEXT_BASE 0xFFF00000
41
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_IMMR 0xE0000000
Andre Schwarzc005b932008-06-10 09:13:16 +020043
44#define CONFIG_PCI
Andre Schwarzc005b932008-06-10 09:13:16 +020045#define CONFIG_PCI_SKIP_HOST_BRIDGE
46#define CONFIG_HARD_I2C
47#define CONFIG_TSEC_ENET
48#define CONFIG_MPC8XXX_SPI
49#define CONFIG_HARD_SPI
50#define MVBLM7_MMC_CS 0x04000000
André Schwarz28887d82009-08-27 14:48:35 +020051#define CONFIG_MISC_INIT_R
Andre Schwarzc005b932008-06-10 09:13:16 +020052
53/* I2C */
Andre Schwarzc005b932008-06-10 09:13:16 +020054#define CONFIG_FSL_I2C
55#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_I2C_OFFSET 0x3000
57#define CONFIG_SYS_I2C2_OFFSET 0x3100
Andre Schwarzc005b932008-06-10 09:13:16 +020058
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_I2C_SPEED 100000
60#define CONFIG_SYS_I2C_SLAVE 0x7F
Andre Schwarzc005b932008-06-10 09:13:16 +020061
62/*
63 * DDR Setup
64 */
André Schwarz28887d82009-08-27 14:48:35 +020065#undef CONFIG_SPD_EEPROM
66
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_DDR_BASE 0x00000000
68#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
69#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
70#define CONFIG_SYS_83XX_DDR_USES_CS0 1
71#define CONFIG_SYS_MEMTEST_START (60<<20)
72#define CONFIG_SYS_MEMTEST_END (70<<20)
André Schwarz28887d82009-08-27 14:48:35 +020073#define CONFIG_VERY_BIG_RAM
Andre Schwarzc005b932008-06-10 09:13:16 +020074
André Schwarz28887d82009-08-27 14:48:35 +020075#define CONFIG_SYS_DDRCDR 0x22000001
76#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
Andre Schwarzc005b932008-06-10 09:13:16 +020077
André Schwarz28887d82009-08-27 14:48:35 +020078#define CONFIG_SYS_DDR_SIZE 512
Andre Schwarzc005b932008-06-10 09:13:16 +020079
André Schwarz28887d82009-08-27 14:48:35 +020080#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
Andre Schwarzc005b932008-06-10 09:13:16 +020081
André Schwarz28887d82009-08-27 14:48:35 +020082#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
Andre Schwarzc005b932008-06-10 09:13:16 +020083
André Schwarz28887d82009-08-27 14:48:35 +020084#define CONFIG_SYS_DDR_TIMING_0 0x00260802
85#define CONFIG_SYS_DDR_TIMING_1 0x3837c322
86#define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6
87#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Andre Schwarzc005b932008-06-10 09:13:16 +020088
André Schwarz28887d82009-08-27 14:48:35 +020089#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
André Schwarz28887d82009-08-27 14:48:35 +020091#define CONFIG_SYS_DDR_INTERVAL 0x02000100
Andre Schwarzc005b932008-06-10 09:13:16 +020092
André Schwarz28887d82009-08-27 14:48:35 +020093#define CONFIG_SYS_DDR_MODE 0x04040242
94#define CONFIG_SYS_DDR_MODE2 0x00800000
Andre Schwarzc005b932008-06-10 09:13:16 +020095
96/* Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020098#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Andre Schwarzc005b932008-06-10 09:13:16 +0200100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_FLASH_BASE 0xFF800000
102#define CONFIG_SYS_FLASH_SIZE 8
103#define CONFIG_SYS_FLASH_SIZE_SHIFT 3
104#define CONFIG_SYS_FLASH_EMPTY_INFO
105#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
106#define CONFIG_SYS_FLASH_WRITE_TOUT 500
107#define CONFIG_SYS_MAX_FLASH_BANKS 1
108#define CONFIG_SYS_MAX_FLASH_SECT 256
Andre Schwarzc005b932008-06-10 09:13:16 +0200109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
111#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
Kim Phillips2329fe12008-06-10 13:25:24 -0500112 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\
Andre Schwarzc005b932008-06-10 09:13:16 +0200113 OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \
114 OR_GPCM_EAD)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
116#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
Andre Schwarzc005b932008-06-10 09:13:16 +0200117
118/*
119 * U-Boot memory configuration
120 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200121#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#undef CONFIG_SYS_RAMBOOT
Andre Schwarzc005b932008-06-10 09:13:16 +0200123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_INIT_RAM_LOCK
125#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
126#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
Andre Schwarzc005b932008-06-10 09:13:16 +0200127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
129#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
130#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Andre Schwarzc005b932008-06-10 09:13:16 +0200131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
133#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
134#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
Andre Schwarzc005b932008-06-10 09:13:16 +0200135
136/*
137 * Local Bus LCRR and LBCR regs
138 * LCRR: DLL bypass, Clock divider is 4
139 * External Local Bus rate is
140 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
141 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500142#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
143#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_LBC_LBCR 0x00000000
Andre Schwarzc005b932008-06-10 09:13:16 +0200145
146/* LB sdram refresh timer, about 6us */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_LBC_LSRT 0x32000000
Andre Schwarzc005b932008-06-10 09:13:16 +0200148/* LB refresh timer prescal, 266MHz/32*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_LBC_MRTPR 0x20000000
Andre Schwarzc005b932008-06-10 09:13:16 +0200150
151/*
152 * Serial Port
153 */
154#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_NS16550
156#define CONFIG_SYS_NS16550_SERIAL
157#define CONFIG_SYS_NS16550_REG_SIZE 1
158#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Andre Schwarzc005b932008-06-10 09:13:16 +0200159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_BAUDRATE_TABLE \
Andre Schwarzc005b932008-06-10 09:13:16 +0200161 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
162
163#define CONFIG_CONSOLE ttyS0
164#define CONFIG_BAUDRATE 115200
165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
167#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
Andre Schwarzc005b932008-06-10 09:13:16 +0200168
169/* pass open firmware flat tree */
170#define CONFIG_OF_LIBFDT 1
171#define CONFIG_OF_BOARD_SETUP 1
172#define CONFIG_OF_STDOUT_VIA_ALIAS 1
173#define MV_DTB_NAME "mvblm7.dtb"
174
175/*
176 * PCI
177 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
179#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
180#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
181#define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
182#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
183#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
184#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
185#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
186#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
Andre Schwarzc005b932008-06-10 09:13:16 +0200187
Andre Schwarzc005b932008-06-10 09:13:16 +0200188#define CONFIG_NET_MULTI 1
189#define CONFIG_NET_RETRY_COUNT 3
190
Wolfgang Denk2ae18242010-10-06 09:05:45 +0200191#define CONFIG_PCI_66M
Andre Schwarzc005b932008-06-10 09:13:16 +0200192#define CONFIG_83XX_CLKIN 66666667
193#define CONFIG_PCI_PNP
194#define CONFIG_PCI_SCAN_SHOW
195
196/* TSEC */
197#define CONFIG_GMII
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_VSC8601_SKEWFIX
199#define CONFIG_SYS_VSC8601_SKEW_TX 3
200#define CONFIG_SYS_VSC8601_SKEW_RX 3
Andre Schwarzc005b932008-06-10 09:13:16 +0200201
202#define CONFIG_TSEC1
203#define CONFIG_TSEC2
204
205#define CONFIG_HAS_ETH0
206#define CONFIG_TSEC1_NAME "TSEC0"
207#define CONFIG_FEC1_PHY_NORXERR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_TSEC1_OFFSET 0x24000
209#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
Andre Schwarzc005b932008-06-10 09:13:16 +0200210#define TSEC1_PHY_ADDR 0x10
211#define TSEC1_PHYIDX 0
212#define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
213
214#define CONFIG_HAS_ETH1
215#define CONFIG_TSEC2_NAME "TSEC1"
216#define CONFIG_FEC2_PHY_NORXERR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_TSEC2_OFFSET 0x25000
218#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Andre Schwarzc005b932008-06-10 09:13:16 +0200219#define TSEC2_PHY_ADDR 0x11
220#define TSEC2_PHYIDX 0
221#define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
222
223#define CONFIG_ETHPRIME "TSEC0"
224
225#define CONFIG_BOOTP_VENDOREX
226#define CONFIG_BOOTP_SUBNETMASK
227#define CONFIG_BOOTP_GATEWAY
228#define CONFIG_BOOTP_DNS
229#define CONFIG_BOOTP_DNS2
230#define CONFIG_BOOTP_HOSTNAME
231#define CONFIG_BOOTP_BOOTFILESIZE
232#define CONFIG_BOOTP_BOOTPATH
233#define CONFIG_BOOTP_NTPSERVER
234#define CONFIG_BOOTP_RANDOM_DELAY
235#define CONFIG_BOOTP_SEND_HOSTNAME
236
237/* USB */
Andre Schwarzfd194f82010-05-03 13:22:31 +0200238#define CONFIG_SYS_USB_HOST
239#define CONFIG_USB_EHCI
240#define CONFIG_USB_EHCI_FSL
Andre Schwarzc005b932008-06-10 09:13:16 +0200241#define CONFIG_HAS_FSL_DR_USB
Andre Schwarzfd194f82010-05-03 13:22:31 +0200242#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Andre Schwarzc005b932008-06-10 09:13:16 +0200243
244/*
245 * Environment
246 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#undef CONFIG_SYS_FLASH_PROTECTION
Andre Schwarzc005b932008-06-10 09:13:16 +0200248#define CONFIG_ENV_OVERWRITE
249
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200250#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200251#define CONFIG_ENV_ADDR 0xFF800000
252#define CONFIG_ENV_SIZE 0x2000
253#define CONFIG_ENV_SECT_SIZE 0x2000
254#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
255#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
Andre Schwarzc005b932008-06-10 09:13:16 +0200256
Wolfgang Denke093a242008-06-28 23:34:37 +0200257#define CONFIG_LOADS_ECHO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_LOADS_BAUD_CHANGE
Andre Schwarzc005b932008-06-10 09:13:16 +0200259
260/*
261 * Command line configuration.
262 */
263#include <config_cmd_default.h>
264
265#define CONFIG_CMD_CACHE
266#define CONFIG_CMD_IRQ
267#define CONFIG_CMD_NET
268#define CONFIG_CMD_MII
269#define CONFIG_CMD_PING
270#define CONFIG_CMD_DHCP
271#define CONFIG_CMD_SDRAM
272#define CONFIG_CMD_PCI
273#define CONFIG_CMD_I2C
274#define CONFIG_CMD_FPGA
Andre Schwarzfd194f82010-05-03 13:22:31 +0200275#define CONFIG_CMD_USB
276#define CONFIG_DOS_PARTITION
Andre Schwarzc005b932008-06-10 09:13:16 +0200277
278#undef CONFIG_WATCHDOG
279
280/*
281 * Miscellaneous configurable options
282 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_LONGHELP
Andre Schwarzc005b932008-06-10 09:13:16 +0200284#define CONFIG_CMDLINE_EDITING
Kim Phillipsa059e902010-04-15 17:36:05 -0500285#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_HUSH_PARSER
287#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Andre Schwarzc005b932008-06-10 09:13:16 +0200288
289/* default load address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_LOAD_ADDR 0x2000000
Andre Schwarzc005b932008-06-10 09:13:16 +0200291/* default location for tftp and bootm */
292#define CONFIG_LOADADDR 0x200000
293
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_PROMPT "mvBL-M7> "
295#define CONFIG_SYS_CBSIZE 256
Andre Schwarzc005b932008-06-10 09:13:16 +0200296
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
298#define CONFIG_SYS_MAXARGS 16
299#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
300#define CONFIG_SYS_HZ 1000
Andre Schwarzc005b932008-06-10 09:13:16 +0200301
302/*
303 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700304 * have to be in the first 256 MB of memory, since this is
Andre Schwarzc005b932008-06-10 09:13:16 +0200305 * the maximum mapped by the Linux kernel during initialization.
306 */
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700307#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
Andre Schwarzc005b932008-06-10 09:13:16 +0200308
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_HRCW_LOW 0x0
310#define CONFIG_SYS_HRCW_HIGH 0x0
Andre Schwarzc005b932008-06-10 09:13:16 +0200311
312/*
313 * System performance
314 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
316#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
317#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
318#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
Andre Schwarzc005b932008-06-10 09:13:16 +0200319
320/* clocking */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_SCCR_ENCCM 0
322#define CONFIG_SYS_SCCR_USBMPHCM 0
323#define CONFIG_SYS_SCCR_USBDRCM 2
324#define CONFIG_SYS_SCCR_TSEC1CM 1
325#define CONFIG_SYS_SCCR_TSEC2CM 1
Andre Schwarzc005b932008-06-10 09:13:16 +0200326
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_SICRH 0x1fff8003
328#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
Andre Schwarzc005b932008-06-10 09:13:16 +0200329
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_HID0_INIT 0x000000000
Kim Phillips1a2e2032010-04-20 19:37:54 -0500331#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
332 HID0_ENABLE_INSTRUCTION_CACHE)
Andre Schwarzc005b932008-06-10 09:13:16 +0200333
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_HID2 HID2_HBE
Andre Schwarz5ed546f2008-07-02 18:54:08 +0200335#define CONFIG_HIGH_BATS 1
Andre Schwarzc005b932008-06-10 09:13:16 +0200336
337/* DDR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
339#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Andre Schwarzc005b932008-06-10 09:13:16 +0200340
341/* PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
343#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
344#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
Andre Schwarzc005b932008-06-10 09:13:16 +0200345 BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Andre Schwarzc005b932008-06-10 09:13:16 +0200347
348/* no PCI2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_IBAT3L 0
350#define CONFIG_SYS_IBAT3U 0
351#define CONFIG_SYS_IBAT4L 0
352#define CONFIG_SYS_IBAT4U 0
Andre Schwarzc005b932008-06-10 09:13:16 +0200353
354/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \
Andre Schwarzc005b932008-06-10 09:13:16 +0200356 BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
Andre Schwarzc005b932008-06-10 09:13:16 +0200358
359/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
Scott Woodc1230982009-03-31 17:49:36 -0500360#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
361 BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
363#define CONFIG_SYS_IBAT7L 0
364#define CONFIG_SYS_IBAT7U 0
Andre Schwarzc005b932008-06-10 09:13:16 +0200365
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
367#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
368#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
369#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
370#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
371#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
372#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
373#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
374#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
375#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
376#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
377#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
378#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
379#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
380#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
381#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Andre Schwarzc005b932008-06-10 09:13:16 +0200382
383/*
Andre Schwarzc005b932008-06-10 09:13:16 +0200384 * Environment Configuration
385 */
386#define CONFIG_ENV_OVERWRITE
387
388#define CONFIG_NETDEV eth0
389
390/* Default path and filenames */
391#define CONFIG_BOOTDELAY 5
392#define CONFIG_AUTOBOOT_KEYED
393#define CONFIG_AUTOBOOT_STOP_STR "s"
394#define CONFIG_ZERO_BOOTDELAY_CHECK
395#define CONFIG_RESET_TO_RETRY 1000
396
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200397#define MV_CI mvBL-M7
398#define MV_VCI mvBL-M7
André Schwarz28887d82009-08-27 14:48:35 +0200399#define MV_FPGA_DATA 0xfff40000
400#define MV_FPGA_SIZE 0
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200401#define MV_KERNEL_ADDR 0xff810000
402#define MV_INITRD_ADDR 0xffb00000
Peter Tyser3202d332009-09-16 21:38:10 -0500403#define MV_SCRIPT_ADDR 0xff804000
404#define MV_SCRIPT_ADDR2 0xff806000
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200405#define MV_DTB_ADDR 0xff808000
406#define MV_INITRD_LENGTH 0x00400000
Andre Schwarzc005b932008-06-10 09:13:16 +0200407
408#define CONFIG_SHOW_BOOT_PROGRESS 1
409
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200410#define MV_KERNEL_ADDR_RAM 0x00100000
411#define MV_DTB_ADDR_RAM 0x00600000
412#define MV_INITRD_ADDR_RAM 0x01000000
Andre Schwarzc005b932008-06-10 09:13:16 +0200413
Peter Tyser3202d332009-09-16 21:38:10 -0500414#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \
415 then source ${script_addr}; \
416 else source ${script_addr2}; \
Andre Schwarzc005b932008-06-10 09:13:16 +0200417 fi;"
418#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
419
420#define CONFIG_EXTRA_ENV_SETTINGS \
421 "console_nr=0\0" \
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200422 "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" \
Andre Schwarzc005b932008-06-10 09:13:16 +0200423 "stdin=serial\0" \
424 "stdout=serial\0" \
425 "stderr=serial\0" \
426 "fpga=0\0" \
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200427 "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
428 "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
Peter Tyser3202d332009-09-16 21:38:10 -0500429 "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
430 "script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0" \
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200431 "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
432 "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
433 "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
434 "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
435 "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
436 "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \
437 "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
438 "dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
Andre Schwarz5ed546f2008-07-02 18:54:08 +0200439 "mv_version=" U_BOOT_VERSION "\0" \
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200440 "dhcp_client_id=" MK_STR(MV_CI) "\0" \
441 "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
Andre Schwarzc005b932008-06-10 09:13:16 +0200442 "netretry=no\0" \
443 "use_static_ipaddr=no\0" \
444 "static_ipaddr=192.168.90.10\0" \
445 "static_netmask=255.255.255.0\0" \
446 "static_gateway=0.0.0.0\0" \
André Schwarz28887d82009-08-27 14:48:35 +0200447 "initrd_name=uInitrd.mvBL-M7-rfs\0" \
Andre Schwarzc005b932008-06-10 09:13:16 +0200448 "zcip=no\0" \
449 "netboot=yes\0" \
450 "mvtest=Ff\0" \
451 "tried_bootfromflash=no\0" \
452 "tried_bootfromnet=no\0" \
453 "bootfile=mvblm72625.boot\0" \
454 "use_dhcp=yes\0" \
455 "gev_start=yes\0" \
456 "mvbcdma_debug=0\0" \
457 "mvbcia_debug=0\0" \
458 "propdev_debug=0\0" \
459 "gevss_debug=0\0" \
460 "watchdog=0\0" \
461 "usb_dr_mode=host\0" \
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200462 "sensor_cnt=2\0" \
Andre Schwarzc005b932008-06-10 09:13:16 +0200463 ""
464
465#define CONFIG_FPGA_COUNT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200466#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
Andre Schwarzc005b932008-06-10 09:13:16 +0200467#define CONFIG_FPGA_ALTERA
468#define CONFIG_FPGA_CYCLON2
469
470#endif