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stroesea20b27a2004-12-16 18:05:42 +00001/*
2 * (C) Copyright 2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
Stefan Roese82f4c6a2005-08-12 16:52:47 +020035#define CONFIG_IDENT_STRING " $Name: $"
stroesea20b27a2004-12-16 18:05:42 +000036
37#define CONFIG_405EP 1 /* This is a PPC405 CPU */
38#define CONFIG_4xx 1 /* ...member of PPC4xx family */
39#define CONFIG_WUH405 1 /* ...on a WUH405 board */
40
Wolfgang Denk2ae18242010-10-06 09:05:45 +020041#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
42
stroesea20b27a2004-12-16 18:05:42 +000043#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
44#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
45
46#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */
47
48#define CONFIG_BAUDRATE 9600
49#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
50
51#undef CONFIG_BOOTARGS
52#undef CONFIG_BOOTCOMMAND
53
54#define CONFIG_PREBOOT /* enable preboot variable */
55
56#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
stroesea20b27a2004-12-16 18:05:42 +000058
Ben Warren96e21f82008-10-27 23:50:15 -070059#define CONFIG_PPC4xx_EMAC
stroesea20b27a2004-12-16 18:05:42 +000060#define CONFIG_MII 1 /* MII PHY management */
61#define CONFIG_PHY_ADDR 0 /* PHY address */
62#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Ben Warren18cc7af2009-04-28 16:50:53 -070063#define CONFIG_NET_MULTI
stroesea20b27a2004-12-16 18:05:42 +000064
65#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
66
stroesea20b27a2004-12-16 18:05:42 +000067
Jon Loeligera5562902007-07-08 15:31:57 -050068/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050069 * BOOTP options
70 */
71#define CONFIG_BOOTP_BOOTFILESIZE
72#define CONFIG_BOOTP_BOOTPATH
73#define CONFIG_BOOTP_GATEWAY
74#define CONFIG_BOOTP_HOSTNAME
75
76
77/*
Jon Loeligera5562902007-07-08 15:31:57 -050078 * Command line configuration.
79 */
80#include <config_cmd_default.h>
81
82#define CONFIG_CMD_DHCP
83#define CONFIG_CMD_IRQ
84#define CONFIG_CMD_ELF
85#define CONFIG_CMD_NAND
86#define CONFIG_CMD_DATE
87#define CONFIG_CMD_I2C
88#define CONFIG_CMD_MII
89#define CONFIG_CMD_PING
90#define CONFIG_CMD_EEPROM
91
stroesea20b27a2004-12-16 18:05:42 +000092
93#undef CONFIG_WATCHDOG /* watchdog disabled */
94
95#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
stroesea20b27a2004-12-16 18:05:42 +000097
98#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
99
100/*
101 * Miscellaneous configurable options
102 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_LONGHELP /* undef to save memory */
104#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
stroesea20b27a2004-12-16 18:05:42 +0000105
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
107#ifdef CONFIG_SYS_HUSH_PARSER
108#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
stroesea20b27a2004-12-16 18:05:42 +0000109#endif
110
Jon Loeligera5562902007-07-08 15:31:57 -0500111#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000113#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000115#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
117#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
118#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
stroesea20b27a2004-12-16 18:05:42 +0000121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroesea20b27a2004-12-16 18:05:42 +0000123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
125#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
stroesea20b27a2004-12-16 18:05:42 +0000126
Stefan Roese550650d2010-09-20 16:05:31 +0200127#define CONFIG_CONS_INDEX 2 /* Use UART1 */
128#define CONFIG_SYS_NS16550
129#define CONFIG_SYS_NS16550_SERIAL
130#define CONFIG_SYS_NS16550_REG_SIZE 1
131#define CONFIG_SYS_NS16550_CLK get_serial_clock()
132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_BASE_BAUD 691200
stroesea20b27a2004-12-16 18:05:42 +0000135
136/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_BAUDRATE_TABLE \
stroesea20b27a2004-12-16 18:05:42 +0000138 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
139 57600, 115200, 230400, 460800, 921600 }
140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
142#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
stroesea20b27a2004-12-16 18:05:42 +0000143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
stroesea20b27a2004-12-16 18:05:42 +0000145
146#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
147
148#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroesea20b27a2004-12-16 18:05:42 +0000151
152/*-----------------------------------------------------------------------
153 * NAND-FLASH stuff
154 *-----------------------------------------------------------------------
155 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Matthias Fuchsbd84ee42007-07-09 10:10:06 +0200158#define NAND_BIG_DELAY_US 25
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
161#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
162#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
163#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
stroesea20b27a2004-12-16 18:05:42 +0000164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
stroesea20b27a2004-12-16 18:05:42 +0000166
167/*-----------------------------------------------------------------------
168 * PCI stuff
169 *-----------------------------------------------------------------------
170 */
171#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
172#define PCI_HOST_FORCE 1 /* configure as pci host */
173#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
174
175#define CONFIG_PCI /* include pci support */
176#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
177#undef CONFIG_PCI_PNP /* do pci plug-and-play */
178 /* resource configuration */
179
180#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
181
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
183#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
184#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
185#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
186#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
187#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
188#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
189#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
190#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
stroesea20b27a2004-12-16 18:05:42 +0000191
192/*-----------------------------------------------------------------------
193 * Start addresses for the final memory configuration
194 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
stroesea20b27a2004-12-16 18:05:42 +0000196 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_SDRAM_BASE 0x00000000
198#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
199#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
200#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
201#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
stroesea20b27a2004-12-16 18:05:42 +0000202
203/*
204 * For booting Linux, the board info and command line data
205 * have to be in the first 8 MB of memory, since this is
206 * the maximum mapped by the Linux kernel during initialization.
207 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
stroesea20b27a2004-12-16 18:05:42 +0000209/*-----------------------------------------------------------------------
210 * FLASH organization
211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
213#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
stroesea20b27a2004-12-16 18:05:42 +0000214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
216#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
stroesea20b27a2004-12-16 18:05:42 +0000217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
219#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
220#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
stroesea20b27a2004-12-16 18:05:42 +0000221/*
222 * The following defines are added for buggy IOP480 byte interface.
223 * All other boards should use the standard values (CPCI405 etc.)
224 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
226#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
227#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
stroesea20b27a2004-12-16 18:05:42 +0000228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroesea20b27a2004-12-16 18:05:42 +0000230
231#if 0 /* test-only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
233#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
stroesea20b27a2004-12-16 18:05:42 +0000234#endif
235
236/*-----------------------------------------------------------------------
237 * Environment Variable setup
238 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200239#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200240#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
241#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
stroesea20b27a2004-12-16 18:05:42 +0000242 /* total size of a CAT24WC16 is 2048 bytes */
243
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
245#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
stroesea20b27a2004-12-16 18:05:42 +0000246
247/*-----------------------------------------------------------------------
248 * I2C EEPROM (CAT24WC16) for environment
249 */
250#define CONFIG_HARD_I2C /* I2c with hardware support */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200251#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
253#define CONFIG_SYS_I2C_SLAVE 0x7F
stroesea20b27a2004-12-16 18:05:42 +0000254
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
256#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
stroesea20b27a2004-12-16 18:05:42 +0000257/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
259#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
stroesea20b27a2004-12-16 18:05:42 +0000260 /* 16 byte page write mode using*/
261 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
stroesea20b27a2004-12-16 18:05:42 +0000263
stroesea20b27a2004-12-16 18:05:42 +0000264/*
265 * Init Memory Controller:
266 *
267 * BR0/1 and OR0/1 (FLASH)
268 */
269
270#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
271
272/*-----------------------------------------------------------------------
273 * External Bus Controller (EBC) Setup
274 */
275
276/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_EBC_PB0AP 0x92015480
278/*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
279#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
stroesea20b27a2004-12-16 18:05:42 +0000280
281/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_EBC_PB1AP 0x92015480
283#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
stroesea20b27a2004-12-16 18:05:42 +0000284
285/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
287#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
stroesea20b27a2004-12-16 18:05:42 +0000288
289/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
291#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
stroesea20b27a2004-12-16 18:05:42 +0000292
293#define CAN_BA 0xF0000000 /* CAN Base Address */
294#define DUART0_BA 0xF0000400 /* DUART Base Address */
295#define DUART1_BA 0xF0000408 /* DUART Base Address */
296#define DUART2_BA 0xF0000410 /* DUART Base Address */
297#define DUART3_BA 0xF0000418 /* DUART Base Address */
298#define RTC_BA 0xF0000500 /* RTC Base Address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_NAND_BASE 0xF4000000
stroesea20b27a2004-12-16 18:05:42 +0000300
301/*-----------------------------------------------------------------------
302 * FPGA stuff
303 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
305#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
stroesea20b27a2004-12-16 18:05:42 +0000306
307/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
309#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
310#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
311#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
312#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
stroesea20b27a2004-12-16 18:05:42 +0000313
314/*-----------------------------------------------------------------------
315 * Definitions for initial stack pointer and data area (in data cache)
316 */
317/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_TEMP_STACK_OCM 1
stroesea20b27a2004-12-16 18:05:42 +0000319
320/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
322#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
323#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
324#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
stroesea20b27a2004-12-16 18:05:42 +0000325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
327#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
328#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
stroesea20b27a2004-12-16 18:05:42 +0000329
330/*-----------------------------------------------------------------------
331 * Definitions for GPIO setup (PPC405EP specific)
332 *
333 * GPIO0[0] - External Bus Controller BLAST output
334 * GPIO0[1-9] - Instruction trace outputs -> GPIO
335 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
336 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
337 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
338 * GPIO0[24-27] - UART0 control signal inputs/outputs
339 * GPIO0[28-29] - UART1 data signal input/output
340 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
341 */
Stefan Roeseafabb492010-09-12 06:21:37 +0200342#define CONFIG_SYS_GPIO0_OSRL 0x40000550
343#define CONFIG_SYS_GPIO0_OSRH 0x00000110
344#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
345#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_GPIO0_TSRL 0x00000000
Stefan Roeseafabb492010-09-12 06:21:37 +0200347#define CONFIG_SYS_GPIO0_TSRH 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014
stroesea20b27a2004-12-16 18:05:42 +0000349
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
stroesea20b27a2004-12-16 18:05:42 +0000351
352/*
stroesea20b27a2004-12-16 18:05:42 +0000353 * Default speed selection (cpu_plb_opb_ebc) in mhz.
354 * This value will be set if iic boot eprom is disabled.
355 */
356#if 0
357#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
358#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
359#endif
360#if 1
361#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
362#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
363#endif
364#if 0
365#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
366#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
367#endif
368
369#endif /* __CONFIG_H */