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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020031#define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */
wdenkc6097192002-11-03 00:24:07 +000032#define CONFIG_ETHER_PORT_MII /* use two MII ports */
33#define CONFIG_INTEL_LXT97X /* Intel LXT97X phy */
34
35#ifndef __ASSEMBLY__
36#include <galileo/core.h>
37#endif
38
39#include "../board/evb64260/local.h"
40
41#define CONFIG_EVB64260 1 /* this is an EVB64260 board */
42#define CONFIG_ZUMA_V2 1 /* always define this for ZUMA v2 */
43
Wolfgang Denk2ae18242010-10-06 09:05:45 +020044#define CONFIG_SYS_TEXT_BASE 0xfff00000
45
wdenkc6097192002-11-03 00:24:07 +000046/* #define CONFIG_ZUMA_V2_OLD 1 */ /* backwards compat for old V2 board */
47
48#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */
49
50#define CONFIG_ECC /* enable ECC support */
51
52#define CONFIG_750CX /* we have a 750CX/CXe (override local.h) */
53
54/* which initialization functions to call for this board */
55#define CONFIG_MISC_INIT_R
wdenkc837dcb2004-01-20 23:12:12 +000056#define CONFIG_BOARD_EARLY_INIT_F
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_BOARD_ASM_INIT
wdenkc6097192002-11-03 00:24:07 +000058
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_BOARD_NAME "Zuma APv2"
wdenkc6097192002-11-03 00:24:07 +000060
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_HUSH_PARSER
62#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkc6097192002-11-03 00:24:07 +000063
64/*
65 * The following defines let you select what serial you want to use
66 * for your console driver.
67 *
68 * what to do:
69 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070 * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
wdenkc6097192002-11-03 00:24:07 +000071 * to 0 below.
72 *
73 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
74 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
75 */
76#define CONFIG_MPSC
77
78#define CONFIG_MPSC_PORT 0
79
80#define CONFIG_NET_MULTI /* attempt all available adapters */
81
82/* define this if you want to enable GT MAC filtering */
83#define CONFIG_GT_USE_MAC_HASH_TABLE
84
85#if 1
86#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
87#else
88#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
89#endif
90#define CONFIG_ZERO_BOOTDELAY_CHECK
91
92#undef CONFIG_BOOTARGS
93
94#define CONFIG_BOOTCOMMAND \
95 "tftpboot && " \
96 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
97 "ip=$ipaddr:$serverip:$gatewayip:" \
98 "$netmask:$hostname:eth0:none panic=5 && bootm"
99
100#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
wdenkc6097192002-11-03 00:24:07 +0000102
103#undef CONFIG_WATCHDOG /* watchdog disabled */
104#undef CONFIG_ALTIVEC /* undef to disable */
105
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500106/*
107 * BOOTP options
108 */
109#define CONFIG_BOOTP_SUBNETMASK
110#define CONFIG_BOOTP_GATEWAY
111#define CONFIG_BOOTP_HOSTNAME
112#define CONFIG_BOOTP_BOOTPATH
113#define CONFIG_BOOTP_BOOTFILESIZE
wdenkc6097192002-11-03 00:24:07 +0000114
115#define CONFIG_MII /* enable MII commands */
116
Jon Loeligera5562902007-07-08 15:31:57 -0500117
118/*
119 * Command line configuration.
120 */
121#include <config_cmd_default.h>
122
123#define CONFIG_CMD_ASKENV
124#define CONFIG_CMD_BSP
125#define CONFIG_CMD_JFFS2
126#define CONFIG_CMD_MII
127#define CONFIG_CMD_DATE
128
wdenkc6097192002-11-03 00:24:07 +0000129
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200130/*
131 * JFFS2 partitions
132 *
133 */
134/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100135#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200136#define CONFIG_JFFS2_DEV "nor0"
137#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
138#define CONFIG_JFFS2_PART_OFFSET 0x00000000
139
140/* mtdparts command line support */
141/* Note: fake mtd_id used, no linux mtd map file */
142/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100143#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200144#define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2"
145#define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)"
146*/
wdenkc6097192002-11-03 00:24:07 +0000147
wdenkc6097192002-11-03 00:24:07 +0000148/*
149 * Miscellaneous configurable options
150 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_LONGHELP /* undef to save memory */
152#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligera5562902007-07-08 15:31:57 -0500153#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000155#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000157#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
159#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
160#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
163#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */
wdenkc6097192002-11-03 00:24:07 +0000166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
wdenkc6097192002-11-03 00:24:07 +0000168
Wolfgang Denkee80fa72010-06-13 18:38:23 +0200169#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */
wdenkc6097192002-11-03 00:24:07 +0000170
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenkc6097192002-11-03 00:24:07 +0000172
173/*
174 * Low Level Configuration Settings
175 * (address mappings, register initial values, etc.)
176 * You should know what you are doing if you make changes here.
177 */
178
179/*-----------------------------------------------------------------------
180 * Definitions for initial stack pointer and data area
181 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
183#define CONFIG_SYS_INIT_RAM_END 0x1000
184#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
185#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
186#define CONFIG_SYS_INIT_RAM_LOCK
wdenkc6097192002-11-03 00:24:07 +0000187
188
189/*-----------------------------------------------------------------------
190 * Start addresses for the final memory configuration
191 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_SDRAM_BASE 0x00000000
195#define CONFIG_SYS_FLASH_BASE 0xfff00000
196#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
197#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
198#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
199#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
wdenkc6097192002-11-03 00:24:07 +0000200
201/* areas to map different things with the GT in physical space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_DRAM_BANKS 4
203#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
wdenkc6097192002-11-03 00:24:07 +0000204
205/* What to put in the bats. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
wdenkc6097192002-11-03 00:24:07 +0000207
208/* Peripheral Device section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_GT_REGS 0xf8000000 /* later mapped GT_REGS */
210#define CONFIG_SYS_DEV_BASE 0xf0000000
211#define CONFIG_SYS_DEV0_SIZE _64M /* zuma flash @ 0xf000.0000*/
212#define CONFIG_SYS_DEV1_SIZE _8M /* zuma IDE @ 0xf400.0000 */
213#define CONFIG_SYS_DEV2_SIZE _8M /* unused */
214#define CONFIG_SYS_DEV3_SIZE _8M /* unused */
wdenkc6097192002-11-03 00:24:07 +0000215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_DEV0_PAR 0xc498243c
wdenkc6097192002-11-03 00:24:07 +0000217 /* c 4 9 8 2 4 3 c */
218 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
219 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
220 /* 11|00|0100|10 01|100|0 00|10 0|100 0|011 1|100 */
221 /* 3| 0|.... ..| 1| 4 | 0 | 4 | 8 | 7 | 4 */
222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_DEV1_PAR 0xc01b6ac5
wdenkc6097192002-11-03 00:24:07 +0000224 /* c 0 1 b 6 a c 5 */
225 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
226 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
227 /* 11|00|0000|00 01|101|1 01|10 1|010 1|100 0|101 */
228 /* 3| 0|.... ..| 1| 5 | 5 | 5 | 5 | 8 | 5 */
229
230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_8BIT_BOOT_PAR 0xc00b5e7c
wdenkc6097192002-11-03 00:24:07 +0000232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_MPP_CONTROL_0 0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */
234#define CONFIG_SYS_MPP_CONTROL_1 0x00000000 /* GPP[15:12] : GPP[11:8] */
235#define CONFIG_SYS_MPP_CONTROL_2 0x00008888 /* GPP[23:20] : REQ1[1:0] GNT1[1:0] */
236#define CONFIG_SYS_MPP_CONTROL_3 0x00000000 /* GPP[31:28] (int[3:0]) */
wdenkc6097192002-11-03 00:24:07 +0000237 /* GPP[27:24] (27 is int4, rest are GPP) */
238
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_SERIAL_PORT_MUX 0x00001101 /* 11=MPSC1/MPSC0 01=ETH, 0=only MII */
240#define CONFIG_SYS_GPP_LEVEL_CONTROL 0xf8000000 /* interrupt inputs: GPP[31:27] */
wdenkc6097192002-11-03 00:24:07 +0000241
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_SDRAM_CONFIG 0xe4e18200 /* 0x448 */
wdenkc6097192002-11-03 00:24:07 +0000243 /* idmas use buffer 1,1
244 comm use buffer 1
245 pci use buffer 0,0 (pci1->0 pci0->0)
246 cpu use buffer 1 (R*18)
247 normal load (see also ifdef HVL)
248 standard SDRAM (see also ifdef REG)
249 non staggered refresh */
250 /* 31:26 25 23 20 19 18 16 */
251 /* 111001 00 111 0 0 00 1 */
252
253 /* refresh count=0x200
254 phy interleave disable (by default,
255 set later by dram config..)
256 virt interleave enable */
257 /* 15 14 13:0 */
258 /* 1 0 0x200 */
259
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE
261#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
262#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
263#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
wdenkc6097192002-11-03 00:24:07 +0000264
265/*-----------------------------------------------------------------------
266 * PCI stuff
267 */
268
269#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
270#define PCI_HOST_FORCE 1 /* configure as pci host */
271#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
272
273#define CONFIG_PCI /* include pci support */
274#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
275#define CONFIG_PCI_PNP /* do pci plug-and-play */
276
277/* PCI MEMORY MAP section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
279#define CONFIG_SYS_PCI0_MEM_SIZE _128M
280#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
281#define CONFIG_SYS_PCI1_MEM_SIZE _128M
wdenkc6097192002-11-03 00:24:07 +0000282
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
284#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
wdenkc6097192002-11-03 00:24:07 +0000285
286/* PCI I/O MAP section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
288#define CONFIG_SYS_PCI0_IO_SIZE _16M
289#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
290#define CONFIG_SYS_PCI1_IO_SIZE _16M
wdenkc6097192002-11-03 00:24:07 +0000291
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
293#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
294#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
295#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
wdenkc6097192002-11-03 00:24:07 +0000296
297
298/*----------------------------------------------------------------------
299 * Initial BAT mappings
300 */
301
302/* NOTES:
303 * 1) GUARDED and WRITE_THRU not allowed in IBATS
304 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
305 */
306
307/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
309#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
310#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
311#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
wdenkc6097192002-11-03 00:24:07 +0000312
313/* init ram */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
315#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
316#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
317#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
wdenkc6097192002-11-03 00:24:07 +0000318
319/* PCI0, PCI1 memory space (starting at PCI0 base, mapped in one BAT) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
321#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
322#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
323#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000324
325/* GT regs, bootrom, all the devices, PCI I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
327#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
328#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
329#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenkc6097192002-11-03 00:24:07 +0000330
331/*
332 * For booting Linux, the board info and command line data
333 * have to be in the first 8 MB of memory, since this is
334 * the maximum mapped by the Linux kernel during initialization.
335 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000337
338
339/*-----------------------------------------------------------------------
340 * FLASH organization
341 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */
343#define CONFIG_SYS_MAX_FLASH_SECT 130 /* max number of sectors on one chip */
wdenkc6097192002-11-03 00:24:07 +0000344
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE0 /* extra flash at device 0 */
346#define CONFIG_SYS_EXTRA_FLASH_WIDTH 2 /* 16 bit */
wdenkc6097192002-11-03 00:24:07 +0000347
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
349#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
350#define CONFIG_SYS_FLASH_CFI 1
wdenkc6097192002-11-03 00:24:07 +0000351
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200352#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200353#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
354#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
355#define CONFIG_ENV_ADDR (0xfff80000 - CONFIG_ENV_SECT_SIZE)
wdenkc6097192002-11-03 00:24:07 +0000356
357/*-----------------------------------------------------------------------
358 * Cache Configuration
359 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
Jon Loeligera5562902007-07-08 15:31:57 -0500361#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkc6097192002-11-03 00:24:07 +0000363#endif
364
365/*-----------------------------------------------------------------------
366 * L2CR setup -- make sure this is right for your board!
wdenk1d0350e2002-11-11 21:14:20 +0000367 * look in include/74xx_7xx.h for the defines used here
wdenkc6097192002-11-03 00:24:07 +0000368 */
369
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_L2
wdenkc6097192002-11-03 00:24:07 +0000371
372#ifdef CONFIG_750CX
373#define L2_INIT 0
374#else
375#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
376 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
377#endif
378
379#define L2_ENABLE (L2_INIT | L2CR_L2E)
380
381/*------------------------------------------------------------------------
382 * Real time clock
383 */
384#define CONFIG_RTC_DS1302
385
386
387/*------------------------------------------------------------------------
388 * Galileo I2C driver
389 */
390#define CONFIG_GT_I2C
391
wdenkc6097192002-11-03 00:24:07 +0000392#endif /* __CONFIG_H */