blob: de76d36174a06a41d7812a4996aeecd1ea014732 [file] [log] [blame]
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001/*
Zhao Chenhuib813cbe2011-08-24 13:20:04 +08002 * Copyright 2004, 2007, 2009-2011 Freescale Semiconductor, Inc.
Jon Loeligerd9b94f22005-07-25 14:05:07 -05003 *
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
Jon Loeligerd9b94f22005-07-25 14:05:07 -05007 */
8
9#include <common.h>
10#include <pci.h>
11#include <asm/processor.h>
Jon Loeligere31d2c12008-03-18 13:51:06 -050012#include <asm/mmu.h>
Jon Loeligerd9b94f22005-07-25 14:05:07 -050013#include <asm/immap_85xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050014#include <asm/fsl_pci.h>
York Sun5614e712013-09-30 09:22:09 -070015#include <fsl_ddr_sdram.h>
Kumar Gala5d27e022010-12-15 04:55:20 -060016#include <asm/fsl_serdes.h>
Andy Fleming09f3e092006-09-13 10:34:18 -050017#include <miiphy.h>
Kumar Galab90d2542007-11-29 00:11:44 -060018#include <libfdt.h>
19#include <fdt_support.h>
chenhui zhaod3701222011-09-06 16:41:18 +000020#include <tsec.h>
21#include <fsl_mdio.h>
22#include <netdev.h>
Jon Loeligerd9b94f22005-07-25 14:05:07 -050023
24#include "../common/cadmus.h"
25#include "../common/eeprom.h"
Matthew McClintockbf1dfff2006-06-28 10:46:13 -050026#include "../common/via.h"
Jon Loeligerd9b94f22005-07-25 14:05:07 -050027
Jon Loeligerd9b94f22005-07-25 14:05:07 -050028void local_bus_init(void);
Jon Loeligerd9b94f22005-07-25 14:05:07 -050029
Jon Loeligerd9b94f22005-07-25 14:05:07 -050030int checkboard (void)
31{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
33 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
Jon Loeligerd9b94f22005-07-25 14:05:07 -050034
35 /* PCI slot in USER bits CSR[6:7] by convention. */
36 uint pci_slot = get_pci_slot ();
37
Jon Loeligerd9b94f22005-07-25 14:05:07 -050038 uint cpu_board_rev = get_cpu_board_revision ();
39
chenhui zhaofff80972011-10-13 13:40:59 +080040 puts("Board: MPC8548CDS");
41 printf(" Carrier Rev: 0x%02x, PCI Slot %d\n",
42 get_board_version(), pci_slot);
43 printf(" Daughtercard Rev: %d.%d (0x%04x)\n",
Jon Loeligerd9b94f22005-07-25 14:05:07 -050044 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
45 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
Jon Loeligerd9b94f22005-07-25 14:05:07 -050046 /*
47 * Initialize local bus.
48 */
49 local_bus_init ();
50
Jon Loeligerd9b94f22005-07-25 14:05:07 -050051 /*
52 * Hack TSEC 3 and 4 IO voltages.
53 */
54 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
55
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050056 ecm->eedr = 0xffffffff; /* clear ecm errors */
57 ecm->eeer = 0xffffffff; /* enable ecm errors */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050058 return 0;
59}
60
Jon Loeligerd9b94f22005-07-25 14:05:07 -050061/*
62 * Initialize Local Bus
63 */
64void
65local_bus_init(void)
66{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Becky Brucef51cdaf2010-06-17 11:37:20 -050068 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Jon Loeligerd9b94f22005-07-25 14:05:07 -050069
70 uint clkdiv;
Jon Loeligerd9b94f22005-07-25 14:05:07 -050071 sys_info_t sysinfo;
72
73 get_sys_info(&sysinfo);
Trent Piephoa5d212a2008-12-03 15:16:34 -080074 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
Jon Loeligerd9b94f22005-07-25 14:05:07 -050075
76 gur->lbiuiplldcr1 = 0x00078080;
77 if (clkdiv == 16) {
78 gur->lbiuiplldcr0 = 0x7c0f1bf0;
79 } else if (clkdiv == 8) {
80 gur->lbiuiplldcr0 = 0x6c0f1bf0;
81 } else if (clkdiv == 4) {
82 gur->lbiuiplldcr0 = 0x5c0f1bf0;
83 }
84
85 lbc->lcrr |= 0x00030000;
86
87 asm("sync;isync;msync");
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050088
89 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
90 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050091}
92
93/*
94 * Initialize SDRAM memory on the Local Bus.
95 */
Becky Bruce70961ba2010-12-17 17:17:57 -060096void lbc_sdram_init(void)
Jon Loeligerd9b94f22005-07-25 14:05:07 -050097{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
Jon Loeligerd9b94f22005-07-25 14:05:07 -050099
100 uint idx;
Becky Brucef51cdaf2010-06-17 11:37:20 -0500101 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500103 uint lsdmr_common;
104
Becky Bruce7ea38712010-12-17 17:17:59 -0600105 puts("LBC SDRAM: ");
106 print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
chenhui zhaoa6d0bfa2011-09-06 16:41:14 +0000107 "\n");
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500108
109 /*
110 * Setup SDRAM Base and Option Registers
111 */
Becky Brucef51cdaf2010-06-17 11:37:20 -0500112 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
113 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500115 asm("msync");
116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
118 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500119 asm("msync");
120
121 /*
122 * MPC8548 uses "new" 15-16 style addressing.
123 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500125 lsdmr_common |= LSDMR_BSMA1516;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500126
127 /*
128 * Issue PRECHARGE ALL command.
129 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500130 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500131 asm("sync;msync");
132 *sdram_addr = 0xff;
133 ppcDcbf((unsigned long) sdram_addr);
134 udelay(100);
135
136 /*
137 * Issue 8 AUTO REFRESH commands.
138 */
139 for (idx = 0; idx < 8; idx++) {
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500140 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500141 asm("sync;msync");
142 *sdram_addr = 0xff;
143 ppcDcbf((unsigned long) sdram_addr);
144 udelay(100);
145 }
146
147 /*
148 * Issue 8 MODE-set command.
149 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500150 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500151 asm("sync;msync");
152 *sdram_addr = 0xff;
153 ppcDcbf((unsigned long) sdram_addr);
154 udelay(100);
155
156 /*
157 * Issue NORMAL OP command.
158 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500159 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500160 asm("sync;msync");
161 *sdram_addr = 0xff;
162 ppcDcbf((unsigned long) sdram_addr);
163 udelay(200); /* Overkill. Must wait > 200 bus cycles */
164
165#endif /* enable SDRAM init */
166}
167
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500168#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500169/* For some reason the Tundra PCI bridge shows up on itself as a
170 * different device. Work around that by refusing to configure it.
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500171 */
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500172void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500173
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500174static struct pci_config_table pci_mpc85xxcds_config_table[] = {
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500175 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700176 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
177 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
Andy Flemingffa621a2007-02-24 01:08:13 -0600178 mpc85xx_config_via_usbide, {0,0,0}},
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700179 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
180 mpc85xx_config_via_usb, {0,0,0}},
181 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
182 mpc85xx_config_via_usb2, {0,0,0}},
183 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
Andy Flemingffa621a2007-02-24 01:08:13 -0600184 mpc85xx_config_via_power, {0,0,0}},
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700185 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
186 mpc85xx_config_via_ac97, {0,0,0}},
Andy Flemingffa621a2007-02-24 01:08:13 -0600187 {},
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500188};
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500189
Zhao Chenhuib813cbe2011-08-24 13:20:04 +0800190static struct pci_controller pci1_hose;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500191#endif /* CONFIG_PCI */
192
Kumar Gala7b626882009-11-04 11:15:29 -0600193void pci_init_board(void)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500194{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Kumar Galaf5fa8f32010-12-17 10:21:22 -0600196 struct fsl_pci_info pci_info;
Kumar Gala7b626882009-11-04 11:15:29 -0600197 u32 devdisr, pordevsr, io_sel;
198 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
199 int first_free_busno = 0;
chenhui zhao568336e2011-09-15 14:52:34 +0800200 char buf[32];
Kumar Gala7b626882009-11-04 11:15:29 -0600201
202 devdisr = in_be32(&gur->devdisr);
203 pordevsr = in_be32(&gur->pordevsr);
204 porpllsr = in_be32(&gur->porpllsr);
205 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
206
207 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500208
209#ifdef CONFIG_PCI1
Kumar Gala7b626882009-11-04 11:15:29 -0600210 pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
211 pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
212 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
213 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500214
Kumar Gala7b626882009-11-04 11:15:29 -0600215 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
Kumar Galaf5fa8f32010-12-17 10:21:22 -0600216 SET_STD_PCI_INFO(pci_info, 1);
217 set_next_law(pci_info.mem_phys,
218 law_size_bits(pci_info.mem_size), pci_info.law);
219 set_next_law(pci_info.io_phys,
220 law_size_bits(pci_info.io_size), pci_info.law);
221
222 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
chenhui zhaoa6d0bfa2011-09-06 16:41:14 +0000223 printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500224 (pci_32) ? 32 : 64,
chenhui zhao568336e2011-09-15 14:52:34 +0800225 strmhz(buf, pci_speed),
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500226 pci_clk_sel ? "sync" : "async",
227 pci_agent ? "agent" : "host",
Kumar Gala7b626882009-11-04 11:15:29 -0600228 pci_arb ? "arbiter" : "external-arbiter",
Kumar Galaf5fa8f32010-12-17 10:21:22 -0600229 pci_info.regs);
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500230
Zhao Chenhuib813cbe2011-08-24 13:20:04 +0800231 pci1_hose.config_table = pci_mpc85xxcds_config_table;
Kumar Galaf5fa8f32010-12-17 10:21:22 -0600232 first_free_busno = fsl_pci_init_port(&pci_info,
Kumar Gala7b626882009-11-04 11:15:29 -0600233 &pci1_hose, first_free_busno);
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500234
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500235#ifdef CONFIG_PCIX_CHECK
Kumar Gala7b626882009-11-04 11:15:29 -0600236 if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500237 /* PCI-X init */
238 if (CONFIG_SYS_CLK_FREQ < 66000000)
239 printf("PCI-X will only work at 66 MHz\n");
240
241 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
242 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
243 pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
244 }
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500245#endif
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500246 } else {
chenhui zhaoa6d0bfa2011-09-06 16:41:14 +0000247 printf("PCI1: disabled\n");
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500248 }
Kumar Gala7b626882009-11-04 11:15:29 -0600249
250 puts("\n");
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500251#else
Kumar Gala7b626882009-11-04 11:15:29 -0600252 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500253#endif
254
255#ifdef CONFIG_PCI2
256{
Kumar Gala7b626882009-11-04 11:15:29 -0600257 uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500258 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
259 if (pci_dual) {
Peter Tyser8ca78f22010-10-29 17:59:24 -0500260 printf("PCI2: 32 bit, 66 MHz, %s\n",
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500261 pci2_clk_sel ? "sync" : "async");
262 } else {
Peter Tyser8ca78f22010-10-29 17:59:24 -0500263 printf("PCI2: disabled\n");
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500264 }
265}
266#else
Kumar Gala7b626882009-11-04 11:15:29 -0600267 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500268#endif /* CONFIG_PCI2 */
269
Kumar Galaf5fa8f32010-12-17 10:21:22 -0600270 fsl_pcie_init_board(first_free_busno);
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500271}
Andy Fleming09f3e092006-09-13 10:34:18 -0500272
chenhui zhaod3701222011-09-06 16:41:18 +0000273void configure_rgmii(void)
Andy Fleming09f3e092006-09-13 10:34:18 -0500274{
Jon Loeligerf5012822006-10-20 15:54:34 -0500275 unsigned short temp;
Andy Fleming09f3e092006-09-13 10:34:18 -0500276
277 /* Change the resistors for the PHY */
278 /* This is needed to get the RGMII working for the 1.3+
279 * CDS cards */
280 if (get_board_version() == 0x13) {
chenhui zhaod3701222011-09-06 16:41:18 +0000281 miiphy_write(DEFAULT_MII_NAME,
Andy Fleming09f3e092006-09-13 10:34:18 -0500282 TSEC1_PHY_ADDR, 29, 18);
283
chenhui zhaod3701222011-09-06 16:41:18 +0000284 miiphy_read(DEFAULT_MII_NAME,
Andy Fleming09f3e092006-09-13 10:34:18 -0500285 TSEC1_PHY_ADDR, 30, &temp);
286
287 temp = (temp & 0xf03f);
288 temp |= 2 << 9; /* 36 ohm */
289 temp |= 2 << 6; /* 39 ohm */
290
chenhui zhaod3701222011-09-06 16:41:18 +0000291 miiphy_write(DEFAULT_MII_NAME,
Andy Fleming09f3e092006-09-13 10:34:18 -0500292 TSEC1_PHY_ADDR, 30, temp);
293
chenhui zhaod3701222011-09-06 16:41:18 +0000294 miiphy_write(DEFAULT_MII_NAME,
Andy Fleming09f3e092006-09-13 10:34:18 -0500295 TSEC1_PHY_ADDR, 29, 3);
296
chenhui zhaod3701222011-09-06 16:41:18 +0000297 miiphy_write(DEFAULT_MII_NAME,
Andy Fleming09f3e092006-09-13 10:34:18 -0500298 TSEC1_PHY_ADDR, 30, 0x8000);
299 }
300
chenhui zhaod3701222011-09-06 16:41:18 +0000301 return;
Andy Fleming09f3e092006-09-13 10:34:18 -0500302}
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500303
chenhui zhaod3701222011-09-06 16:41:18 +0000304int board_eth_init(bd_t *bis)
305{
Bin Meng1adc0952016-01-11 22:41:15 -0800306#ifdef CONFIG_TSEC_ENET
chenhui zhaod3701222011-09-06 16:41:18 +0000307 struct fsl_pq_mdio_info mdio_info;
308 struct tsec_info_struct tsec_info[4];
309 int num = 0;
310
311#ifdef CONFIG_TSEC1
312 SET_STD_TSEC_INFO(tsec_info[num], 1);
313 num++;
314#endif
315#ifdef CONFIG_TSEC2
316 SET_STD_TSEC_INFO(tsec_info[num], 2);
317 num++;
318#endif
319#ifdef CONFIG_TSEC3
320 /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */
321 if (get_board_version() >= 0x13) {
322 SET_STD_TSEC_INFO(tsec_info[num], 3);
323 tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
324 num++;
325 }
326#endif
327#ifdef CONFIG_TSEC4
328 /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */
329 if (get_board_version() >= 0x13) {
330 SET_STD_TSEC_INFO(tsec_info[num], 4);
331 tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
332 num++;
333 }
334#endif
335
336 if (!num) {
337 printf("No TSECs initialized\n");
338
339 return 0;
340 }
341
342 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
343 mdio_info.name = DEFAULT_MII_NAME;
344 fsl_pq_mdio_init(bis, &mdio_info);
345
346 tsec_eth_init(bis, tsec_info, num);
347 configure_rgmii();
Bin Meng1adc0952016-01-11 22:41:15 -0800348#endif
chenhui zhaod3701222011-09-06 16:41:18 +0000349
350 return pci_eth_init(bis);
351}
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500352
Kumar Galab90d2542007-11-29 00:11:44 -0600353#if defined(CONFIG_OF_BOARD_SETUP)
Kumar Gala2dba0de2008-10-21 08:28:33 -0500354void ft_pci_setup(void *blob, bd_t *bd)
355{
Kumar Gala6525d512010-07-08 22:37:44 -0500356 FT_FSL_PCI_SETUP;
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500357}
358#endif