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Vikas Manocha9fa32b12014-11-18 10:42:22 -08001/*
2 * (C) Copyright 2014
3 * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
Simon Glass9d922452017-05-17 17:18:03 -06009#include <dm.h>
Vikas Manocha9fa32b12014-11-18 10:42:22 -080010#include <miiphy.h>
11#include <asm/arch/stv0991_periph.h>
12#include <asm/arch/stv0991_defs.h>
Vikas Manocha2ce4eaf2014-11-18 10:42:23 -080013#include <asm/arch/hardware.h>
14#include <asm/arch/gpio.h>
15#include <netdev.h>
16#include <asm/io.h>
Vikas Manocha39e47952014-12-01 12:27:54 -080017#include <dm/platform_data/serial_pl01x.h>
Vikas Manocha9fa32b12014-11-18 10:42:22 -080018
19DECLARE_GLOBAL_DATA_PTR;
20
Vikas Manocha2ce4eaf2014-11-18 10:42:23 -080021struct gpio_regs *const gpioa_regs =
22 (struct gpio_regs *) GPIOA_BASE_ADDR;
23
Vikas Manochae0320b72015-05-03 14:10:35 -070024#ifndef CONFIG_OF_CONTROL
Vikas Manocha39e47952014-12-01 12:27:54 -080025static const struct pl01x_serial_platdata serial_platdata = {
26 .base = 0x80406000,
27 .type = TYPE_PL011,
28 .clock = 2700 * 1000,
29};
30
31U_BOOT_DEVICE(stv09911_serials) = {
32 .name = "serial_pl01x",
33 .platdata = &serial_platdata,
34};
Vikas Manochae0320b72015-05-03 14:10:35 -070035#endif
Vikas Manocha39e47952014-12-01 12:27:54 -080036
Vikas Manocha9fa32b12014-11-18 10:42:22 -080037#ifdef CONFIG_SHOW_BOOT_PROGRESS
38void show_boot_progress(int progress)
39{
40 printf("%i\n", progress);
41}
42#endif
43
Vikas Manocha2ce4eaf2014-11-18 10:42:23 -080044void enable_eth_phy(void)
45{
46 /* Set GPIOA_06 pad HIGH (Appli board)*/
47 writel(readl(&gpioa_regs->dir) | 0x40, &gpioa_regs->dir);
48 writel(readl(&gpioa_regs->data) | 0x40, &gpioa_regs->data);
49}
50int board_eth_enable(void)
51{
52 stv0991_pinmux_config(ETH_GPIOB_10_31_C_0_4);
53 clock_setup(ETH_CLOCK_CFG);
54 enable_eth_phy();
55 return 0;
56}
57
Vikas Manocha54afb502015-07-02 18:29:40 -070058int board_qspi_enable(void)
59{
60 stv0991_pinmux_config(QSPI_CS_CLK_PAD);
61 clock_setup(QSPI_CLOCK_CFG);
62 return 0;
63}
64
Vikas Manocha9fa32b12014-11-18 10:42:22 -080065/*
66 * Miscellaneous platform dependent initialisations
67 */
68int board_init(void)
69{
Vikas Manocha2ce4eaf2014-11-18 10:42:23 -080070 board_eth_enable();
Vikas Manocha54afb502015-07-02 18:29:40 -070071 board_qspi_enable();
Vikas Manocha9fa32b12014-11-18 10:42:22 -080072 return 0;
73}
74
75int board_uart_init(void)
76{
77 stv0991_pinmux_config(UART_GPIOC_30_31);
78 clock_setup(UART_CLOCK_CFG);
79 return 0;
80}
Vikas Manocha2ce4eaf2014-11-18 10:42:23 -080081
Vikas Manocha9fa32b12014-11-18 10:42:22 -080082#ifdef CONFIG_BOARD_EARLY_INIT_F
83int board_early_init_f(void)
84{
85 board_uart_init();
86 return 0;
87}
88#endif
89
90int dram_init(void)
91{
92 gd->ram_size = PHYS_SDRAM_1_SIZE;
93 return 0;
94}
95
Simon Glass76b00ac2017-03-31 08:40:32 -060096int dram_init_banksize(void)
Vikas Manocha9fa32b12014-11-18 10:42:22 -080097{
98 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
99 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
Simon Glass76b00ac2017-03-31 08:40:32 -0600100
101 return 0;
Vikas Manocha9fa32b12014-11-18 10:42:22 -0800102}
Vikas Manocha2ce4eaf2014-11-18 10:42:23 -0800103
104#ifdef CONFIG_CMD_NET
105int board_eth_init(bd_t *bis)
106{
107 int ret = 0;
108
Simon Glassef48f6d2015-04-05 16:07:34 -0600109#if defined(CONFIG_ETH_DESIGNWARE)
Vikas Manocha2ce4eaf2014-11-18 10:42:23 -0800110 u32 interface = PHY_INTERFACE_MODE_MII;
111 if (designware_initialize(GMAC_BASE_ADDR, interface) >= 0)
112 ret++;
113#endif
114 return ret;
115}
116#endif